[net-next-2.6.git] / drivers / gpio / stmpe-gpio.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mfd/stmpe.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

#define CACHE_NR_REGS	3
#define CACHE_NR_BANKS	(STMPE_NR_GPIOS / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;

	int irq_base;
	unsigned norequest_mask;

	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct stmpe_gpio, chip);
}

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return ret & mask;
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);

	return stmpe_gpio->irq_base + offset;
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.to_irq			= stmpe_gpio_to_irq,
	.request		= stmpe_gpio_request,
	.can_sleep		= 1,
};

static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
{
	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	int offset = irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	if (type == IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(unsigned int irq)
{
	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
{
	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[] = {
		[REG_RE]	= STMPE_IDX_GPRER_LSB,
		[REG_FE]	= STMPE_IDX_GPFER_LSB,
		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(unsigned int irq)
{
	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	int offset = irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(unsigned int irq)
{
	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	int offset = irq - stmpe_gpio->irq_base;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.bus_lock		= stmpe_gpio_irq_lock,
	.bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.mask			= stmpe_gpio_irq_mask,
	.unmask			= stmpe_gpio_irq_unmask,
	.set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;

			handle_nested_irq(stmpe_gpio->irq_base + line);
			stat &= ~(1 << bit);
		}

		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
		stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
				status[i]);
	}

	return IRQ_HANDLED;
}

static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
{
	int base = stmpe_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
		set_irq_chip_data(irq, stmpe_gpio);
		set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_nested_thread(irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(irq, IRQF_VALID);
#else
		set_irq_noprobe(irq);
#endif
	}

	return 0;
}

static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
{
	int base = stmpe_gpio->irq_base;
	int irq;

	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
#ifdef CONFIG_ARM
		set_irq_flags(irq, 0);
#endif
		set_irq_chip_and_handler(irq, NULL, NULL);
		set_irq_chip_data(irq, NULL);
	}
}

static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct stmpe_gpio_platform_data *pdata;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq;

	pdata = stmpe->pdata->gpio;
	if (!pdata)
		return -ENODEV;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;

	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.dev = &pdev->dev;
	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;

	stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		return ret;

	ret = stmpe_gpio_irq_init(stmpe_gpio);
	if (ret)
		goto out_free;

	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
				   "stmpe-gpio", stmpe_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		goto out_removeirq;
	}

	ret = gpiochip_add(&stmpe_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_freeirq;
	}

	if (pdata && pdata->setup)
		pdata->setup(stmpe, stmpe_gpio->chip.base);

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_freeirq:
	free_irq(irq, stmpe_gpio);
out_removeirq:
	stmpe_gpio_irq_remove(stmpe_gpio);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
{
	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	int irq = platform_get_irq(pdev, 0);
	int ret;

	if (pdata && pdata->remove)
		pdata->remove(stmpe, stmpe_gpio->chip.base);

	ret = gpiochip_remove(&stmpe_gpio->chip);
	if (ret < 0) {
		dev_err(stmpe_gpio->dev,
			"unable to remove gpiochip: %d\n", ret);
		return ret;
	}

	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);

	free_irq(irq, stmpe_gpio);
	stmpe_gpio_irq_remove(stmpe_gpio);
	platform_set_drvdata(pdev, NULL);
	kfree(stmpe_gpio);

	return 0;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver.name	= "stmpe-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= stmpe_gpio_probe,
	.remove		= __devexit_p(stmpe_gpio_remove),
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);

static void __exit stmpe_gpio_exit(void)
{
	platform_driver_unregister(&stmpe_gpio_driver);
}
module_exit(stmpe_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("STMPExxxx GPIO driver");
MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
	12	#include <linux/gpio.h>
	13	#include <linux/irq.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/mfd/stmpe.h>
	16
	17	/*
	18	* These registers are modified under the irq bus lock and cached to avoid
	19	* unnecessary writes in bus_sync_unlock.
	20	*/
	21	enum { REG_RE, REG_FE, REG_IE };
	22
	23	#define CACHE_NR_REGS 3
	24	#define CACHE_NR_BANKS (STMPE_NR_GPIOS / 8)
	25
	26	struct stmpe_gpio {
	27	struct gpio_chip chip;
	28	struct stmpe *stmpe;
	29	struct device *dev;
	30	struct mutex irq_lock;
	31
	32	int irq_base;
b8e9cf0b	33	unsigned norequest_mask;
03f822f5 RV	34
	35	/* Caches of interrupt control registers for bus_lock */
	36	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	37	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	};
	39
	40	static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	41	{
	42	return container_of(chip, struct stmpe_gpio, chip);
	43	}
	44
	45	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	46	{
	47	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	48	struct stmpe *stmpe = stmpe_gpio->stmpe;
	49	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	50	u8 mask = 1 << (offset % 8);
	51	int ret;
	52
	53	ret = stmpe_reg_read(stmpe, reg);
	54	if (ret < 0)
	55	return ret;
	56
	57	return ret & mask;
	58	}
	59
	60	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	61	{
	62	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	63	struct stmpe *stmpe = stmpe_gpio->stmpe;
	64	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	65	u8 reg = stmpe->regs[which] - (offset / 8);
	66	u8 mask = 1 << (offset % 8);
	67
	68	stmpe_reg_write(stmpe, reg, mask);
	69	}
	70
	71	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	72	unsigned offset, int val)
	73	{
	74	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	75	struct stmpe *stmpe = stmpe_gpio->stmpe;
	76	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	77	u8 mask = 1 << (offset % 8);
	78
	79	stmpe_gpio_set(chip, offset, val);
	80
	81	return stmpe_set_bits(stmpe, reg, mask, mask);
	82	}
	83
	84	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	85	unsigned offset)
	86	{
	87	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	88	struct stmpe *stmpe = stmpe_gpio->stmpe;
	89	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	90	u8 mask = 1 << (offset % 8);
	91
	92	return stmpe_set_bits(stmpe, reg, mask, 0);
	93	}
	94
	95	static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	96	{
	97	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
98
99	return stmpe_gpio->irq_base + offset;
100	}
101
102	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
103	{
104	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
105	struct stmpe *stmpe = stmpe_gpio->stmpe;
106
b8e9cf0b WS	107	if (stmpe_gpio->norequest_mask & (1 << offset))
	108	return -EINVAL;
	109
03f822f5 RV	110	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	111	}
	112
	113	static struct gpio_chip template_chip = {
	114	.label = "stmpe",
	115	.owner = THIS_MODULE,
	116	.direction_input = stmpe_gpio_direction_input,
	117	.get = stmpe_gpio_get,
	118	.direction_output = stmpe_gpio_direction_output,
	119	.set = stmpe_gpio_set,
	120	.to_irq = stmpe_gpio_to_irq,
	121	.request = stmpe_gpio_request,
	122	.can_sleep = 1,
	123	};
	124
	125	static int stmpe_gpio_irq_set_type(unsigned int irq, unsigned int type)
	126	{
	127	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	128	int offset = irq - stmpe_gpio->irq_base;
	129	int regoffset = offset / 8;
	130	int mask = 1 << (offset % 8);
	131
	132	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	133	return -EINVAL;
	134
	135	if (type == IRQ_TYPE_EDGE_RISING)
	136	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	137	else
	138	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	139
	140	if (type == IRQ_TYPE_EDGE_FALLING)
	141	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	142	else
	143	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	144
	145	return 0;
	146	}
	147
	148	static void stmpe_gpio_irq_lock(unsigned int irq)
	149	{
	150	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	151
	152	mutex_lock(&stmpe_gpio->irq_lock);
	153	}
	154
	155	static void stmpe_gpio_irq_sync_unlock(unsigned int irq)
	156	{
	157	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
	158	struct stmpe *stmpe = stmpe_gpio->stmpe;
	159	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	160	static const u8 regmap[] = {
	161	[REG_RE] = STMPE_IDX_GPRER_LSB,
	162	[REG_FE] = STMPE_IDX_GPFER_LSB,
	163	[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	164	};
	165	int i, j;
	166
	167	for (i = 0; i < CACHE_NR_REGS; i++) {
	168	for (j = 0; j < num_banks; j++) {
	169	u8 old = stmpe_gpio->oldregs[i][j];
	170	u8 new = stmpe_gpio->regs[i][j];
	171
	172	if (new == old)
	173	continue;
174
175	stmpe_gpio->oldregs[i][j] = new;
176	stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
177	}
178	}
179
180	mutex_unlock(&stmpe_gpio->irq_lock);
181	}
182
183	static void stmpe_gpio_irq_mask(unsigned int irq)
184	{
185	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
186	int offset = irq - stmpe_gpio->irq_base;
187	int regoffset = offset / 8;
188	int mask = 1 << (offset % 8);
189
190	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
191	}
192
193	static void stmpe_gpio_irq_unmask(unsigned int irq)
194	{
195	struct stmpe_gpio *stmpe_gpio = get_irq_chip_data(irq);
196	int offset = irq - stmpe_gpio->irq_base;
197	int regoffset = offset / 8;
198	int mask = 1 << (offset % 8);
199
200	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
201	}
202
203	static struct irq_chip stmpe_gpio_irq_chip = {
204	.name = "stmpe-gpio",
205	.bus_lock = stmpe_gpio_irq_lock,
206	.bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
207	.mask = stmpe_gpio_irq_mask,
208	.unmask = stmpe_gpio_irq_unmask,
209	.set_type = stmpe_gpio_irq_set_type,
210	};
211
212	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
213	{
214	struct stmpe_gpio *stmpe_gpio = dev;
215	struct stmpe *stmpe = stmpe_gpio->stmpe;
216	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
217	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
218	u8 status[num_banks];
219	int ret;
220	int i;
221
222	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
223	if (ret < 0)
224	return IRQ_NONE;
225
226	for (i = 0; i < num_banks; i++) {
227	int bank = num_banks - i - 1;
228	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
229	unsigned int stat = status[i];
230
231	stat &= enabled;
232	if (!stat)
233	continue;
234
235	while (stat) {
236	int bit = __ffs(stat);
237	int line = bank * 8 + bit;
238
239	handle_nested_irq(stmpe_gpio->irq_base + line);
240	stat &= ~(1 << bit);
241	}
242
243	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
244	stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
245	status[i]);
246	}
247
248	return IRQ_HANDLED;
249	}
250
251	static int __devinit stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio)
252	{
253	int base = stmpe_gpio->irq_base;
254	int irq;
255
256	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
257	set_irq_chip_data(irq, stmpe_gpio);
258	set_irq_chip_and_handler(irq, &stmpe_gpio_irq_chip,
259	handle_simple_irq);
260	set_irq_nested_thread(irq, 1);
261	#ifdef CONFIG_ARM
262	set_irq_flags(irq, IRQF_VALID);
263	#else
264	set_irq_noprobe(irq);
265	#endif
266	}
267
268	return 0;
269	}
270
271	static void stmpe_gpio_irq_remove(struct stmpe_gpio *stmpe_gpio)
272	{
273	int base = stmpe_gpio->irq_base;
274	int irq;
275
276	for (irq = base; irq < base + stmpe_gpio->chip.ngpio; irq++) {
277	#ifdef CONFIG_ARM
278	set_irq_flags(irq, 0);
279	#endif
280	set_irq_chip_and_handler(irq, NULL, NULL);
281	set_irq_chip_data(irq, NULL);
282	}
283	}
284
285	static int __devinit stmpe_gpio_probe(struct platform_device *pdev)
286	{
287	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
288	struct stmpe_gpio_platform_data *pdata;
289	struct stmpe_gpio *stmpe_gpio;
290	int ret;
291	int irq;
292
293	pdata = stmpe->pdata->gpio;
294	if (!pdata)
295	return -ENODEV;
296
297	irq = platform_get_irq(pdev, 0);
298	if (irq < 0)
299	return irq;
300
301	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
302	if (!stmpe_gpio)
303	return -ENOMEM;
304
305	mutex_init(&stmpe_gpio->irq_lock);
306
307	stmpe_gpio->dev = &pdev->dev;
308	stmpe_gpio->stmpe = stmpe;
b8e9cf0b	309	stmpe_gpio->norequest_mask = pdata ? pdata->norequest_mask : 0;
03f822f5 RV	310
	311	stmpe_gpio->chip = template_chip;
	312	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	313	stmpe_gpio->chip.dev = &pdev->dev;
	314	stmpe_gpio->chip.base = pdata ? pdata->gpio_base : -1;
	315
	316	stmpe_gpio->irq_base = stmpe->irq_base + STMPE_INT_GPIO(0);
	317
	318	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	319	if (ret)
	320	return ret;
	321
	322	ret = stmpe_gpio_irq_init(stmpe_gpio);
	323	if (ret)
	324	goto out_free;
	325
	326	ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq, IRQF_ONESHOT,
	327	"stmpe-gpio", stmpe_gpio);
	328	if (ret) {
	329	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
	330	goto out_removeirq;
	331	}
	332
	333	ret = gpiochip_add(&stmpe_gpio->chip);
	334	if (ret) {
	335	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	336	goto out_freeirq;
	337	}
	338
	339	if (pdata && pdata->setup)
	340	pdata->setup(stmpe, stmpe_gpio->chip.base);
	341
	342	platform_set_drvdata(pdev, stmpe_gpio);
	343
	344	return 0;
	345
	346	out_freeirq:
	347	free_irq(irq, stmpe_gpio);
	348	out_removeirq:
	349	stmpe_gpio_irq_remove(stmpe_gpio);
	350	out_free:
	351	kfree(stmpe_gpio);
	352	return ret;
	353	}
	354
	355	static int __devexit stmpe_gpio_remove(struct platform_device *pdev)
	356	{
	357	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	358	struct stmpe *stmpe = stmpe_gpio->stmpe;
	359	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
	360	int irq = platform_get_irq(pdev, 0);
	361	int ret;
	362
	363	if (pdata && pdata->remove)
	364	pdata->remove(stmpe, stmpe_gpio->chip.base);
	365
	366	ret = gpiochip_remove(&stmpe_gpio->chip);
	367	if (ret < 0) {
	368	dev_err(stmpe_gpio->dev,
	369	"unable to remove gpiochip: %d\n", ret);
	370	return ret;
	371	}
	372
	373	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
374
375	free_irq(irq, stmpe_gpio);
376	stmpe_gpio_irq_remove(stmpe_gpio);
377	platform_set_drvdata(pdev, NULL);
378	kfree(stmpe_gpio);
379
380	return 0;
381	}
382
383	static struct platform_driver stmpe_gpio_driver = {
384	.driver.name = "stmpe-gpio",
385	.driver.owner = THIS_MODULE,
386	.probe = stmpe_gpio_probe,
387	.remove = __devexit_p(stmpe_gpio_remove),
388	};
389
390	static int __init stmpe_gpio_init(void)
391	{
392	return platform_driver_register(&stmpe_gpio_driver);
393	}
394	subsys_initcall(stmpe_gpio_init);
395
396	static void __exit stmpe_gpio_exit(void)
397	{
398	platform_driver_unregister(&stmpe_gpio_driver);
399	}
400	module_exit(stmpe_gpio_exit);
401
402	MODULE_LICENSE("GPL v2");
403	MODULE_DESCRIPTION("STMPExxxx GPIO driver");
404	MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");