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edac: mpc85xx: fix coldplug/hotplug module autoloading
[net-next-2.6.git] / drivers / edac / mpc85xx_edac.c
CommitLineData
a9a753d5
DJ		 1/*
2 * Freescale MPC85xx Memory Controller kenel module
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12#include <linux/module.h>
13#include <linux/init.h>
a9a753d5
DJ		 14#include <linux/interrupt.h>
15#include <linux/ctype.h>
16#include <linux/io.h>
17#include <linux/mod_devicetable.h>
18#include <linux/edac.h>
60be7551 19#include <linux/smp.h>
5a0e3ad6 20#include <linux/gfp.h>
a9a753d5
DJ		 21
22#include <linux/of_platform.h>
23#include <linux/of_device.h>
a9a753d5
DJ		 24#include "edac_module.h"
25#include "edac_core.h"
26#include "mpc85xx_edac.h"
27
28static int edac_dev_idx;
0616fb00 29#ifdef CONFIG_PCI
a9a753d5 30static int edac_pci_idx;
0616fb00 31#endif
a9a753d5
DJ		 32static int edac_mc_idx;
33
34static u32 orig_ddr_err_disable;
35static u32 orig_ddr_err_sbe;
36
37/*
38 * PCI Err defines
39 */
40#ifdef CONFIG_PCI
41static u32 orig_pci_err_cap_dr;
42static u32 orig_pci_err_en;
43#endif
44
45static u32 orig_l2_err_disable;
b4846251 46#ifdef CONFIG_MPC85xx
60be7551 47static u32 orig_hid1[2];
b4846251 48#endif
a9a753d5 49
a9a753d5
DJ		 50/************************ MC SYSFS parts ***********************************/
51
52static ssize_t mpc85xx_mc_inject_data_hi_show(struct mem_ctl_info *mci,
53 char *data)
54{
55 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
56 return sprintf(data, "0x%08x",
57 in_be32(pdata->mc_vbase +
58 MPC85XX_MC_DATA_ERR_INJECT_HI));
59}
60
61static ssize_t mpc85xx_mc_inject_data_lo_show(struct mem_ctl_info *mci,
62 char *data)
63{
64 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
65 return sprintf(data, "0x%08x",
66 in_be32(pdata->mc_vbase +
67 MPC85XX_MC_DATA_ERR_INJECT_LO));
68}
69
70static ssize_t mpc85xx_mc_inject_ctrl_show(struct mem_ctl_info *mci, char *data)
71{
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
73 return sprintf(data, "0x%08x",
74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
75}
76
77static ssize_t mpc85xx_mc_inject_data_hi_store(struct mem_ctl_info *mci,
78 const char *data, size_t count)
79{
80 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
81 if (isdigit(*data)) {
82 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
83 simple_strtoul(data, NULL, 0));
84 return count;
85 }
86 return 0;
87}
88
89static ssize_t mpc85xx_mc_inject_data_lo_store(struct mem_ctl_info *mci,
90 const char *data, size_t count)
91{
92 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
93 if (isdigit(*data)) {
94 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
95 simple_strtoul(data, NULL, 0));
96 return count;
97 }
98 return 0;
99}
100
101static ssize_t mpc85xx_mc_inject_ctrl_store(struct mem_ctl_info *mci,
102 const char *data, size_t count)
103{
104 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
105 if (isdigit(*data)) {
106 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
107 simple_strtoul(data, NULL, 0));
108 return count;
109 }
110 return 0;
111}
112
113static struct mcidev_sysfs_attribute mpc85xx_mc_sysfs_attributes[] = {
114 {
115 .attr = {
116 .name = "inject_data_hi",
117 .mode = (S_IRUGO | S_IWUSR)
118 },
119 .show = mpc85xx_mc_inject_data_hi_show,
120 .store = mpc85xx_mc_inject_data_hi_store},
121 {
122 .attr = {
123 .name = "inject_data_lo",
124 .mode = (S_IRUGO | S_IWUSR)
125 },
126 .show = mpc85xx_mc_inject_data_lo_show,
127 .store = mpc85xx_mc_inject_data_lo_store},
128 {
129 .attr = {
130 .name = "inject_ctrl",
131 .mode = (S_IRUGO | S_IWUSR)
132 },
133 .show = mpc85xx_mc_inject_ctrl_show,
134 .store = mpc85xx_mc_inject_ctrl_store},
135
136 /* End of list */
137 {
138 .attr = {.name = NULL}
139 }
140};
141
142static void mpc85xx_set_mc_sysfs_attributes(struct mem_ctl_info *mci)
143{
144 mci->mc_driver_sysfs_attributes = mpc85xx_mc_sysfs_attributes;
145}
146
147/**************************** PCI Err device ***************************/
148#ifdef CONFIG_PCI
149
150static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
151{
152 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
153 u32 err_detect;
154
155 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
156
157 /* master aborts can happen during PCI config cycles */
158 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
159 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
160 return;
161 }
162
163 printk(KERN_ERR "PCI error(s) detected\n");
164 printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);
165
166 printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
167 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
168 printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
169 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
170 printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
171 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
172 printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
173 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
174 printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
175 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));
176
177 /* clear error bits */
178 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
179
180 if (err_detect & PCI_EDE_PERR_MASK)
181 edac_pci_handle_pe(pci, pci->ctl_name);
182
183 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
184 edac_pci_handle_npe(pci, pci->ctl_name);
185}
186
187static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id)
188{
189 struct edac_pci_ctl_info *pci = dev_id;
190 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
191 u32 err_detect;
192
193 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);
194
195 if (!err_detect)
196 return IRQ_NONE;
197
198 mpc85xx_pci_check(pci);
199
200 return IRQ_HANDLED;
201}
202
f87bd330
DJ		 203static int __devinit mpc85xx_pci_err_probe(struct of_device *op,
204 const struct of_device_id *match)
a9a753d5
DJ		 205{
206 struct edac_pci_ctl_info *pci;
207 struct mpc85xx_pci_pdata *pdata;
f87bd330 208 struct resource r;
a9a753d5
DJ		 209 int res = 0;
210
f87bd330 211 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL))
a9a753d5
DJ		 212 return -ENOMEM;
213
214 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err");
215 if (!pci)
216 return -ENOMEM;
217
218 pdata = pci->pvt_info;
219 pdata->name = "mpc85xx_pci_err";
220 pdata->irq = NO_IRQ;
f87bd330
DJ		 221 dev_set_drvdata(&op->dev, pci);
222 pci->dev = &op->dev;
a9a753d5
DJ		 223 pci->mod_name = EDAC_MOD_STR;
224 pci->ctl_name = pdata->name;
031d5518 225 pci->dev_name = dev_name(&op->dev);
a9a753d5
DJ		 226
227 if (edac_op_state == EDAC_OPSTATE_POLL)
228 pci->edac_check = mpc85xx_pci_check;
229
230 pdata->edac_idx = edac_pci_idx++;
231
a26f95fe 232 res = of_address_to_resource(op->dev.of_node, 0, &r);
f87bd330 233 if (res) {
a9a753d5
DJ		 234 printk(KERN_ERR "%s: Unable to get resource for "
235 "PCI err regs\n", __func__);
236 goto err;
237 }
238
f87bd330
DJ		 239 /* we only need the error registers */
240 r.start += 0xe00;
241
66ed3f75
HS		 242 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
243 pdata->name)) {
a9a753d5
DJ		 244 printk(KERN_ERR "%s: Error while requesting mem region\n",
245 __func__);
246 res = -EBUSY;
247 goto err;
248 }
249
66ed3f75 250 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
a9a753d5
DJ		 251 if (!pdata->pci_vbase) {
252 printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__);
253 res = -ENOMEM;
254 goto err;
255 }
256
257 orig_pci_err_cap_dr =
258 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR);
259
260 /* PCI master abort is expected during config cycles */
261 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40);
262
263 orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN);
264
265 /* disable master abort reporting */
266 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40);
267
268 /* clear error bits */
269 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0);
270
271 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) {
272 debugf3("%s(): failed edac_pci_add_device()\n", __func__);
273 goto err;
274 }
275
276 if (edac_op_state == EDAC_OPSTATE_INT) {
a26f95fe 277 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
f87bd330 278 res = devm_request_irq(&op->dev, pdata->irq,
a9a753d5
DJ		 279 mpc85xx_pci_isr, IRQF_DISABLED,
280 "[EDAC] PCI err", pci);
281 if (res < 0) {
282 printk(KERN_ERR
283 "%s: Unable to requiest irq %d for "
284 "MPC85xx PCI err\n", __func__, pdata->irq);
f87bd330 285 irq_dispose_mapping(pdata->irq);
a9a753d5
DJ		 286 res = -ENODEV;
287 goto err2;
288 }
289
290 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for PCI Err\n",
291 pdata->irq);
292 }
293
f87bd330 294 devres_remove_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 295 debugf3("%s(): success\n", __func__);
296 printk(KERN_INFO EDAC_MOD_STR " PCI err registered\n");
297
298 return 0;
299
300err2:
f87bd330 301 edac_pci_del_device(&op->dev);
a9a753d5
DJ		 302err:
303 edac_pci_free_ctl_info(pci);
f87bd330 304 devres_release_group(&op->dev, mpc85xx_pci_err_probe);
a9a753d5
DJ		 305 return res;
306}
307
f87bd330 308static int mpc85xx_pci_err_remove(struct of_device *op)
a9a753d5 309{
f87bd330 310 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev);
a9a753d5
DJ		 311 struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
312
313 debugf0("%s()\n", __func__);
314
315 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR,
316 orig_pci_err_cap_dr);
317
318 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en);
319
320 edac_pci_del_device(pci->dev);
321
322 if (edac_op_state == EDAC_OPSTATE_INT)
323 irq_dispose_mapping(pdata->irq);
324
325 edac_pci_free_ctl_info(pci);
326
327 return 0;
328}
329
f87bd330
DJ		 330static struct of_device_id mpc85xx_pci_err_of_match[] = {
331 {
332 .compatible = "fsl,mpc8540-pcix",
333 },
334 {
335 .compatible = "fsl,mpc8540-pci",
336 },
337 {},
338};
952e1c66 339MODULE_DEVICE_TABLE(of, mpc85xx_pci_err_of_match);
f87bd330
DJ		 340
341static struct of_platform_driver mpc85xx_pci_err_driver = {
a9a753d5
DJ		 342 .probe = mpc85xx_pci_err_probe,
343 .remove = __devexit_p(mpc85xx_pci_err_remove),
344 .driver = {
4018294b
GL		 345 .name = "mpc85xx_pci_err",
346 .owner = THIS_MODULE,
347 .of_match_table = mpc85xx_pci_err_of_match,
348 },
a9a753d5
DJ		 349};
350
351#endif /* CONFIG_PCI */
352
353/**************************** L2 Err device ***************************/
354
355/************************ L2 SYSFS parts ***********************************/
356
357static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info
358 *edac_dev, char *data)
359{
360 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
361 return sprintf(data, "0x%08x",
362 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI));
363}
364
365static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info
366 *edac_dev, char *data)
367{
368 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
369 return sprintf(data, "0x%08x",
370 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO));
371}
372
373static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info
374 *edac_dev, char *data)
375{
376 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
377 return sprintf(data, "0x%08x",
378 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL));
379}
380
381static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info
382 *edac_dev, const char *data,
383 size_t count)
384{
385 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
386 if (isdigit(*data)) {
387 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI,
388 simple_strtoul(data, NULL, 0));
389 return count;
390 }
391 return 0;
392}
393
394static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info
395 *edac_dev, const char *data,
396 size_t count)
397{
398 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
399 if (isdigit(*data)) {
400 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO,
401 simple_strtoul(data, NULL, 0));
402 return count;
403 }
404 return 0;
405}
406
407static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info
408 *edac_dev, const char *data,
409 size_t count)
410{
411 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
412 if (isdigit(*data)) {
413 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL,
414 simple_strtoul(data, NULL, 0));
415 return count;
416 }
417 return 0;
418}
419
420static struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = {
421 {
422 .attr = {
423 .name = "inject_data_hi",
424 .mode = (S_IRUGO | S_IWUSR)
425 },
426 .show = mpc85xx_l2_inject_data_hi_show,
427 .store = mpc85xx_l2_inject_data_hi_store},
428 {
429 .attr = {
430 .name = "inject_data_lo",
431 .mode = (S_IRUGO | S_IWUSR)
432 },
433 .show = mpc85xx_l2_inject_data_lo_show,
434 .store = mpc85xx_l2_inject_data_lo_store},
435 {
436 .attr = {
437 .name = "inject_ctrl",
438 .mode = (S_IRUGO | S_IWUSR)
439 },
440 .show = mpc85xx_l2_inject_ctrl_show,
441 .store = mpc85xx_l2_inject_ctrl_store},
442
443 /* End of list */
444 {
445 .attr = {.name = NULL}
446 }
447};
448
449static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info
450 *edac_dev)
451{
452 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes;
453}
454
455/***************************** L2 ops ***********************************/
456
457static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev)
458{
459 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
460 u32 err_detect;
461
462 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
463
464 if (!(err_detect & L2_EDE_MASK))
465 return;
466
467 printk(KERN_ERR "ECC Error in CPU L2 cache\n");
468 printk(KERN_ERR "L2 Error Detect Register: 0x%08x\n", err_detect);
469 printk(KERN_ERR "L2 Error Capture Data High Register: 0x%08x\n",
470 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI));
471 printk(KERN_ERR "L2 Error Capture Data Lo Register: 0x%08x\n",
472 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO));
473 printk(KERN_ERR "L2 Error Syndrome Register: 0x%08x\n",
474 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC));
475 printk(KERN_ERR "L2 Error Attributes Capture Register: 0x%08x\n",
476 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR));
477 printk(KERN_ERR "L2 Error Address Capture Register: 0x%08x\n",
478 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR));
479
480 /* clear error detect register */
481 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect);
482
483 if (err_detect & L2_EDE_CE_MASK)
484 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name);
485
486 if (err_detect & L2_EDE_UE_MASK)
487 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
488}
489
490static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id)
491{
492 struct edac_device_ctl_info *edac_dev = dev_id;
493 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
494 u32 err_detect;
495
496 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET);
497
498 if (!(err_detect & L2_EDE_MASK))
499 return IRQ_NONE;
500
501 mpc85xx_l2_check(edac_dev);
502
503 return IRQ_HANDLED;
504}
505
506static int __devinit mpc85xx_l2_err_probe(struct of_device *op,
507 const struct of_device_id *match)
508{
509 struct edac_device_ctl_info *edac_dev;
510 struct mpc85xx_l2_pdata *pdata;
511 struct resource r;
512 int res;
513
514 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL))
515 return -ENOMEM;
516
517 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata),
518 "cpu", 1, "L", 1, 2, NULL, 0,
519 edac_dev_idx);
520 if (!edac_dev) {
521 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
522 return -ENOMEM;
523 }
524
525 pdata = edac_dev->pvt_info;
526 pdata->name = "mpc85xx_l2_err";
527 pdata->irq = NO_IRQ;
528 edac_dev->dev = &op->dev;
529 dev_set_drvdata(edac_dev->dev, edac_dev);
530 edac_dev->ctl_name = pdata->name;
531 edac_dev->dev_name = pdata->name;
532
a26f95fe 533 res = of_address_to_resource(op->dev.of_node, 0, &r);
a9a753d5
DJ		 534 if (res) {
535 printk(KERN_ERR "%s: Unable to get resource for "
536 "L2 err regs\n", __func__);
537 goto err;
538 }
539
540 /* we only need the error registers */
541 r.start += 0xe00;
542
543 if (!devm_request_mem_region(&op->dev, r.start,
544 r.end - r.start + 1, pdata->name)) {
545 printk(KERN_ERR "%s: Error while requesting mem region\n",
546 __func__);
547 res = -EBUSY;
548 goto err;
549 }
550
551 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
552 if (!pdata->l2_vbase) {
553 printk(KERN_ERR "%s: Unable to setup L2 err regs\n", __func__);
554 res = -ENOMEM;
555 goto err;
556 }
557
558 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0);
559
560 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS);
561
562 /* clear the err_dis */
563 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0);
564
565 edac_dev->mod_name = EDAC_MOD_STR;
566
567 if (edac_op_state == EDAC_OPSTATE_POLL)
568 edac_dev->edac_check = mpc85xx_l2_check;
569
570 mpc85xx_set_l2_sysfs_attributes(edac_dev);
571
572 pdata->edac_idx = edac_dev_idx++;
573
574 if (edac_device_add_device(edac_dev) > 0) {
575 debugf3("%s(): failed edac_device_add_device()\n", __func__);
576 goto err;
577 }
578
579 if (edac_op_state == EDAC_OPSTATE_INT) {
a26f95fe 580 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
a9a753d5
DJ		 581 res = devm_request_irq(&op->dev, pdata->irq,
582 mpc85xx_l2_isr, IRQF_DISABLED,
583 "[EDAC] L2 err", edac_dev);
584 if (res < 0) {
585 printk(KERN_ERR
586 "%s: Unable to requiest irq %d for "
587 "MPC85xx L2 err\n", __func__, pdata->irq);
588 irq_dispose_mapping(pdata->irq);
589 res = -ENODEV;
590 goto err2;
591 }
592
593 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for L2 Err\n",
594 pdata->irq);
595
596 edac_dev->op_state = OP_RUNNING_INTERRUPT;
597
598 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK);
599 }
600
601 devres_remove_group(&op->dev, mpc85xx_l2_err_probe);
602
603 debugf3("%s(): success\n", __func__);
604 printk(KERN_INFO EDAC_MOD_STR " L2 err registered\n");
605
606 return 0;
607
608err2:
609 edac_device_del_device(&op->dev);
610err:
611 devres_release_group(&op->dev, mpc85xx_l2_err_probe);
612 edac_device_free_ctl_info(edac_dev);
613 return res;
614}
615
616static int mpc85xx_l2_err_remove(struct of_device *op)
617{
618 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev);
619 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info;
620
621 debugf0("%s()\n", __func__);
622
623 if (edac_op_state == EDAC_OPSTATE_INT) {
624 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0);
625 irq_dispose_mapping(pdata->irq);
626 }
627
628 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable);
629 edac_device_del_device(&op->dev);
630 edac_device_free_ctl_info(edac_dev);
631 return 0;
632}
633
634static struct of_device_id mpc85xx_l2_err_of_match[] = {
29d6cf26
KG		 635/* deprecate the fsl,85.. forms in the future, 2.6.30? */
636 { .compatible = "fsl,8540-l2-cache-controller", },
637 { .compatible = "fsl,8541-l2-cache-controller", },
638 { .compatible = "fsl,8544-l2-cache-controller", },
639 { .compatible = "fsl,8548-l2-cache-controller", },
640 { .compatible = "fsl,8555-l2-cache-controller", },
641 { .compatible = "fsl,8568-l2-cache-controller", },
642 { .compatible = "fsl,mpc8536-l2-cache-controller", },
643 { .compatible = "fsl,mpc8540-l2-cache-controller", },
644 { .compatible = "fsl,mpc8541-l2-cache-controller", },
645 { .compatible = "fsl,mpc8544-l2-cache-controller", },
646 { .compatible = "fsl,mpc8548-l2-cache-controller", },
647 { .compatible = "fsl,mpc8555-l2-cache-controller", },
648 { .compatible = "fsl,mpc8560-l2-cache-controller", },
649 { .compatible = "fsl,mpc8568-l2-cache-controller", },
650 { .compatible = "fsl,mpc8572-l2-cache-controller", },
a014554e 651 { .compatible = "fsl,p2020-l2-cache-controller", },
a9a753d5
DJ		 652 {},
653};
952e1c66 654MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match);
a9a753d5
DJ		 655
656static struct of_platform_driver mpc85xx_l2_err_driver = {
a9a753d5
DJ		 657 .probe = mpc85xx_l2_err_probe,
658 .remove = mpc85xx_l2_err_remove,
659 .driver = {
4018294b
GL		 660 .name = "mpc85xx_l2_err",
661 .owner = THIS_MODULE,
662 .of_match_table = mpc85xx_l2_err_of_match,
663 },
a9a753d5
DJ		 664};
665
666/**************************** MC Err device ***************************/
667
dcca7c3d
PT		 668/*
669 * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
670 * MPC8572 User's Manual. Each line represents a syndrome bit column as a
671 * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
672 * below correspond to Freescale's manuals.
673 */
674static unsigned int ecc_table[16] = {
675 /* MSB LSB */
676 /* [0:31] [32:63] */
677 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
678 0x00ff00ff, 0x00fff0ff,
679 0x0f0f0f0f, 0x0f0fff00,
680 0x11113333, 0x7777000f,
681 0x22224444, 0x8888222f,
682 0x44448888, 0xffff4441,
683 0x8888ffff, 0x11118882,
684 0xffff1111, 0x22221114, /* Syndrome bit 0 */
685};
686
687/*
688 * Calculate the correct ECC value for a 64-bit value specified by high:low
689 */
690static u8 calculate_ecc(u32 high, u32 low)
691{
692 u32 mask_low;
693 u32 mask_high;
694 int bit_cnt;
695 u8 ecc = 0;
696 int i;
697 int j;
698
699 for (i = 0; i < 8; i++) {
700 mask_high = ecc_table[i * 2];
701 mask_low = ecc_table[i * 2 + 1];
702 bit_cnt = 0;
703
704 for (j = 0; j < 32; j++) {
705 if ((mask_high >> j) & 1)
706 bit_cnt ^= (high >> j) & 1;
707 if ((mask_low >> j) & 1)
708 bit_cnt ^= (low >> j) & 1;
709 }
710
711 ecc |= bit_cnt << i;
712 }
713
714 return ecc;
715}
716
717/*
718 * Create the syndrome code which is generated if the data line specified by
719 * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
720 * User's Manual and 9-61 in the MPC8572 User's Manual.
721 */
722static u8 syndrome_from_bit(unsigned int bit) {
723 int i;
724 u8 syndrome = 0;
725
726 /*
727 * Cycle through the upper or lower 32-bit portion of each value in
728 * ecc_table depending on if 'bit' is in the upper or lower half of
729 * 64-bit data.
730 */
731 for (i = bit < 32; i < 16; i += 2)
732 syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
733
734 return syndrome;
735}
736
737/*
738 * Decode data and ecc syndrome to determine what went wrong
739 * Note: This can only decode single-bit errors
740 */
741static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
742 int *bad_data_bit, int *bad_ecc_bit)
743{
744 int i;
745 u8 syndrome;
746
747 *bad_data_bit = -1;
748 *bad_ecc_bit = -1;
749
750 /*
751 * Calculate the ECC of the captured data and XOR it with the captured
752 * ECC to find an ECC syndrome value we can search for
753 */
754 syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
755
756 /* Check if a data line is stuck... */
757 for (i = 0; i < 64; i++) {
758 if (syndrome == syndrome_from_bit(i)) {
759 *bad_data_bit = i;
760 return;
761 }
762 }
763
764 /* If data is correct, check ECC bits for errors... */
765 for (i = 0; i < 8; i++) {
766 if ((syndrome >> i) & 0x1) {
767 *bad_ecc_bit = i;
768 return;
769 }
770 }
771}
772
a9a753d5
DJ		 773static void mpc85xx_mc_check(struct mem_ctl_info *mci)
774{
775 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
776 struct csrow_info *csrow;
21768639 777 u32 bus_width;
a9a753d5
DJ		 778 u32 err_detect;
779 u32 syndrome;
780 u32 err_addr;
781 u32 pfn;
782 int row_index;
dcca7c3d
PT		 783 u32 cap_high;
784 u32 cap_low;
785 int bad_data_bit;
786 int bad_ecc_bit;
a9a753d5
DJ		 787
788 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
55e5750b 789 if (!err_detect)
a9a753d5
DJ		 790 return;
791
792 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
793 err_detect);
794
795 /* no more processing if not ECC bit errors */
796 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
797 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
798 return;
799 }
800
801 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
21768639
PT		 802
803 /* Mask off appropriate bits of syndrome based on bus width */
804 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
805 DSC_DBW_MASK) ? 32 : 64;
806 if (bus_width == 64)
807 syndrome &= 0xff;
808 else
809 syndrome &= 0xffff;
810
a9a753d5
DJ		 811 err_addr = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS);
812 pfn = err_addr >> PAGE_SHIFT;
813
814 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
815 csrow = &mci->csrows[row_index];
816 if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
817 break;
818 }
819
dcca7c3d
PT		 820 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
821 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
822
823 /*
824 * Analyze single-bit errors on 64-bit wide buses
825 * TODO: Add support for 32-bit wide buses
826 */
827 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
828 sbe_ecc_decode(cap_high, cap_low, syndrome,
829 &bad_data_bit, &bad_ecc_bit);
830
831 if (bad_data_bit != -1)
832 mpc85xx_mc_printk(mci, KERN_ERR,
833 "Faulty Data bit: %d\n", bad_data_bit);
834 if (bad_ecc_bit != -1)
835 mpc85xx_mc_printk(mci, KERN_ERR,
836 "Faulty ECC bit: %d\n", bad_ecc_bit);
837
838 mpc85xx_mc_printk(mci, KERN_ERR,
839 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
840 cap_high ^ (1 << (bad_data_bit - 32)),
841 cap_low ^ (1 << bad_data_bit),
842 syndrome ^ (1 << bad_ecc_bit));
843 }
844
845 mpc85xx_mc_printk(mci, KERN_ERR,
846 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
847 cap_high, cap_low, syndrome);
848 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8x\n", err_addr);
a9a753d5
DJ		 849 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
850
851 /* we are out of range */
852 if (row_index == mci->nr_csrows)
853 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
854
855 if (err_detect & DDR_EDE_SBE)
856 edac_mc_handle_ce(mci, pfn, err_addr & PAGE_MASK,
857 syndrome, row_index, 0, mci->ctl_name);
858
859 if (err_detect & DDR_EDE_MBE)
860 edac_mc_handle_ue(mci, pfn, err_addr & PAGE_MASK,
861 row_index, mci->ctl_name);
862
863 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
864}
865
866static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
867{
868 struct mem_ctl_info *mci = dev_id;
869 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
870 u32 err_detect;
871
872 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
873 if (!err_detect)
874 return IRQ_NONE;
875
876 mpc85xx_mc_check(mci);
877
878 return IRQ_HANDLED;
879}
880
881static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci)
882{
883 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
884 struct csrow_info *csrow;
885 u32 sdram_ctl;
886 u32 sdtype;
887 enum mem_type mtype;
888 u32 cs_bnds;
889 int index;
890
891 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
892
893 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
894 if (sdram_ctl & DSC_RD_EN) {
895 switch (sdtype) {
896 case DSC_SDTYPE_DDR:
897 mtype = MEM_RDDR;
898 break;
899 case DSC_SDTYPE_DDR2:
900 mtype = MEM_RDDR2;
901 break;
b1cfebc9
YS		 902 case DSC_SDTYPE_DDR3:
903 mtype = MEM_RDDR3;
904 break;
a9a753d5
DJ		 905 default:
906 mtype = MEM_UNKNOWN;
907 break;
908 }
909 } else {
910 switch (sdtype) {
911 case DSC_SDTYPE_DDR:
912 mtype = MEM_DDR;
913 break;
914 case DSC_SDTYPE_DDR2:
915 mtype = MEM_DDR2;
916 break;
b1cfebc9
YS		 917 case DSC_SDTYPE_DDR3:
918 mtype = MEM_DDR3;
919 break;
a9a753d5
DJ		 920 default:
921 mtype = MEM_UNKNOWN;
922 break;
923 }
924 }
925
926 for (index = 0; index < mci->nr_csrows; index++) {
927 u32 start;
928 u32 end;
929
930 csrow = &mci->csrows[index];
931 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
932 (index * MPC85XX_MC_CS_BNDS_OFS));
b4846251
IS		 933
934 start = (cs_bnds & 0xffff0000) >> 16;
935 end = (cs_bnds & 0x0000ffff);
a9a753d5
DJ		 936
937 if (start == end)
938 continue; /* not populated */
939
b4846251
IS		 940 start <<= (24 - PAGE_SHIFT);
941 end <<= (24 - PAGE_SHIFT);
942 end |= (1 << (24 - PAGE_SHIFT)) - 1;
943
cff9279e
PT		 944 csrow->first_page = start;
945 csrow->last_page = end;
b4846251 946 csrow->nr_pages = end + 1 - start;
a9a753d5
DJ		 947 csrow->grain = 8;
948 csrow->mtype = mtype;
949 csrow->dtype = DEV_UNKNOWN;
950 if (sdram_ctl & DSC_X32_EN)
951 csrow->dtype = DEV_X32;
952 csrow->edac_mode = EDAC_SECDED;
953 }
954}
955
956static int __devinit mpc85xx_mc_err_probe(struct of_device *op,
957 const struct of_device_id *match)
958{
959 struct mem_ctl_info *mci;
960 struct mpc85xx_mc_pdata *pdata;
961 struct resource r;
962 u32 sdram_ctl;
963 int res;
964
965 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
966 return -ENOMEM;
967
968 mci = edac_mc_alloc(sizeof(*pdata), 4, 1, edac_mc_idx);
969 if (!mci) {
970 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
971 return -ENOMEM;
972 }
973
974 pdata = mci->pvt_info;
975 pdata->name = "mpc85xx_mc_err";
976 pdata->irq = NO_IRQ;
977 mci->dev = &op->dev;
978 pdata->edac_idx = edac_mc_idx++;
979 dev_set_drvdata(mci->dev, mci);
980 mci->ctl_name = pdata->name;
981 mci->dev_name = pdata->name;
982
a26f95fe 983 res = of_address_to_resource(op->dev.of_node, 0, &r);
a9a753d5
DJ		 984 if (res) {
985 printk(KERN_ERR "%s: Unable to get resource for MC err regs\n",
986 __func__);
987 goto err;
988 }
989
990 if (!devm_request_mem_region(&op->dev, r.start,
991 r.end - r.start + 1, pdata->name)) {
992 printk(KERN_ERR "%s: Error while requesting mem region\n",
993 __func__);
994 res = -EBUSY;
995 goto err;
996 }
997
998 pdata->mc_vbase = devm_ioremap(&op->dev, r.start, r.end - r.start + 1);
999 if (!pdata->mc_vbase) {
1000 printk(KERN_ERR "%s: Unable to setup MC err regs\n", __func__);
1001 res = -ENOMEM;
1002 goto err;
1003 }
1004
1005 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
1006 if (!(sdram_ctl & DSC_ECC_EN)) {
1007 /* no ECC */
1008 printk(KERN_WARNING "%s: No ECC DIMMs discovered\n", __func__);
1009 res = -ENODEV;
1010 goto err;
1011 }
1012
1013 debugf3("%s(): init mci\n", __func__);
1014 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_RDDR2 |
1015 MEM_FLAG_DDR | MEM_FLAG_DDR2;
1016 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
1017 mci->edac_cap = EDAC_FLAG_SECDED;
1018 mci->mod_name = EDAC_MOD_STR;
1019 mci->mod_ver = MPC85XX_REVISION;
1020
1021 if (edac_op_state == EDAC_OPSTATE_POLL)
1022 mci->edac_check = mpc85xx_mc_check;
1023
1024 mci->ctl_page_to_phys = NULL;
1025
1026 mci->scrub_mode = SCRUB_SW_SRC;
1027
1028 mpc85xx_set_mc_sysfs_attributes(mci);
1029
1030 mpc85xx_init_csrows(mci);
1031
a9a753d5
DJ		 1032 /* store the original error disable bits */
1033 orig_ddr_err_disable =
1034 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
1035 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
1036
1037 /* clear all error bits */
1038 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
1039
1040 if (edac_mc_add_mc(mci)) {
1041 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1042 goto err;
1043 }
1044
1045 if (edac_op_state == EDAC_OPSTATE_INT) {
1046 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
1047 DDR_EIE_MBEE | DDR_EIE_SBEE);
1048
1049 /* store the original error management threshold */
1050 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
1051 MPC85XX_MC_ERR_SBE) & 0xff0000;
1052
1053 /* set threshold to 1 error per interrupt */
1054 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
1055
1056 /* register interrupts */
a26f95fe 1057 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
a9a753d5 1058 res = devm_request_irq(&op->dev, pdata->irq,
60be7551
AK		 1059 mpc85xx_mc_isr,
1060 IRQF_DISABLED | IRQF_SHARED,
a9a753d5
DJ		 1061 "[EDAC] MC err", mci);
1062 if (res < 0) {
1063 printk(KERN_ERR "%s: Unable to request irq %d for "
1064 "MPC85xx DRAM ERR\n", __func__, pdata->irq);
1065 irq_dispose_mapping(pdata->irq);
1066 res = -ENODEV;
1067 goto err2;
1068 }
1069
1070 printk(KERN_INFO EDAC_MOD_STR " acquired irq %d for MC\n",
1071 pdata->irq);
1072 }
1073
1074 devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
1075 debugf3("%s(): success\n", __func__);
1076 printk(KERN_INFO EDAC_MOD_STR " MC err registered\n");
1077
1078 return 0;
1079
1080err2:
1081 edac_mc_del_mc(&op->dev);
1082err:
1083 devres_release_group(&op->dev, mpc85xx_mc_err_probe);
1084 edac_mc_free(mci);
1085 return res;
1086}
1087
1088static int mpc85xx_mc_err_remove(struct of_device *op)
1089{
1090 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1091 struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
1092
1093 debugf0("%s()\n", __func__);
1094
1095 if (edac_op_state == EDAC_OPSTATE_INT) {
1096 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
1097 irq_dispose_mapping(pdata->irq);
1098 }
1099
1100 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
1101 orig_ddr_err_disable);
1102 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
1103
1104 edac_mc_del_mc(&op->dev);
1105 edac_mc_free(mci);
1106 return 0;
1107}
1108
1109static struct of_device_id mpc85xx_mc_err_of_match[] = {
29d6cf26
KG		 1110/* deprecate the fsl,85.. forms in the future, 2.6.30? */
1111 { .compatible = "fsl,8540-memory-controller", },
1112 { .compatible = "fsl,8541-memory-controller", },
1113 { .compatible = "fsl,8544-memory-controller", },
1114 { .compatible = "fsl,8548-memory-controller", },
1115 { .compatible = "fsl,8555-memory-controller", },
1116 { .compatible = "fsl,8568-memory-controller", },
1117 { .compatible = "fsl,mpc8536-memory-controller", },
1118 { .compatible = "fsl,mpc8540-memory-controller", },
1119 { .compatible = "fsl,mpc8541-memory-controller", },
1120 { .compatible = "fsl,mpc8544-memory-controller", },
1121 { .compatible = "fsl,mpc8548-memory-controller", },
1122 { .compatible = "fsl,mpc8555-memory-controller", },
1123 { .compatible = "fsl,mpc8560-memory-controller", },
1124 { .compatible = "fsl,mpc8568-memory-controller", },
5528e229 1125 { .compatible = "fsl,mpc8569-memory-controller", },
29d6cf26 1126 { .compatible = "fsl,mpc8572-memory-controller", },
b4846251 1127 { .compatible = "fsl,mpc8349-memory-controller", },
a014554e 1128 { .compatible = "fsl,p2020-memory-controller", },
a9a753d5
DJ		 1129 {},
1130};
952e1c66 1131MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
a9a753d5
DJ		 1132
1133static struct of_platform_driver mpc85xx_mc_err_driver = {
a9a753d5
DJ		 1134 .probe = mpc85xx_mc_err_probe,
1135 .remove = mpc85xx_mc_err_remove,
1136 .driver = {
4018294b
GL		 1137 .name = "mpc85xx_mc_err",
1138 .owner = THIS_MODULE,
1139 .of_match_table = mpc85xx_mc_err_of_match,
1140 },
a9a753d5
DJ		 1141};
1142
b4846251 1143#ifdef CONFIG_MPC85xx
60be7551
AK		 1144static void __init mpc85xx_mc_clear_rfxe(void *data)
1145{
1146 orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
1147 mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000));
1148}
b4846251 1149#endif
60be7551 1150
a9a753d5
DJ		 1151static int __init mpc85xx_mc_init(void)
1152{
1153 int res = 0;
1154
1155 printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
1156 "(C) 2006 Montavista Software\n");
1157
1158 /* make sure error reporting method is sane */
1159 switch (edac_op_state) {
1160 case EDAC_OPSTATE_POLL:
1161 case EDAC_OPSTATE_INT:
1162 break;
1163 default:
1164 edac_op_state = EDAC_OPSTATE_INT;
1165 break;
1166 }
1167
1168 res = of_register_platform_driver(&mpc85xx_mc_err_driver);
1169 if (res)
1170 printk(KERN_WARNING EDAC_MOD_STR "MC fails to register\n");
1171
1172 res = of_register_platform_driver(&mpc85xx_l2_err_driver);
1173 if (res)
1174 printk(KERN_WARNING EDAC_MOD_STR "L2 fails to register\n");
1175
1176#ifdef CONFIG_PCI
f87bd330 1177 res = of_register_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1178 if (res)
1179 printk(KERN_WARNING EDAC_MOD_STR "PCI fails to register\n");
1180#endif
1181
b4846251 1182#ifdef CONFIG_MPC85xx
a9a753d5
DJ		 1183 /*
1184 * need to clear HID1[RFXE] to disable machine check int
1185 * so we can catch it
1186 */
60be7551
AK		 1187 if (edac_op_state == EDAC_OPSTATE_INT)
1188 on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
b4846251 1189#endif
a9a753d5
DJ		 1190
1191 return 0;
1192}
1193
1194module_init(mpc85xx_mc_init);
1195
b4846251 1196#ifdef CONFIG_MPC85xx
60be7551
AK		 1197static void __exit mpc85xx_mc_restore_hid1(void *data)
1198{
1199 mtspr(SPRN_HID1, orig_hid1[smp_processor_id()]);
1200}
b4846251 1201#endif
60be7551 1202
a9a753d5
DJ		 1203static void __exit mpc85xx_mc_exit(void)
1204{
b4846251 1205#ifdef CONFIG_MPC85xx
60be7551 1206 on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
b4846251 1207#endif
a9a753d5 1208#ifdef CONFIG_PCI
f87bd330 1209 of_unregister_platform_driver(&mpc85xx_pci_err_driver);
a9a753d5
DJ		 1210#endif
1211 of_unregister_platform_driver(&mpc85xx_l2_err_driver);
1212 of_unregister_platform_driver(&mpc85xx_mc_err_driver);
1213}
1214
1215module_exit(mpc85xx_mc_exit);
1216
1217MODULE_LICENSE("GPL");
1218MODULE_AUTHOR("Montavista Software, Inc.");
1219module_param(edac_op_state, int, 0444);
1220MODULE_PARM_DESC(edac_op_state,
1221 "EDAC Error Reporting state: 0=Poll, 2=Interrupt");
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