[net-next-2.6.git] / drivers / ata / pata_oldpiix.c

/*
 *    pata_oldpiix.c - Intel PATA/SATA controllers
 *
 *	(C) 2005 Red Hat
 *
 *    Some parts based on ata_piix.c by Jeff Garzik and others.
 *
 *    Early PIIX differs significantly from the later PIIX as it lacks
 *    SITRE and the slave timing registers. This means that you have to
 *    set timing per channel, or be clever. Libata tells us whenever it
 *    does drive selection and we use this to reload the timings.
 *
 *    Because of these behaviour differences PIIX gets its own driver module.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include <linux/ata.h>

#define DRV_NAME	"pata_oldpiix"
#define DRV_VERSION	"0.5.5"

/**
 *	oldpiix_pre_reset		-	probe begin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits oldpiix_enable_bits[] = {
		{ 0x41U, 1U, 0x80UL, 0x80UL },	/* port 0 */
		{ 0x43U, 1U, 0x80UL, 0x80UL },	/* port 1 */
	};

	if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	oldpiix_set_piomode - Initialize host controller PATA PIO timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device whose timings we are configuring
 *
 *	Set PIO mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
{
	unsigned int pio	= adev->pio_mode - XFER_PIO_0;
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	u16 idetm_data;
	int control = 0;

	/*
	 *	See Intel Document 298600-004 for the timing programing rules
	 *	for PIIX/ICH. Note that the early PIIX does not have the slave
	 *	timing port at 0x44.
	 */

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	if (pio > 1)
		control |= 1;	/* TIME */
	if (ata_pio_need_iordy(adev))
		control |= 2;	/* IE */

	/* Intel specifies that the prefetch/posting is for disk only */
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE */

	pci_read_config_word(dev, idetm_port, &idetm_data);

	/*
	 * Set PPE, IE and TIME as appropriate.
	 * Clear the other drive's timing bits.
	 */
	if (adev->devno == 0) {
		idetm_data &= 0xCCE0;
		idetm_data |= control;
	} else {
		idetm_data &= 0xCC0E;
		idetm_data |= (control << 4);
	}
	idetm_data |= (timings[pio][0] << 12) |
			(timings[pio][1] << 8);
	pci_write_config_word(dev, idetm_port, idetm_data);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	oldpiix_set_dmamode - Initialize host controller PATA DMA timings
 *	@ap: Port whose timings we are configuring
 *	@adev: Device to program
 *
 *	Set MWDMA mode for device, in host controller PCI config space.
 *
 *	LOCKING:
 *	None (inherited from caller).
 */

static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *dev	= to_pci_dev(ap->host->dev);
	u8 idetm_port		= ap->port_no ? 0x42 : 0x40;
	u16 idetm_data;

	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	/*
	 * MWDMA is driven by the PIO timings. We must also enable
	 * IORDY unconditionally along with TIME1. PPE has already
	 * been set when the PIO timing was set.
	 */

	unsigned int mwdma	= adev->dma_mode - XFER_MW_DMA_0;
	unsigned int control;
	const unsigned int needed_pio[3] = {
		XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	};
	int pio = needed_pio[mwdma] - XFER_PIO_0;

	pci_read_config_word(dev, idetm_port, &idetm_data);

	control = 3;	/* IORDY|TIME0 */
	/* Intel specifies that the PPE functionality is for disk only */
	if (adev->class == ATA_DEV_ATA)
		control |= 4;	/* PPE enable */

	/* If the drive MWDMA is faster than it can do PIO then
	   we must force PIO into PIO0 */

	if (adev->pio_mode < needed_pio[mwdma])
		/* Enable DMA timing only */
		control |= 8;	/* PIO cycles in PIO0 */

	/* Mask out the relevant control and timing bits we will load. Also
	   clear the other drive TIME register as a precaution */
	if (adev->devno == 0) {
		idetm_data &= 0xCCE0;
		idetm_data |= control;
	} else {
		idetm_data &= 0xCC0E;
		idetm_data |= (control << 4);
	}
	idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	pci_write_config_word(dev, idetm_port, idetm_data);

	/* Track which port is configured */
	ap->private_data = adev;
}

/**
 *	oldpiix_qc_issue	-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	if (adev != ap->private_data) {
		oldpiix_set_piomode(ap, adev);
		if (ata_dma_enabled(adev))
			oldpiix_set_dmamode(ap, adev);
	}
	return ata_bmdma_qc_issue(qc);
}


static struct scsi_host_template oldpiix_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations oldpiix_pata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.qc_issue		= oldpiix_qc_issue,
	.cable_detect		= ata_cable_40wire,
	.set_piomode		= oldpiix_set_piomode,
	.set_dmamode		= oldpiix_set_dmamode,
	.prereset		= oldpiix_pre_reset,
};


/**
 *	oldpiix_init_one - Register PIIX ATA PCI device with kernel services
 *	@pdev: PCI device to register
 *	@ent: Entry in oldpiix_pci_tbl matching with @pdev
 *
 *	Called from kernel PCI layer.  We probe for combined mode (sigh),
 *	and then hand over control to libata, for it to do the rest.
 *
 *	LOCKING:
 *	Inherited from PCI layer (may sleep).
 *
 *	RETURNS:
 *	Zero on success, or -ERRNO value.
 */

static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	static const struct ata_port_info info = {
		.flags		= ATA_FLAG_SLAVE_POSS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA12_ONLY,
		.port_ops	= &oldpiix_pata_ops,
	};
	const struct ata_port_info *ppi[] = { &info, NULL };

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev,
			   "version " DRV_VERSION "\n");

	return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
}

static const struct pci_device_id oldpiix_pci_tbl[] = {
	{ PCI_VDEVICE(INTEL, 0x1230), },

	{ }	/* terminate list */
};

static struct pci_driver oldpiix_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= oldpiix_pci_tbl,
	.probe			= oldpiix_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

static int __init oldpiix_init(void)
{
	return pci_register_driver(&oldpiix_pci_driver);
}

static void __exit oldpiix_exit(void)
{
	pci_unregister_driver(&oldpiix_pci_driver);
}

module_init(oldpiix_init);
module_exit(oldpiix_exit);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_oldpiix.c - Intel PATA/SATA controllers
	3	*
ab771630	4	* (C) 2005 Red Hat
669a5db4 JG	5	*
	6	* Some parts based on ata_piix.c by Jeff Garzik and others.
	7	*
	8	* Early PIIX differs significantly from the later PIIX as it lacks
	9	* SITRE and the slave timing registers. This means that you have to
	10	* set timing per channel, or be clever. Libata tells us whenever it
	11	* does drive selection and we use this to reload the timings.
	12	*
	13	* Because of these behaviour differences PIIX gets its own driver module.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/blkdev.h>
	21	#include <linux/delay.h>
	22	#include <linux/device.h>
	23	#include <scsi/scsi_host.h>
	24	#include <linux/libata.h>
	25	#include <linux/ata.h>
	26
	27	#define DRV_NAME "pata_oldpiix"
a0fcdc02	28	#define DRV_VERSION "0.5.5"
669a5db4 JG	29
	30	/**
	31	* oldpiix_pre_reset - probe begin
cc0680a5	32	* @link: ATA link
d4b2bab4	33	* @deadline: deadline jiffies for the operation
669a5db4 JG	34	*
	35	* Set up cable type and use generic probe init
	36	*/
	37
cc0680a5	38	static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	39	{
cc0680a5	40	struct ata_port *ap = link->ap;
669a5db4 JG	41	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	42	static const struct pci_bits oldpiix_enable_bits[] = {
	43	{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
	44	{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
	45	};
	46
c961922b AC	47	if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
c961922b AC	48	return -ENOENT;
d4b2bab4	49
9363c382	50	return ata_sff_prereset(link, deadline);
669a5db4 JG	51	}
669a5db4 JG	52
669a5db4 JG	53	/**
	54	* oldpiix_set_piomode - Initialize host controller PATA PIO timings
	55	* @ap: Port whose timings we are configuring
a0fcdc02	56	* @adev: Device whose timings we are configuring
669a5db4 JG	57	*
	58	* Set PIO mode for device, in host controller PCI config space.
	59	*
	60	* LOCKING:
	61	* None (inherited from caller).
	62	*/
	63
	64	static void oldpiix_set_piomode (struct ata_port ap, struct ata_device adev)
	65	{
	66	unsigned int pio = adev->pio_mode - XFER_PIO_0;
	67	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	68	unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
	69	u16 idetm_data;
	70	int control = 0;
	71
	72	/*
	73	* See Intel Document 298600-004 for the timing programing rules
	74	* for PIIX/ICH. Note that the early PIIX does not have the slave
	75	* timing port at 0x44.
	76	*/
	77
	78	static const /* ISP RTC */
	79	u8 timings[][2] = { { 0, 0 },
	80	{ 0, 0 },
	81	{ 1, 0 },
	82	{ 2, 1 },
	83	{ 2, 3 }, };
	84
409ba47c SS	85	if (pio > 1)
409ba47c SS	86	control \|= 1; /* TIME */
669a5db4	87	if (ata_pio_need_iordy(adev))
409ba47c	88	control \|= 2; /* IE */
669a5db4	89
409ba47c	90	/* Intel specifies that the prefetch/posting is for disk only */
669a5db4	91	if (adev->class == ATA_DEV_ATA)
409ba47c	92	control \|= 4; /* PPE */
669a5db4 JG	93
	94	pci_read_config_word(dev, idetm_port, &idetm_data);
	95
409ba47c SS	96	/*
	97	* Set PPE, IE and TIME as appropriate.
	98	* Clear the other drive's timing bits.
	99	*/
669a5db4 JG	100	if (adev->devno == 0) {
	101	idetm_data &= 0xCCE0;
	102	idetm_data \|= control;
	103	} else {
	104	idetm_data &= 0xCC0E;
	105	idetm_data \|= (control << 4);
	106	}
	107	idetm_data \|= (timings[pio][0] << 12) \|
	108	(timings[pio][1] << 8);
	109	pci_write_config_word(dev, idetm_port, idetm_data);
	110
	111	/* Track which port is configured */
	112	ap->private_data = adev;
	113	}
	114
	115	/**
	116	* oldpiix_set_dmamode - Initialize host controller PATA DMA timings
	117	* @ap: Port whose timings we are configuring
	118	* @adev: Device to program
669a5db4 JG	119	*
	120	* Set MWDMA mode for device, in host controller PCI config space.
	121	*
	122	* LOCKING:
	123	* None (inherited from caller).
	124	*/
	125
	126	static void oldpiix_set_dmamode (struct ata_port ap, struct ata_device adev)
	127	{
	128	struct pci_dev *dev = to_pci_dev(ap->host->dev);
	129	u8 idetm_port = ap->port_no ? 0x42 : 0x40;
	130	u16 idetm_data;
	131
	132	static const /* ISP RTC */
	133	u8 timings[][2] = { { 0, 0 },
	134	{ 0, 0 },
	135	{ 1, 0 },
	136	{ 2, 1 },
	137	{ 2, 3 }, };
	138
	139	/*
	140	* MWDMA is driven by the PIO timings. We must also enable
	141	* IORDY unconditionally along with TIME1. PPE has already
	142	* been set when the PIO timing was set.
	143	*/
	144
	145	unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
	146	unsigned int control;
	147	const unsigned int needed_pio[3] = {
	148	XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
	149	};
	150	int pio = needed_pio[mwdma] - XFER_PIO_0;
	151
	152	pci_read_config_word(dev, idetm_port, &idetm_data);
	153
	154	control = 3; /* IORDY\|TIME0 */
	155	/* Intel specifies that the PPE functionality is for disk only */
	156	if (adev->class == ATA_DEV_ATA)
	157	control \|= 4; /* PPE enable */
	158
	159	/* If the drive MWDMA is faster than it can do PIO then
	160	we must force PIO into PIO0 */
	161
	162	if (adev->pio_mode < needed_pio[mwdma])
	163	/* Enable DMA timing only */
	164	control \|= 8; /* PIO cycles in PIO0 */
	165
	166	/* Mask out the relevant control and timing bits we will load. Also
	167	clear the other drive TIME register as a precaution */
	168	if (adev->devno == 0) {
	169	idetm_data &= 0xCCE0;
	170	idetm_data \|= control;
	171	} else {
	172	idetm_data &= 0xCC0E;
	173	idetm_data \|= (control << 4);
	174	}
	175	idetm_data \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	176	pci_write_config_word(dev, idetm_port, idetm_data);
	177
	178	/* Track which port is configured */
	179	ap->private_data = adev;
	180	}
	181
	182	/**
9363c382	183	* oldpiix_qc_issue - command issue
669a5db4 JG	184	* @qc: command pending
	185	*
	186	* Called when the libata layer is about to issue a command. We wrap
	187	* this interface so that we can load the correct ATA timings if
3a4fa0a2	188	* necessary. Our logic also clears TIME0/TIME1 for the other device so
669a5db4 JG	189	* that, even if we get this wrong, cycles to the other device will
	190	* be made PIO0.
	191	*/
	192
9363c382	193	static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
669a5db4 JG	194	{
	195	struct ata_port *ap = qc->ap;
	196	struct ata_device *adev = qc->dev;
	197
	198	if (adev != ap->private_data) {
b7939b14	199	oldpiix_set_piomode(ap, adev);
b15b3eba	200	if (ata_dma_enabled(adev))
669a5db4	201	oldpiix_set_dmamode(ap, adev);
669a5db4	202	}
360ff783	203	return ata_bmdma_qc_issue(qc);
669a5db4 JG	204	}
	205
	206
	207	static struct scsi_host_template oldpiix_sht = {
68d1d07b	208	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	209	};
669a5db4 JG	210
029cfd6b TH	211	static struct ata_port_operations oldpiix_pata_ops = {
029cfd6b TH	212	.inherits = &ata_bmdma_port_ops,
9363c382	213	.qc_issue = oldpiix_qc_issue,
029cfd6b	214	.cable_detect = ata_cable_40wire,
669a5db4 JG	215	.set_piomode = oldpiix_set_piomode,
669a5db4 JG	216	.set_dmamode = oldpiix_set_dmamode,
a1efdaba	217	.prereset = oldpiix_pre_reset,
669a5db4 JG	218	};
	219
	220
	221	/**
	222	* oldpiix_init_one - Register PIIX ATA PCI device with kernel services
	223	* @pdev: PCI device to register
	224	* @ent: Entry in oldpiix_pci_tbl matching with @pdev
	225	*
	226	* Called from kernel PCI layer. We probe for combined mode (sigh),
	227	* and then hand over control to libata, for it to do the rest.
	228	*
	229	* LOCKING:
	230	* Inherited from PCI layer (may sleep).
	231	*
	232	* RETURNS:
	233	* Zero on success, or -ERRNO value.
	234	*/
	235
	236	static int oldpiix_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	237	{
	238	static int printed_version;
1626aeb8	239	static const struct ata_port_info info = {
1d2808fd	240	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	241	.pio_mask = ATA_PIO4,
82563232	242	.mwdma_mask = ATA_MWDMA12_ONLY,
669a5db4 JG	243	.port_ops = &oldpiix_pata_ops,
669a5db4 JG	244	};
1626aeb8	245	const struct ata_port_info *ppi[] = { &info, NULL };
669a5db4 JG	246
	247	if (!printed_version++)
	248	dev_printk(KERN_DEBUG, &pdev->dev,
	249	"version " DRV_VERSION "\n");
	250
1c5afdf7	251	return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
669a5db4 JG	252	}
	253
	254	static const struct pci_device_id oldpiix_pci_tbl[] = {
2d2744fc JG	255	{ PCI_VDEVICE(INTEL, 0x1230), },
2d2744fc JG	256
669a5db4 JG	257	{ } /* terminate list */
	258	};
	259
	260	static struct pci_driver oldpiix_pci_driver = {
	261	.name = DRV_NAME,
	262	.id_table = oldpiix_pci_tbl,
	263	.probe = oldpiix_init_one,
	264	.remove = ata_pci_remove_one,
438ac6d5	265	#ifdef CONFIG_PM
30ced0f0 AC	266	.suspend = ata_pci_device_suspend,
30ced0f0 AC	267	.resume = ata_pci_device_resume,
438ac6d5	268	#endif
669a5db4 JG	269	};
	270
	271	static int __init oldpiix_init(void)
	272	{
	273	return pci_register_driver(&oldpiix_pci_driver);
	274	}
	275
	276	static void __exit oldpiix_exit(void)
	277	{
	278	pci_unregister_driver(&oldpiix_pci_driver);
	279	}
	280
669a5db4 JG	281	module_init(oldpiix_init);
	282	module_exit(oldpiix_exit);
	283
	284	MODULE_AUTHOR("Alan Cox");
	285	MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
	286	MODULE_LICENSE("GPL");
	287	MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
	288	MODULE_VERSION(DRV_VERSION);
	289