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ahci,ata_generic: let ata_generic handle new MBP w/ MCP89
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
1da177e4 63
441577ef
TH		 64 /* board IDs for specific chipsets in alphabetical order */
65 board_ahci_mcp65,
83f2b963
TH		 66 board_ahci_mcp77,
67 board_ahci_mcp89,
441577ef
TH		 68 board_ahci_mv,
69 board_ahci_sb600,
70 board_ahci_sb700, /* for SB700 and SB800 */
71 board_ahci_vt8251,
72
73 /* aliases */
74 board_ahci_mcp_linux = board_ahci_mcp65,
75 board_ahci_mcp67 = board_ahci_mcp65,
76 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 77 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 78};
79
2dcb407e 80static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 81static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
82 unsigned long deadline);
a1efdaba
TH		 83static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
438ac6d5 87#ifdef CONFIG_PM
c1332875
TH		 88static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 90#endif
ad616ffb 91
029cfd6b
TH		 92static struct ata_port_operations ahci_vt8251_ops = {
93 .inherits = &ahci_ops,
a1efdaba 94 .hardreset = ahci_vt8251_hardreset,
029cfd6b 95};
edc93052 96
029cfd6b
TH		 97static struct ata_port_operations ahci_p5wdh_ops = {
98 .inherits = &ahci_ops,
a1efdaba 99 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 100};
101
bd17243a
SH		 102static struct ata_port_operations ahci_sb600_ops = {
103 .inherits = &ahci_ops,
104 .softreset = ahci_sb600_softreset,
105 .pmp_softreset = ahci_sb600_softreset,
106};
107
417a1a6d
TH		 108#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109
98ac62de 110static const struct ata_port_info ahci_port_info[] = {
441577ef 111 /* by features */
4da646b7 112 [board_ahci] =
1da177e4 113 {
1188c0d8 114 .flags = AHCI_FLAG_COMMON,
14bdef98 115 .pio_mask = ATA_PIO4,
469248ab 116 .udma_mask = ATA_UDMA6,
1da177e4
LT		 117 .port_ops = &ahci_ops,
118 },
441577ef 119 [board_ahci_ign_iferr] =
bf2af2a2 120 {
441577ef 121 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 122 .flags = AHCI_FLAG_COMMON,
14bdef98 123 .pio_mask = ATA_PIO4,
469248ab 124 .udma_mask = ATA_UDMA6,
441577ef 125 .port_ops = &ahci_ops,
bf2af2a2 126 },
441577ef 127 [board_ahci_nosntf] =
41669553 128 {
441577ef 129 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 130 .flags = AHCI_FLAG_COMMON,
14bdef98 131 .pio_mask = ATA_PIO4,
469248ab 132 .udma_mask = ATA_UDMA6,
41669553
TH		 133 .port_ops = &ahci_ops,
134 },
441577ef
TH		 135 /* by chipsets */
136 [board_ahci_mcp65] =
55a61604 137 {
83f2b963
TH		 138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_mcp77] =
146 {
147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
148 .flags = AHCI_FLAG_COMMON,
149 .pio_mask = ATA_PIO4,
150 .udma_mask = ATA_UDMA6,
151 .port_ops = &ahci_ops,
152 },
153 [board_ahci_mcp89] =
154 {
155 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 156 .flags = AHCI_FLAG_COMMON,
14bdef98 157 .pio_mask = ATA_PIO4,
469248ab 158 .udma_mask = ATA_UDMA6,
441577ef 159 .port_ops = &ahci_ops,
55a61604 160 },
4da646b7 161 [board_ahci_mv] =
cd70c266 162 {
417a1a6d 163 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 164 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 165 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 166 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 167 .pio_mask = ATA_PIO4,
cd70c266
JG		 168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_ops,
170 },
441577ef 171 [board_ahci_sb600] =
e39fc8c9 172 {
441577ef
TH		 173 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
174 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
175 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 176 .flags = AHCI_FLAG_COMMON,
14bdef98 177 .pio_mask = ATA_PIO4,
e39fc8c9 178 .udma_mask = ATA_UDMA6,
bd17243a 179 .port_ops = &ahci_sb600_ops,
e39fc8c9 180 },
441577ef 181 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 182 {
441577ef 183 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 184 .flags = AHCI_FLAG_COMMON,
185 .pio_mask = ATA_PIO4,
186 .udma_mask = ATA_UDMA6,
441577ef 187 .port_ops = &ahci_sb600_ops,
aa431dd3 188 },
441577ef 189 [board_ahci_vt8251] =
1b677afd 190 {
441577ef 191 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 192 .flags = AHCI_FLAG_COMMON,
193 .pio_mask = ATA_PIO4,
194 .udma_mask = ATA_UDMA6,
441577ef 195 .port_ops = &ahci_vt8251_ops,
1b677afd 196 },
1da177e4
LT		 197};
198
3b7d697d 199static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 200 /* Intel */
54bb3a94
JG		 201 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
202 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
203 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
204 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
205 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 206 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 207 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
208 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
209 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
210 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 211 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 212 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 213 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
214 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
215 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
216 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
217 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
218 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
219 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
222 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
223 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
224 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
225 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 228 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
229 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 230 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 231 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 232 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 233 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
234 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 235 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 236 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 237 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 238 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 239 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 240 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 241 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
242 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
243 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
244 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
245 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
246 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
fe7fa31a 247
e34bb370
TH		 248 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
249 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
250 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 251
252 /* ATI */
c65ec1c2 253 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 254 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
255 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
256 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
257 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
258 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
259 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 260
e2dd90b1 261 /* AMD */
5deab536 262 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 263 /* AMD is using RAID class only for ahci controllers */
264 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
265 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
266
fe7fa31a 267 /* VIA */
54bb3a94 268 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 269 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 270
271 /* NVIDIA */
e297d99e
TH		 272 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
273 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
274 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
275 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
276 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
277 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
278 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
279 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 280 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
281 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
282 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
283 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
284 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
285 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
286 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
287 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
288 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
289 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
290 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
291 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
292 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
293 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
294 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
295 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
296 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
297 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
298 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
299 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
300 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
301 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
302 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
303 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
304 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
309 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
310 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
311 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
312 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
313 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
314 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
315 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
316 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
317 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
318 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
319 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
320 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
321 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
322 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
323 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
324 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
325 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
326 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
327 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
328 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
329 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
330 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
331 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
332 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
333 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
334 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
335 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
336 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
337 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
338 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
339 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
340 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
341 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
342 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
343 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
344 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
345 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
346 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
347 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
348 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
349 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
350 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
351 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
352 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
353 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
354 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
355 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 356
95916edd 357 /* SiS */
20e2de4a
TH		 358 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
359 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
360 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 361
cd70c266
JG		 362 /* Marvell */
363 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 364 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 365
c77a036b
MN		 366 /* Promise */
367 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
368
415ae2b5
JG		 369 /* Generic, PCI class code for AHCI */
370 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 371 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 372
1da177e4
LT		 373 { } /* terminate list */
374};
375
376
377static struct pci_driver ahci_pci_driver = {
378 .name = DRV_NAME,
379 .id_table = ahci_pci_tbl,
380 .probe = ahci_init_one,
24dc5f33 381 .remove = ata_pci_remove_one,
438ac6d5 382#ifdef CONFIG_PM
c1332875 383 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 384 .resume = ahci_pci_device_resume,
385#endif
386};
1da177e4 387
365cfa1e
AV		 388#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
389static int marvell_enable;
390#else
391static int marvell_enable = 1;
392#endif
393module_param(marvell_enable, int, 0644);
394MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 395
1da177e4 396
365cfa1e
AV		 397static void ahci_pci_save_initial_config(struct pci_dev *pdev,
398 struct ahci_host_priv *hpriv)
399{
400 unsigned int force_port_map = 0;
401 unsigned int mask_port_map = 0;
67846b30 402
365cfa1e
AV		 403 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
404 dev_info(&pdev->dev, "JMB361 has only one port\n");
405 force_port_map = 1;
1da177e4
LT		 406 }
407
365cfa1e
AV		 408 /*
409 * Temporary Marvell 6145 hack: PATA port presence
410 * is asserted through the standard AHCI port
411 * presence register, as bit 4 (counting from 0)
d28f87aa 412 */
365cfa1e
AV		 413 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
414 if (pdev->device == 0x6121)
415 mask_port_map = 0x3;
416 else
417 mask_port_map = 0xf;
418 dev_info(&pdev->dev,
419 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
420 }
1da177e4 421
365cfa1e
AV		 422 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
423 mask_port_map);
1da177e4
LT		 424}
425
365cfa1e 426static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 427{
365cfa1e 428 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 429
365cfa1e 430 ahci_reset_controller(host);
1da177e4 431
365cfa1e
AV		 432 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
433 struct ahci_host_priv *hpriv = host->private_data;
434 u16 tmp16;
d6ef3153 435
365cfa1e
AV		 436 /* configure PCS */
437 pci_read_config_word(pdev, 0x92, &tmp16);
438 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
439 tmp16 |= hpriv->port_map;
440 pci_write_config_word(pdev, 0x92, tmp16);
441 }
d6ef3153
SH		 442 }
443
1da177e4
LT		 444 return 0;
445}
446
365cfa1e 447static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 448{
365cfa1e
AV		 449 struct ahci_host_priv *hpriv = host->private_data;
450 struct pci_dev *pdev = to_pci_dev(host->dev);
451 void __iomem *port_mmio;
78cd52d0 452 u32 tmp;
365cfa1e 453 int mv;
78cd52d0 454
365cfa1e
AV		 455 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
456 if (pdev->device == 0x6121)
457 mv = 2;
458 else
459 mv = 4;
460 port_mmio = __ahci_port_base(host, mv);
78cd52d0 461
365cfa1e 462 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 463
365cfa1e
AV		 464 /* clear port IRQ */
465 tmp = readl(port_mmio + PORT_IRQ_STAT);
466 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
467 if (tmp)
468 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 469 }
470
365cfa1e 471 ahci_init_controller(host);
edc93052
TH		 472}
473
365cfa1e 474static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 475{
365cfa1e
AV		 476 void __iomem *port_mmio = ahci_port_base(link->ap);
477 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
478 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
479
480 /*
481 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
482 * which can save timeout delay.
483 */
484 if (irq_status & PORT_IRQ_BAD_PMP)
485 return -EIO;
78cd52d0 486
365cfa1e 487 return ata_check_ready(status);
78cd52d0
TH		 488}
489
365cfa1e
AV		 490static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
491 unsigned long deadline)
d6ef3153 492{
365cfa1e 493 struct ata_port *ap = link->ap;
d6ef3153 494 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 495 int pmp = sata_srst_pmp(link);
d6ef3153 496 int rc;
365cfa1e 497 u32 irq_sts;
d6ef3153 498
365cfa1e 499 DPRINTK("ENTER\n");
d6ef3153 500
365cfa1e
AV		 501 rc = ahci_do_softreset(link, class, pmp, deadline,
502 ahci_sb600_check_ready);
d6ef3153 503
365cfa1e
AV		 504 /*
505 * Soft reset fails on some ATI chips with IPMS set when PMP
506 * is enabled but SATA HDD/ODD is connected to SATA port,
507 * do soft reset again to port 0.
508 */
509 if (rc == -EIO) {
510 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
511 if (irq_sts & PORT_IRQ_BAD_PMP) {
512 ata_link_printk(link, KERN_WARNING,
513 "applying SB600 PMP SRST workaround "
514 "and retrying\n");
515 rc = ahci_do_softreset(link, class, 0, deadline,
516 ahci_check_ready);
517 }
518 }
d6ef3153 519
365cfa1e 520 return rc;
d6ef3153
SH		 521}
522
365cfa1e
AV		 523static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
524 unsigned long deadline)
d6ef3153 525{
365cfa1e
AV		 526 struct ata_port *ap = link->ap;
527 bool online;
d6ef3153
SH		 528 int rc;
529
365cfa1e 530 DPRINTK("ENTER\n");
d6ef3153 531
365cfa1e 532 ahci_stop_engine(ap);
d6ef3153 533
365cfa1e
AV		 534 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
535 deadline, &online, NULL);
d6ef3153
SH		 536
537 ahci_start_engine(ap);
d6ef3153 538
365cfa1e 539 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 540
365cfa1e
AV		 541 /* vt8251 doesn't clear BSY on signature FIS reception,
542 * request follow-up softreset.
543 */
544 return online ? -EAGAIN : rc;
7d50b60b
TH		 545}
546
365cfa1e
AV		 547static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
548 unsigned long deadline)
7d50b60b 549{
365cfa1e 550 struct ata_port *ap = link->ap;
1c954a4d 551 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 552 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
553 struct ata_taskfile tf;
554 bool online;
555 int rc;
7d50b60b 556
365cfa1e 557 ahci_stop_engine(ap);
028a2596 558
365cfa1e
AV		 559 /* clear D2H reception area to properly wait for D2H FIS */
560 ata_tf_init(link->device, &tf);
561 tf.command = 0x80;
562 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 563
365cfa1e
AV		 564 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
565 deadline, &online, NULL);
028a2596 566
365cfa1e 567 ahci_start_engine(ap);
c1332875 568
365cfa1e
AV		 569 /* The pseudo configuration device on SIMG4726 attached to
570 * ASUS P5W-DH Deluxe doesn't send signature FIS after
571 * hardreset if no device is attached to the first downstream
572 * port && the pseudo device locks up on SRST w/ PMP==0. To
573 * work around this, wait for !BSY only briefly. If BSY isn't
574 * cleared, perform CLO and proceed to IDENTIFY (achieved by
575 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
576 *
577 * Wait for two seconds. Devices attached to downstream port
578 * which can't process the following IDENTIFY after this will
579 * have to be reset again. For most cases, this should
580 * suffice while making probing snappish enough.
581 */
582 if (online) {
583 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
584 ahci_check_ready);
585 if (rc)
586 ahci_kick_engine(ap);
c1332875 587 }
c1332875
TH		 588 return rc;
589}
590
365cfa1e 591#ifdef CONFIG_PM
c1332875
TH		 592static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
593{
cca3974e 594 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 595 struct ahci_host_priv *hpriv = host->private_data;
d8993349 596 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 597 u32 ctl;
598
9b10ae86
TH		 599 if (mesg.event & PM_EVENT_SUSPEND &&
600 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
601 dev_printk(KERN_ERR, &pdev->dev,
602 "BIOS update required for suspend/resume\n");
603 return -EIO;
604 }
605
3a2d5b70 606 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 607 /* AHCI spec rev1.1 section 8.3.3:
608 * Software must disable interrupts prior to requesting a
609 * transition of the HBA to D3 state.
610 */
611 ctl = readl(mmio + HOST_CTL);
612 ctl &= ~HOST_IRQ_EN;
613 writel(ctl, mmio + HOST_CTL);
614 readl(mmio + HOST_CTL); /* flush */
615 }
616
617 return ata_pci_device_suspend(pdev, mesg);
618}
619
620static int ahci_pci_device_resume(struct pci_dev *pdev)
621{
cca3974e 622 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 623 int rc;
624
553c4aa6
TH		 625 rc = ata_pci_device_do_resume(pdev);
626 if (rc)
627 return rc;
c1332875
TH		 628
629 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 630 rc = ahci_pci_reset_controller(host);
c1332875
TH		 631 if (rc)
632 return rc;
633
781d6550 634 ahci_pci_init_controller(host);
c1332875
TH		 635 }
636
cca3974e 637 ata_host_resume(host);
c1332875
TH		 638
639 return 0;
640}
438ac6d5 641#endif
c1332875 642
4447d351 643static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 644{
1da177e4 645 int rc;
1da177e4 646
1da177e4 647 if (using_dac &&
6a35528a
YH		 648 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
649 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 650 if (rc) {
284901a9 651 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 652 if (rc) {
a9524a76
JG		 653 dev_printk(KERN_ERR, &pdev->dev,
654 "64-bit DMA enable failed\n");
1da177e4
LT		 655 return rc;
656 }
657 }
1da177e4 658 } else {
284901a9 659 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 660 if (rc) {
a9524a76
JG		 661 dev_printk(KERN_ERR, &pdev->dev,
662 "32-bit DMA enable failed\n");
1da177e4
LT		 663 return rc;
664 }
284901a9 665 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 666 if (rc) {
a9524a76
JG		 667 dev_printk(KERN_ERR, &pdev->dev,
668 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 669 return rc;
670 }
671 }
1da177e4
LT		 672 return 0;
673}
674
439fcaec
AV		 675static void ahci_pci_print_info(struct ata_host *host)
676{
677 struct pci_dev *pdev = to_pci_dev(host->dev);
678 u16 cc;
679 const char *scc_s;
680
681 pci_read_config_word(pdev, 0x0a, &cc);
682 if (cc == PCI_CLASS_STORAGE_IDE)
683 scc_s = "IDE";
684 else if (cc == PCI_CLASS_STORAGE_SATA)
685 scc_s = "SATA";
686 else if (cc == PCI_CLASS_STORAGE_RAID)
687 scc_s = "RAID";
688 else
689 scc_s = "unknown";
690
691 ahci_print_info(host, scc_s);
692}
693
edc93052
TH		 694/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
695 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
696 * support PMP and the 4726 either directly exports the device
697 * attached to the first downstream port or acts as a hardware storage
698 * controller and emulate a single ATA device (can be RAID 0/1 or some
699 * other configuration).
700 *
701 * When there's no device attached to the first downstream port of the
702 * 4726, "Config Disk" appears, which is a pseudo ATA device to
703 * configure the 4726. However, ATA emulation of the device is very
704 * lame. It doesn't send signature D2H Reg FIS after the initial
705 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
706 *
707 * The following function works around the problem by always using
708 * hardreset on the port and not depending on receiving signature FIS
709 * afterward. If signature FIS isn't received soon, ATA class is
710 * assumed without follow-up softreset.
711 */
712static void ahci_p5wdh_workaround(struct ata_host *host)
713{
714 static struct dmi_system_id sysids[] = {
715 {
716 .ident = "P5W DH Deluxe",
717 .matches = {
718 DMI_MATCH(DMI_SYS_VENDOR,
719 "ASUSTEK COMPUTER INC"),
720 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
721 },
722 },
723 { }
724 };
725 struct pci_dev *pdev = to_pci_dev(host->dev);
726
727 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
728 dmi_check_system(sysids)) {
729 struct ata_port *ap = host->ports[1];
730
731 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
732 "Deluxe on-board SIMG4726 workaround\n");
733
734 ap->ops = &ahci_p5wdh_ops;
735 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
736 }
737}
738
2fcad9d2
TH		 739/* only some SB600 ahci controllers can do 64bit DMA */
740static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 741{
742 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 743 /*
744 * The oldest version known to be broken is 0901 and
745 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 746 * Enable 64bit DMA on 1501 and anything newer.
747 *
03d783bf
TH		 748 * Please read bko#9412 for more info.
749 */
58a09b38
SH		 750 {
751 .ident = "ASUS M2A-VM",
752 .matches = {
753 DMI_MATCH(DMI_BOARD_VENDOR,
754 "ASUSTeK Computer INC."),
755 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
756 },
03d783bf 757 .driver_data = "20071026", /* yyyymmdd */
58a09b38 758 },
e65cc194
MN		 759 /*
760 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
761 * support 64bit DMA.
762 *
763 * BIOS versions earlier than 1.5 had the Manufacturer DMI
764 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
765 * This spelling mistake was fixed in BIOS version 1.5, so
766 * 1.5 and later have the Manufacturer as
767 * "MICRO-STAR INTERNATIONAL CO.,LTD".
768 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
769 *
770 * BIOS versions earlier than 1.9 had a Board Product Name
771 * DMI field of "MS-7376". This was changed to be
772 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
773 * match on DMI_BOARD_NAME of "MS-7376".
774 */
775 {
776 .ident = "MSI K9A2 Platinum",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR,
779 "MICRO-STAR INTER"),
780 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
781 },
782 },
58a09b38
SH		 783 { }
784 };
03d783bf 785 const struct dmi_system_id *match;
2fcad9d2
TH		 786 int year, month, date;
787 char buf[9];
58a09b38 788
03d783bf 789 match = dmi_first_match(sysids);
58a09b38 790 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 791 !match)
58a09b38
SH		 792 return false;
793
e65cc194
MN		 794 if (!match->driver_data)
795 goto enable_64bit;
796
2fcad9d2
TH		 797 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
798 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 799
e65cc194
MN		 800 if (strcmp(buf, match->driver_data) >= 0)
801 goto enable_64bit;
802 else {
03d783bf
TH		 803 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
804 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 805 return false;
806 }
e65cc194
MN		 807
808enable_64bit:
809 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
810 match->ident);
811 return true;
58a09b38
SH		 812}
813
1fd68434
RW		 814static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
815{
816 static const struct dmi_system_id broken_systems[] = {
817 {
818 .ident = "HP Compaq nx6310",
819 .matches = {
820 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
821 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
822 },
823 /* PCI slot number of the controller */
824 .driver_data = (void *)0x1FUL,
825 },
d2f9c061
MR		 826 {
827 .ident = "HP Compaq 6720s",
828 .matches = {
829 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
830 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
831 },
832 /* PCI slot number of the controller */
833 .driver_data = (void *)0x1FUL,
834 },
1fd68434
RW		 835
836 { } /* terminate list */
837 };
838 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
839
840 if (dmi) {
841 unsigned long slot = (unsigned long)dmi->driver_data;
842 /* apply the quirk only to on-board controllers */
843 return slot == PCI_SLOT(pdev->devfn);
844 }
845
846 return false;
847}
848
9b10ae86
TH		 849static bool ahci_broken_suspend(struct pci_dev *pdev)
850{
851 static const struct dmi_system_id sysids[] = {
852 /*
853 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
854 * to the harddisk doesn't become online after
855 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 856 *
857 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
858 *
859 * Use dates instead of versions to match as HP is
860 * apparently recycling both product and version
861 * strings.
862 *
863 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 864 */
865 {
866 .ident = "dv4",
867 .matches = {
868 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
869 DMI_MATCH(DMI_PRODUCT_NAME,
870 "HP Pavilion dv4 Notebook PC"),
871 },
9deb3431 872 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 873 },
874 {
875 .ident = "dv5",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME,
879 "HP Pavilion dv5 Notebook PC"),
880 },
9deb3431 881 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 882 },
883 {
884 .ident = "dv6",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME,
888 "HP Pavilion dv6 Notebook PC"),
889 },
9deb3431 890 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 891 },
892 {
893 .ident = "HDX18",
894 .matches = {
895 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
896 DMI_MATCH(DMI_PRODUCT_NAME,
897 "HP HDX18 Notebook PC"),
898 },
9deb3431 899 .driver_data = "20090430", /* F.23 */
9b10ae86 900 },
cedc9bf9
TH		 901 /*
902 * Acer eMachines G725 has the same problem. BIOS
903 * V1.03 is known to be broken. V3.04 is known to
904 * work. Inbetween, there are V1.06, V2.06 and V3.03
905 * that we don't have much idea about. For now,
906 * blacklist anything older than V3.04.
9deb3431
TH		 907 *
908 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 909 */
910 {
911 .ident = "G725",
912 .matches = {
913 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
914 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
915 },
9deb3431 916 .driver_data = "20091216", /* V3.04 */
cedc9bf9 917 },
9b10ae86
TH		 918 { } /* terminate list */
919 };
920 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 921 int year, month, date;
922 char buf[9];
9b10ae86
TH		 923
924 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
925 return false;
926
9deb3431
TH		 927 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
928 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 929
9deb3431 930 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 931}
932
5594639a
TH		 933static bool ahci_broken_online(struct pci_dev *pdev)
934{
935#define ENCODE_BUSDEVFN(bus, slot, func) \
936 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
937 static const struct dmi_system_id sysids[] = {
938 /*
939 * There are several gigabyte boards which use
940 * SIMG5723s configured as hardware RAID. Certain
941 * 5723 firmware revisions shipped there keep the link
942 * online but fail to answer properly to SRST or
943 * IDENTIFY when no device is attached downstream
944 * causing libata to retry quite a few times leading
945 * to excessive detection delay.
946 *
947 * As these firmwares respond to the second reset try
948 * with invalid device signature, considering unknown
949 * sig as offline works around the problem acceptably.
950 */
951 {
952 .ident = "EP45-DQ6",
953 .matches = {
954 DMI_MATCH(DMI_BOARD_VENDOR,
955 "Gigabyte Technology Co., Ltd."),
956 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
957 },
958 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
959 },
960 {
961 .ident = "EP45-DS5",
962 .matches = {
963 DMI_MATCH(DMI_BOARD_VENDOR,
964 "Gigabyte Technology Co., Ltd."),
965 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
966 },
967 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
968 },
969 { } /* terminate list */
970 };
971#undef ENCODE_BUSDEVFN
972 const struct dmi_system_id *dmi = dmi_first_match(sysids);
973 unsigned int val;
974
975 if (!dmi)
976 return false;
977
978 val = (unsigned long)dmi->driver_data;
979
980 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
981}
982
8e513217 983#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 984static void ahci_gtf_filter_workaround(struct ata_host *host)
985{
986 static const struct dmi_system_id sysids[] = {
987 /*
988 * Aspire 3810T issues a bunch of SATA enable commands
989 * via _GTF including an invalid one and one which is
990 * rejected by the device. Among the successful ones
991 * is FPDMA non-zero offset enable which when enabled
992 * only on the drive side leads to NCQ command
993 * failures. Filter it out.
994 */
995 {
996 .ident = "Aspire 3810T",
997 .matches = {
998 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
999 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1000 },
1001 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1002 },
1003 { }
1004 };
1005 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1006 unsigned int filter;
1007 int i;
1008
1009 if (!dmi)
1010 return;
1011
1012 filter = (unsigned long)dmi->driver_data;
1013 dev_printk(KERN_INFO, host->dev,
1014 "applying extra ACPI _GTF filter 0x%x for %s\n",
1015 filter, dmi->ident);
1016
1017 for (i = 0; i < host->n_ports; i++) {
1018 struct ata_port *ap = host->ports[i];
1019 struct ata_link *link;
1020 struct ata_device *dev;
1021
1022 ata_for_each_link(link, ap, EDGE)
1023 ata_for_each_dev(dev, link, ALL)
1024 dev->gtf_filter |= filter;
1025 }
1026}
8e513217
MT		 1027#else
1028static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1029{}
1030#endif
f80ae7e4 1031
24dc5f33 1032static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1033{
1034 static int printed_version;
e297d99e
TH		 1035 unsigned int board_id = ent->driver_data;
1036 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1037 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1038 struct device *dev = &pdev->dev;
1da177e4 1039 struct ahci_host_priv *hpriv;
4447d351 1040 struct ata_host *host;
837f5f8f 1041 int n_ports, i, rc;
1da177e4
LT		 1042
1043 VPRINTK("ENTER\n");
1044
12fad3f9
TH		 1045 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1046
1da177e4 1047 if (!printed_version++)
a9524a76 1048 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1049
5b66c829
AC		 1050 /* The AHCI driver can only drive the SATA ports, the PATA driver
1051 can drive them all so if both drivers are selected make sure
1052 AHCI stays out of the way */
1053 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1054 return -ENODEV;
1055
c6353b45
TH		 1056 /*
1057 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1058 * ahci, use ata_generic instead.
1059 */
1060 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1061 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1062 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1063 pdev->subsystem_device == 0xcb89)
1064 return -ENODEV;
1065
7a02267e
MN		 1066 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1067 * At the moment, we can only use the AHCI mode. Let the users know
1068 * that for SAS drives they're out of luck.
1069 */
1070 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1071 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1072 "can only drive SATA devices with this driver\n");
1073
4447d351 1074 /* acquire resources */
24dc5f33 1075 rc = pcim_enable_device(pdev);
1da177e4
LT		 1076 if (rc)
1077 return rc;
1078
dea55137
TH		 1079 /* AHCI controllers often implement SFF compatible interface.
1080 * Grab all PCI BARs just in case.
1081 */
1082 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1083 if (rc == -EBUSY)
24dc5f33 1084 pcim_pin_device(pdev);
0d5ff566 1085 if (rc)
24dc5f33 1086 return rc;
1da177e4 1087
c4f7792c
TH		 1088 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1089 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1090 u8 map;
1091
1092 /* ICH6s share the same PCI ID for both piix and ahci
1093 * modes. Enabling ahci mode while MAP indicates
1094 * combined mode is a bad idea. Yield to ata_piix.
1095 */
1096 pci_read_config_byte(pdev, ICH_MAP, &map);
1097 if (map & 0x3) {
1098 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1099 "combined mode, can't enable AHCI mode\n");
1100 return -ENODEV;
1101 }
1102 }
1103
24dc5f33
TH		 1104 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1105 if (!hpriv)
1106 return -ENOMEM;
417a1a6d
TH		 1107 hpriv->flags |= (unsigned long)pi.private_data;
1108
e297d99e
TH		 1109 /* MCP65 revision A1 and A2 can't do MSI */
1110 if (board_id == board_ahci_mcp65 &&
1111 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1112 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1113
e427fe04
SH		 1114 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1115 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1116 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1117
2fcad9d2
TH		 1118 /* only some SB600s can do 64bit DMA */
1119 if (ahci_sb600_enable_64bit(pdev))
1120 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1121
31b239ad
TH		 1122 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1123 pci_intx(pdev, 1);
1da177e4 1124
d8993349
AV		 1125 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1126
4447d351 1127 /* save initial config */
394d6e53 1128 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1129
4447d351 1130 /* prepare host */
453d3131
RH		 1131 if (hpriv->cap & HOST_CAP_NCQ) {
1132 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1133 /*
1134 * Auto-activate optimization is supposed to be
1135 * supported on all AHCI controllers indicating NCQ
1136 * capability, but it seems to be broken on some
1137 * chipsets including NVIDIAs.
1138 */
1139 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1140 pi.flags |= ATA_FLAG_FPDMA_AA;
1141 }
1da177e4 1142
7d50b60b
TH		 1143 if (hpriv->cap & HOST_CAP_PMP)
1144 pi.flags |= ATA_FLAG_PMP;
1145
0cbb0e77 1146 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1147
1fd68434
RW		 1148 if (ahci_broken_system_poweroff(pdev)) {
1149 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1150 dev_info(&pdev->dev,
1151 "quirky BIOS, skipping spindown on poweroff\n");
1152 }
1153
9b10ae86
TH		 1154 if (ahci_broken_suspend(pdev)) {
1155 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1156 dev_printk(KERN_WARNING, &pdev->dev,
1157 "BIOS update required for suspend/resume\n");
1158 }
1159
5594639a
TH		 1160 if (ahci_broken_online(pdev)) {
1161 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1162 dev_info(&pdev->dev,
1163 "online status unreliable, applying workaround\n");
1164 }
1165
837f5f8f
TH		 1166 /* CAP.NP sometimes indicate the index of the last enabled
1167 * port, at other times, that of the last possible port, so
1168 * determining the maximum port number requires looking at
1169 * both CAP.NP and port_map.
1170 */
1171 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1172
1173 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1174 if (!host)
1175 return -ENOMEM;
4447d351
TH		 1176 host->private_data = hpriv;
1177
f3d7f23f 1178 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1179 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1180 else
1181 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1182
18f7ba4c
KCA		 1183 if (pi.flags & ATA_FLAG_EM)
1184 ahci_reset_em(host);
1185
4447d351 1186 for (i = 0; i < host->n_ports; i++) {
dab632e8 1187 struct ata_port *ap = host->ports[i];
4447d351 1188
cbcdd875
TH		 1189 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1190 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1191 0x100 + ap->port_no * 0x80, "port");
1192
31556594
KCA		 1193 /* set initial link pm policy */
1194 ap->pm_policy = NOT_AVAILABLE;
1195
18f7ba4c
KCA		 1196 /* set enclosure management message type */
1197 if (ap->flags & ATA_FLAG_EM)
008dbd61 1198 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1199
1200
dab632e8 1201 /* disabled/not-implemented port */
350756f6 1202 if (!(hpriv->port_map & (1 << i)))
dab632e8 1203 ap->ops = &ata_dummy_port_ops;
4447d351 1204 }
d447df14 1205
edc93052
TH		 1206 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1207 ahci_p5wdh_workaround(host);
1208
f80ae7e4
TH		 1209 /* apply gtf filter quirk */
1210 ahci_gtf_filter_workaround(host);
1211
4447d351
TH		 1212 /* initialize adapter */
1213 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1214 if (rc)
24dc5f33 1215 return rc;
1da177e4 1216
3303040d 1217 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1218 if (rc)
1219 return rc;
1da177e4 1220
781d6550 1221 ahci_pci_init_controller(host);
439fcaec 1222 ahci_pci_print_info(host);
1da177e4 1223
4447d351
TH		 1224 pci_set_master(pdev);
1225 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1226 &ahci_sht);
907f4678 1227}
1da177e4
LT		 1228
1229static int __init ahci_init(void)
1230{
b7887196 1231 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1232}
1233
1da177e4
LT		 1234static void __exit ahci_exit(void)
1235{
1236 pci_unregister_driver(&ahci_pci_driver);
1237}
1238
1239
1240MODULE_AUTHOR("Jeff Garzik");
1241MODULE_DESCRIPTION("AHCI SATA low-level driver");
1242MODULE_LICENSE("GPL");
1243MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1244MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1245
1246module_init(ahci_init);
1247module_exit(ahci_exit);
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