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ahci: add HFLAG_YES_FBS and apply it to 88SE9128
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
5a0e3ad6 45#include <linux/gfp.h>
1da177e4 46#include <scsi/scsi_host.h>
193515d5 47#include <scsi/scsi_cmnd.h>
1da177e4 48#include <linux/libata.h>
365cfa1e 49#include "ahci.h"
1da177e4
LT		 50
51#define DRV_NAME "ahci"
7d50b60b 52#define DRV_VERSION "3.0"
1da177e4 53
1da177e4
LT		 54enum {
55 AHCI_PCI_BAR = 5,
441577ef
TH		 56};
57
58enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
5f173107 63 board_ahci_yes_fbs,
1da177e4 64
441577ef
TH		 65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
83f2b963
TH		 67 board_ahci_mcp77,
68 board_ahci_mcp89,
441577ef
TH		 69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
83f2b963 78 board_ahci_mcp79 = board_ahci_mcp77,
1da177e4
LT		 79};
80
2dcb407e 81static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
bd17243a
SH		 82static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
a1efdaba
TH		 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
438ac6d5 88#ifdef CONFIG_PM
c1332875
TH		 89static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 91#endif
ad616ffb 92
029cfd6b
TH		 93static struct ata_port_operations ahci_vt8251_ops = {
94 .inherits = &ahci_ops,
a1efdaba 95 .hardreset = ahci_vt8251_hardreset,
029cfd6b 96};
edc93052 97
029cfd6b
TH		 98static struct ata_port_operations ahci_p5wdh_ops = {
99 .inherits = &ahci_ops,
a1efdaba 100 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 101};
102
bd17243a
SH		 103static struct ata_port_operations ahci_sb600_ops = {
104 .inherits = &ahci_ops,
105 .softreset = ahci_sb600_softreset,
106 .pmp_softreset = ahci_sb600_softreset,
107};
108
417a1a6d
TH		 109#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
110
98ac62de 111static const struct ata_port_info ahci_port_info[] = {
441577ef 112 /* by features */
4da646b7 113 [board_ahci] =
1da177e4 114 {
1188c0d8 115 .flags = AHCI_FLAG_COMMON,
14bdef98 116 .pio_mask = ATA_PIO4,
469248ab 117 .udma_mask = ATA_UDMA6,
1da177e4
LT		 118 .port_ops = &ahci_ops,
119 },
441577ef 120 [board_ahci_ign_iferr] =
bf2af2a2 121 {
441577ef 122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
417a1a6d 123 .flags = AHCI_FLAG_COMMON,
14bdef98 124 .pio_mask = ATA_PIO4,
469248ab 125 .udma_mask = ATA_UDMA6,
441577ef 126 .port_ops = &ahci_ops,
bf2af2a2 127 },
441577ef 128 [board_ahci_nosntf] =
41669553 129 {
441577ef 130 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
417a1a6d 131 .flags = AHCI_FLAG_COMMON,
14bdef98 132 .pio_mask = ATA_PIO4,
469248ab 133 .udma_mask = ATA_UDMA6,
41669553
TH		 134 .port_ops = &ahci_ops,
135 },
5f173107
TH		 136 [board_ahci_yes_fbs] =
137 {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
441577ef
TH		 144 /* by chipsets */
145 [board_ahci_mcp65] =
55a61604 146 {
83f2b963
TH		 147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_mcp77] =
155 {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_mcp89] =
163 {
164 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
417a1a6d 165 .flags = AHCI_FLAG_COMMON,
14bdef98 166 .pio_mask = ATA_PIO4,
469248ab 167 .udma_mask = ATA_UDMA6,
441577ef 168 .port_ops = &ahci_ops,
55a61604 169 },
4da646b7 170 [board_ahci_mv] =
cd70c266 171 {
417a1a6d 172 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 173 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 174 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 175 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
14bdef98 176 .pio_mask = ATA_PIO4,
cd70c266
JG		 177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
441577ef 180 [board_ahci_sb600] =
e39fc8c9 181 {
441577ef
TH		 182 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
183 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
184 AHCI_HFLAG_32BIT_ONLY),
e39fc8c9 185 .flags = AHCI_FLAG_COMMON,
14bdef98 186 .pio_mask = ATA_PIO4,
e39fc8c9 187 .udma_mask = ATA_UDMA6,
bd17243a 188 .port_ops = &ahci_sb600_ops,
e39fc8c9 189 },
441577ef 190 [board_ahci_sb700] = /* for SB700 and SB800 */
aa431dd3 191 {
441577ef 192 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
aa431dd3
TH		 193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
441577ef 196 .port_ops = &ahci_sb600_ops,
aa431dd3 197 },
441577ef 198 [board_ahci_vt8251] =
1b677afd 199 {
441577ef 200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
1b677afd
SL		 201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
441577ef 204 .port_ops = &ahci_vt8251_ops,
1b677afd 205 },
1da177e4
LT		 206};
207
3b7d697d 208static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 209 /* Intel */
54bb3a94
JG		 210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff 220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
1b677afd 221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
7a234aff
TH		 222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9 239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
b2dde6af 240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
16ad1ad9 241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
c1f57d9b
DM		 242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
adcb5308 244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
c1f57d9b 246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
adcb5308 247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
c1f57d9b 249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
5623cab8
SH		 250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
fe7fa31a 256
e34bb370
TH		 257 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
258 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
259 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 260
261 /* ATI */
c65ec1c2 262 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 263 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
264 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
265 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
266 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a 269
e2dd90b1 270 /* AMD */
5deab536 271 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
e2dd90b1
SH		 272 /* AMD is using RAID class only for ahci controllers */
273 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
274 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
275
fe7fa31a 276 /* VIA */
54bb3a94 277 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 278 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 279
280 /* NVIDIA */
e297d99e
TH		 281 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
282 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
283 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
284 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
441577ef
TH		 289 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
290 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
291 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
292 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
302 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
303 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
304 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
318 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
319 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
320 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
330 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
331 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
342 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
343 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
354 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
355 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
356 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
fe7fa31a 365
95916edd 366 /* SiS */
20e2de4a
TH		 367 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
368 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
369 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 370
cd70c266
JG		 371 /* Marvell */
372 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 373 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
5f173107
TH		 374 { PCI_DEVICE(0x1b4b, 0x9123),
375 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
cd70c266 376
c77a036b
MN		 377 /* Promise */
378 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
379
415ae2b5
JG		 380 /* Generic, PCI class code for AHCI */
381 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 382 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 383
1da177e4
LT		 384 { } /* terminate list */
385};
386
387
388static struct pci_driver ahci_pci_driver = {
389 .name = DRV_NAME,
390 .id_table = ahci_pci_tbl,
391 .probe = ahci_init_one,
24dc5f33 392 .remove = ata_pci_remove_one,
438ac6d5 393#ifdef CONFIG_PM
c1332875 394 .suspend = ahci_pci_device_suspend,
365cfa1e
AV		 395 .resume = ahci_pci_device_resume,
396#endif
397};
1da177e4 398
365cfa1e
AV		 399#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
400static int marvell_enable;
401#else
402static int marvell_enable = 1;
403#endif
404module_param(marvell_enable, int, 0644);
405MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
d28f87aa 406
1da177e4 407
365cfa1e
AV		 408static void ahci_pci_save_initial_config(struct pci_dev *pdev,
409 struct ahci_host_priv *hpriv)
410{
411 unsigned int force_port_map = 0;
412 unsigned int mask_port_map = 0;
67846b30 413
365cfa1e
AV		 414 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
415 dev_info(&pdev->dev, "JMB361 has only one port\n");
416 force_port_map = 1;
1da177e4
LT		 417 }
418
365cfa1e
AV		 419 /*
420 * Temporary Marvell 6145 hack: PATA port presence
421 * is asserted through the standard AHCI port
422 * presence register, as bit 4 (counting from 0)
d28f87aa 423 */
365cfa1e
AV		 424 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
425 if (pdev->device == 0x6121)
426 mask_port_map = 0x3;
427 else
428 mask_port_map = 0xf;
429 dev_info(&pdev->dev,
430 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
431 }
1da177e4 432
365cfa1e
AV		 433 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
434 mask_port_map);
1da177e4
LT		 435}
436
365cfa1e 437static int ahci_pci_reset_controller(struct ata_host *host)
1da177e4 438{
365cfa1e 439 struct pci_dev *pdev = to_pci_dev(host->dev);
7d50b60b 440
365cfa1e 441 ahci_reset_controller(host);
1da177e4 442
365cfa1e
AV		 443 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
444 struct ahci_host_priv *hpriv = host->private_data;
445 u16 tmp16;
d6ef3153 446
365cfa1e
AV		 447 /* configure PCS */
448 pci_read_config_word(pdev, 0x92, &tmp16);
449 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
450 tmp16 |= hpriv->port_map;
451 pci_write_config_word(pdev, 0x92, tmp16);
452 }
d6ef3153
SH		 453 }
454
1da177e4
LT		 455 return 0;
456}
457
365cfa1e 458static void ahci_pci_init_controller(struct ata_host *host)
78cd52d0 459{
365cfa1e
AV		 460 struct ahci_host_priv *hpriv = host->private_data;
461 struct pci_dev *pdev = to_pci_dev(host->dev);
462 void __iomem *port_mmio;
78cd52d0 463 u32 tmp;
365cfa1e 464 int mv;
78cd52d0 465
365cfa1e
AV		 466 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
467 if (pdev->device == 0x6121)
468 mv = 2;
469 else
470 mv = 4;
471 port_mmio = __ahci_port_base(host, mv);
78cd52d0 472
365cfa1e 473 writel(0, port_mmio + PORT_IRQ_MASK);
78cd52d0 474
365cfa1e
AV		 475 /* clear port IRQ */
476 tmp = readl(port_mmio + PORT_IRQ_STAT);
477 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
478 if (tmp)
479 writel(tmp, port_mmio + PORT_IRQ_STAT);
78cd52d0
TH		 480 }
481
365cfa1e 482 ahci_init_controller(host);
edc93052
TH		 483}
484
365cfa1e 485static int ahci_sb600_check_ready(struct ata_link *link)
78cd52d0 486{
365cfa1e
AV		 487 void __iomem *port_mmio = ahci_port_base(link->ap);
488 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
489 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
490
491 /*
492 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
493 * which can save timeout delay.
494 */
495 if (irq_status & PORT_IRQ_BAD_PMP)
496 return -EIO;
78cd52d0 497
365cfa1e 498 return ata_check_ready(status);
78cd52d0
TH		 499}
500
365cfa1e
AV		 501static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
502 unsigned long deadline)
d6ef3153 503{
365cfa1e 504 struct ata_port *ap = link->ap;
d6ef3153 505 void __iomem *port_mmio = ahci_port_base(ap);
365cfa1e 506 int pmp = sata_srst_pmp(link);
d6ef3153 507 int rc;
365cfa1e 508 u32 irq_sts;
d6ef3153 509
365cfa1e 510 DPRINTK("ENTER\n");
d6ef3153 511
365cfa1e
AV		 512 rc = ahci_do_softreset(link, class, pmp, deadline,
513 ahci_sb600_check_ready);
d6ef3153 514
365cfa1e
AV		 515 /*
516 * Soft reset fails on some ATI chips with IPMS set when PMP
517 * is enabled but SATA HDD/ODD is connected to SATA port,
518 * do soft reset again to port 0.
519 */
520 if (rc == -EIO) {
521 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
522 if (irq_sts & PORT_IRQ_BAD_PMP) {
523 ata_link_printk(link, KERN_WARNING,
524 "applying SB600 PMP SRST workaround "
525 "and retrying\n");
526 rc = ahci_do_softreset(link, class, 0, deadline,
527 ahci_check_ready);
528 }
529 }
d6ef3153 530
365cfa1e 531 return rc;
d6ef3153
SH		 532}
533
365cfa1e
AV		 534static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
535 unsigned long deadline)
d6ef3153 536{
365cfa1e
AV		 537 struct ata_port *ap = link->ap;
538 bool online;
d6ef3153
SH		 539 int rc;
540
365cfa1e 541 DPRINTK("ENTER\n");
d6ef3153 542
365cfa1e 543 ahci_stop_engine(ap);
d6ef3153 544
365cfa1e
AV		 545 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
546 deadline, &online, NULL);
d6ef3153
SH		 547
548 ahci_start_engine(ap);
d6ef3153 549
365cfa1e 550 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
d6ef3153 551
365cfa1e
AV		 552 /* vt8251 doesn't clear BSY on signature FIS reception,
553 * request follow-up softreset.
554 */
555 return online ? -EAGAIN : rc;
7d50b60b
TH		 556}
557
365cfa1e
AV		 558static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
559 unsigned long deadline)
7d50b60b 560{
365cfa1e 561 struct ata_port *ap = link->ap;
1c954a4d 562 struct ahci_port_priv *pp = ap->private_data;
365cfa1e
AV		 563 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
564 struct ata_taskfile tf;
565 bool online;
566 int rc;
7d50b60b 567
365cfa1e 568 ahci_stop_engine(ap);
028a2596 569
365cfa1e
AV		 570 /* clear D2H reception area to properly wait for D2H FIS */
571 ata_tf_init(link->device, &tf);
572 tf.command = 0x80;
573 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
7d50b60b 574
365cfa1e
AV		 575 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
576 deadline, &online, NULL);
028a2596 577
365cfa1e 578 ahci_start_engine(ap);
c1332875 579
365cfa1e
AV		 580 /* The pseudo configuration device on SIMG4726 attached to
581 * ASUS P5W-DH Deluxe doesn't send signature FIS after
582 * hardreset if no device is attached to the first downstream
583 * port && the pseudo device locks up on SRST w/ PMP==0. To
584 * work around this, wait for !BSY only briefly. If BSY isn't
585 * cleared, perform CLO and proceed to IDENTIFY (achieved by
586 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
587 *
588 * Wait for two seconds. Devices attached to downstream port
589 * which can't process the following IDENTIFY after this will
590 * have to be reset again. For most cases, this should
591 * suffice while making probing snappish enough.
592 */
593 if (online) {
594 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
595 ahci_check_ready);
596 if (rc)
597 ahci_kick_engine(ap);
c1332875 598 }
c1332875
TH		 599 return rc;
600}
601
365cfa1e 602#ifdef CONFIG_PM
c1332875
TH		 603static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
604{
cca3974e 605 struct ata_host *host = dev_get_drvdata(&pdev->dev);
9b10ae86 606 struct ahci_host_priv *hpriv = host->private_data;
d8993349 607 void __iomem *mmio = hpriv->mmio;
c1332875
TH		 608 u32 ctl;
609
9b10ae86
TH		 610 if (mesg.event & PM_EVENT_SUSPEND &&
611 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
612 dev_printk(KERN_ERR, &pdev->dev,
613 "BIOS update required for suspend/resume\n");
614 return -EIO;
615 }
616
3a2d5b70 617 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 618 /* AHCI spec rev1.1 section 8.3.3:
619 * Software must disable interrupts prior to requesting a
620 * transition of the HBA to D3 state.
621 */
622 ctl = readl(mmio + HOST_CTL);
623 ctl &= ~HOST_IRQ_EN;
624 writel(ctl, mmio + HOST_CTL);
625 readl(mmio + HOST_CTL); /* flush */
626 }
627
628 return ata_pci_device_suspend(pdev, mesg);
629}
630
631static int ahci_pci_device_resume(struct pci_dev *pdev)
632{
cca3974e 633 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 634 int rc;
635
553c4aa6
TH		 636 rc = ata_pci_device_do_resume(pdev);
637 if (rc)
638 return rc;
c1332875
TH		 639
640 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
3303040d 641 rc = ahci_pci_reset_controller(host);
c1332875
TH		 642 if (rc)
643 return rc;
644
781d6550 645 ahci_pci_init_controller(host);
c1332875
TH		 646 }
647
cca3974e 648 ata_host_resume(host);
c1332875
TH		 649
650 return 0;
651}
438ac6d5 652#endif
c1332875 653
4447d351 654static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 655{
1da177e4 656 int rc;
1da177e4 657
1da177e4 658 if (using_dac &&
6a35528a
YH		 659 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
660 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 661 if (rc) {
284901a9 662 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 663 if (rc) {
a9524a76
JG		 664 dev_printk(KERN_ERR, &pdev->dev,
665 "64-bit DMA enable failed\n");
1da177e4
LT		 666 return rc;
667 }
668 }
1da177e4 669 } else {
284901a9 670 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 671 if (rc) {
a9524a76
JG		 672 dev_printk(KERN_ERR, &pdev->dev,
673 "32-bit DMA enable failed\n");
1da177e4
LT		 674 return rc;
675 }
284901a9 676 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 677 if (rc) {
a9524a76
JG		 678 dev_printk(KERN_ERR, &pdev->dev,
679 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 680 return rc;
681 }
682 }
1da177e4
LT		 683 return 0;
684}
685
439fcaec
AV		 686static void ahci_pci_print_info(struct ata_host *host)
687{
688 struct pci_dev *pdev = to_pci_dev(host->dev);
689 u16 cc;
690 const char *scc_s;
691
692 pci_read_config_word(pdev, 0x0a, &cc);
693 if (cc == PCI_CLASS_STORAGE_IDE)
694 scc_s = "IDE";
695 else if (cc == PCI_CLASS_STORAGE_SATA)
696 scc_s = "SATA";
697 else if (cc == PCI_CLASS_STORAGE_RAID)
698 scc_s = "RAID";
699 else
700 scc_s = "unknown";
701
702 ahci_print_info(host, scc_s);
703}
704
edc93052
TH		 705/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
706 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
707 * support PMP and the 4726 either directly exports the device
708 * attached to the first downstream port or acts as a hardware storage
709 * controller and emulate a single ATA device (can be RAID 0/1 or some
710 * other configuration).
711 *
712 * When there's no device attached to the first downstream port of the
713 * 4726, "Config Disk" appears, which is a pseudo ATA device to
714 * configure the 4726. However, ATA emulation of the device is very
715 * lame. It doesn't send signature D2H Reg FIS after the initial
716 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
717 *
718 * The following function works around the problem by always using
719 * hardreset on the port and not depending on receiving signature FIS
720 * afterward. If signature FIS isn't received soon, ATA class is
721 * assumed without follow-up softreset.
722 */
723static void ahci_p5wdh_workaround(struct ata_host *host)
724{
725 static struct dmi_system_id sysids[] = {
726 {
727 .ident = "P5W DH Deluxe",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR,
730 "ASUSTEK COMPUTER INC"),
731 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
732 },
733 },
734 { }
735 };
736 struct pci_dev *pdev = to_pci_dev(host->dev);
737
738 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
739 dmi_check_system(sysids)) {
740 struct ata_port *ap = host->ports[1];
741
742 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
743 "Deluxe on-board SIMG4726 workaround\n");
744
745 ap->ops = &ahci_p5wdh_ops;
746 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
747 }
748}
749
2fcad9d2
TH		 750/* only some SB600 ahci controllers can do 64bit DMA */
751static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
58a09b38
SH		 752{
753 static const struct dmi_system_id sysids[] = {
03d783bf
TH		 754 /*
755 * The oldest version known to be broken is 0901 and
756 * working is 1501 which was released on 2007-10-26.
2fcad9d2
TH		 757 * Enable 64bit DMA on 1501 and anything newer.
758 *
03d783bf
TH		 759 * Please read bko#9412 for more info.
760 */
58a09b38
SH		 761 {
762 .ident = "ASUS M2A-VM",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR,
765 "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
767 },
03d783bf 768 .driver_data = "20071026", /* yyyymmdd */
58a09b38 769 },
e65cc194
MN		 770 /*
771 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
772 * support 64bit DMA.
773 *
774 * BIOS versions earlier than 1.5 had the Manufacturer DMI
775 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
776 * This spelling mistake was fixed in BIOS version 1.5, so
777 * 1.5 and later have the Manufacturer as
778 * "MICRO-STAR INTERNATIONAL CO.,LTD".
779 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
780 *
781 * BIOS versions earlier than 1.9 had a Board Product Name
782 * DMI field of "MS-7376". This was changed to be
783 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
784 * match on DMI_BOARD_NAME of "MS-7376".
785 */
786 {
787 .ident = "MSI K9A2 Platinum",
788 .matches = {
789 DMI_MATCH(DMI_BOARD_VENDOR,
790 "MICRO-STAR INTER"),
791 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
792 },
793 },
58a09b38
SH		 794 { }
795 };
03d783bf 796 const struct dmi_system_id *match;
2fcad9d2
TH		 797 int year, month, date;
798 char buf[9];
58a09b38 799
03d783bf 800 match = dmi_first_match(sysids);
58a09b38 801 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
03d783bf 802 !match)
58a09b38
SH		 803 return false;
804
e65cc194
MN		 805 if (!match->driver_data)
806 goto enable_64bit;
807
2fcad9d2
TH		 808 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
809 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
03d783bf 810
e65cc194
MN		 811 if (strcmp(buf, match->driver_data) >= 0)
812 goto enable_64bit;
813 else {
03d783bf
TH		 814 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
815 "forcing 32bit DMA, update BIOS\n", match->ident);
2fcad9d2
TH		 816 return false;
817 }
e65cc194
MN		 818
819enable_64bit:
820 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
821 match->ident);
822 return true;
58a09b38
SH		 823}
824
1fd68434
RW		 825static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
826{
827 static const struct dmi_system_id broken_systems[] = {
828 {
829 .ident = "HP Compaq nx6310",
830 .matches = {
831 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
832 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
833 },
834 /* PCI slot number of the controller */
835 .driver_data = (void *)0x1FUL,
836 },
d2f9c061
MR		 837 {
838 .ident = "HP Compaq 6720s",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
842 },
843 /* PCI slot number of the controller */
844 .driver_data = (void *)0x1FUL,
845 },
1fd68434
RW		 846
847 { } /* terminate list */
848 };
849 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
850
851 if (dmi) {
852 unsigned long slot = (unsigned long)dmi->driver_data;
853 /* apply the quirk only to on-board controllers */
854 return slot == PCI_SLOT(pdev->devfn);
855 }
856
857 return false;
858}
859
9b10ae86
TH		 860static bool ahci_broken_suspend(struct pci_dev *pdev)
861{
862 static const struct dmi_system_id sysids[] = {
863 /*
864 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
865 * to the harddisk doesn't become online after
866 * resuming from STR. Warn and fail suspend.
9deb3431
TH		 867 *
868 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
869 *
870 * Use dates instead of versions to match as HP is
871 * apparently recycling both product and version
872 * strings.
873 *
874 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
9b10ae86
TH		 875 */
876 {
877 .ident = "dv4",
878 .matches = {
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME,
881 "HP Pavilion dv4 Notebook PC"),
882 },
9deb3431 883 .driver_data = "20090105", /* F.30 */
9b10ae86
TH		 884 },
885 {
886 .ident = "dv5",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME,
890 "HP Pavilion dv5 Notebook PC"),
891 },
9deb3431 892 .driver_data = "20090506", /* F.16 */
9b10ae86
TH		 893 },
894 {
895 .ident = "dv6",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv6 Notebook PC"),
900 },
9deb3431 901 .driver_data = "20090423", /* F.21 */
9b10ae86
TH		 902 },
903 {
904 .ident = "HDX18",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP HDX18 Notebook PC"),
909 },
9deb3431 910 .driver_data = "20090430", /* F.23 */
9b10ae86 911 },
cedc9bf9
TH		 912 /*
913 * Acer eMachines G725 has the same problem. BIOS
914 * V1.03 is known to be broken. V3.04 is known to
915 * work. Inbetween, there are V1.06, V2.06 and V3.03
916 * that we don't have much idea about. For now,
917 * blacklist anything older than V3.04.
9deb3431
TH		 918 *
919 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
cedc9bf9
TH		 920 */
921 {
922 .ident = "G725",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
926 },
9deb3431 927 .driver_data = "20091216", /* V3.04 */
cedc9bf9 928 },
9b10ae86
TH		 929 { } /* terminate list */
930 };
931 const struct dmi_system_id *dmi = dmi_first_match(sysids);
9deb3431
TH		 932 int year, month, date;
933 char buf[9];
9b10ae86
TH		 934
935 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
936 return false;
937
9deb3431
TH		 938 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
939 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
9b10ae86 940
9deb3431 941 return strcmp(buf, dmi->driver_data) < 0;
9b10ae86
TH		 942}
943
5594639a
TH		 944static bool ahci_broken_online(struct pci_dev *pdev)
945{
946#define ENCODE_BUSDEVFN(bus, slot, func) \
947 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
948 static const struct dmi_system_id sysids[] = {
949 /*
950 * There are several gigabyte boards which use
951 * SIMG5723s configured as hardware RAID. Certain
952 * 5723 firmware revisions shipped there keep the link
953 * online but fail to answer properly to SRST or
954 * IDENTIFY when no device is attached downstream
955 * causing libata to retry quite a few times leading
956 * to excessive detection delay.
957 *
958 * As these firmwares respond to the second reset try
959 * with invalid device signature, considering unknown
960 * sig as offline works around the problem acceptably.
961 */
962 {
963 .ident = "EP45-DQ6",
964 .matches = {
965 DMI_MATCH(DMI_BOARD_VENDOR,
966 "Gigabyte Technology Co., Ltd."),
967 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
968 },
969 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
970 },
971 {
972 .ident = "EP45-DS5",
973 .matches = {
974 DMI_MATCH(DMI_BOARD_VENDOR,
975 "Gigabyte Technology Co., Ltd."),
976 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
977 },
978 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
979 },
980 { } /* terminate list */
981 };
982#undef ENCODE_BUSDEVFN
983 const struct dmi_system_id *dmi = dmi_first_match(sysids);
984 unsigned int val;
985
986 if (!dmi)
987 return false;
988
989 val = (unsigned long)dmi->driver_data;
990
991 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
992}
993
8e513217 994#ifdef CONFIG_ATA_ACPI
f80ae7e4
TH		 995static void ahci_gtf_filter_workaround(struct ata_host *host)
996{
997 static const struct dmi_system_id sysids[] = {
998 /*
999 * Aspire 3810T issues a bunch of SATA enable commands
1000 * via _GTF including an invalid one and one which is
1001 * rejected by the device. Among the successful ones
1002 * is FPDMA non-zero offset enable which when enabled
1003 * only on the drive side leads to NCQ command
1004 * failures. Filter it out.
1005 */
1006 {
1007 .ident = "Aspire 3810T",
1008 .matches = {
1009 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1010 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1011 },
1012 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1013 },
1014 { }
1015 };
1016 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1017 unsigned int filter;
1018 int i;
1019
1020 if (!dmi)
1021 return;
1022
1023 filter = (unsigned long)dmi->driver_data;
1024 dev_printk(KERN_INFO, host->dev,
1025 "applying extra ACPI _GTF filter 0x%x for %s\n",
1026 filter, dmi->ident);
1027
1028 for (i = 0; i < host->n_ports; i++) {
1029 struct ata_port *ap = host->ports[i];
1030 struct ata_link *link;
1031 struct ata_device *dev;
1032
1033 ata_for_each_link(link, ap, EDGE)
1034 ata_for_each_dev(dev, link, ALL)
1035 dev->gtf_filter |= filter;
1036 }
1037}
8e513217
MT		 1038#else
1039static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1040{}
1041#endif
f80ae7e4 1042
24dc5f33 1043static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 1044{
1045 static int printed_version;
e297d99e
TH		 1046 unsigned int board_id = ent->driver_data;
1047 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 1048 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 1049 struct device *dev = &pdev->dev;
1da177e4 1050 struct ahci_host_priv *hpriv;
4447d351 1051 struct ata_host *host;
837f5f8f 1052 int n_ports, i, rc;
1da177e4
LT		 1053
1054 VPRINTK("ENTER\n");
1055
b429dd59 1056 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
12fad3f9 1057
1da177e4 1058 if (!printed_version++)
a9524a76 1059 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 1060
5b66c829
AC		 1061 /* The AHCI driver can only drive the SATA ports, the PATA driver
1062 can drive them all so if both drivers are selected make sure
1063 AHCI stays out of the way */
1064 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1065 return -ENODEV;
1066
c6353b45
TH		 1067 /*
1068 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1069 * ahci, use ata_generic instead.
1070 */
1071 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1072 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1073 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1074 pdev->subsystem_device == 0xcb89)
1075 return -ENODEV;
1076
7a02267e
MN		 1077 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1078 * At the moment, we can only use the AHCI mode. Let the users know
1079 * that for SAS drives they're out of luck.
1080 */
1081 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1082 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1083 "can only drive SATA devices with this driver\n");
1084
4447d351 1085 /* acquire resources */
24dc5f33 1086 rc = pcim_enable_device(pdev);
1da177e4
LT		 1087 if (rc)
1088 return rc;
1089
dea55137
TH		 1090 /* AHCI controllers often implement SFF compatible interface.
1091 * Grab all PCI BARs just in case.
1092 */
1093 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 1094 if (rc == -EBUSY)
24dc5f33 1095 pcim_pin_device(pdev);
0d5ff566 1096 if (rc)
24dc5f33 1097 return rc;
1da177e4 1098
c4f7792c
TH		 1099 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1100 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1101 u8 map;
1102
1103 /* ICH6s share the same PCI ID for both piix and ahci
1104 * modes. Enabling ahci mode while MAP indicates
1105 * combined mode is a bad idea. Yield to ata_piix.
1106 */
1107 pci_read_config_byte(pdev, ICH_MAP, &map);
1108 if (map & 0x3) {
1109 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1110 "combined mode, can't enable AHCI mode\n");
1111 return -ENODEV;
1112 }
1113 }
1114
24dc5f33
TH		 1115 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1116 if (!hpriv)
1117 return -ENOMEM;
417a1a6d
TH		 1118 hpriv->flags |= (unsigned long)pi.private_data;
1119
e297d99e
TH		 1120 /* MCP65 revision A1 and A2 can't do MSI */
1121 if (board_id == board_ahci_mcp65 &&
1122 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1123 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1124
e427fe04
SH		 1125 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1126 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1127 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1128
2fcad9d2
TH		 1129 /* only some SB600s can do 64bit DMA */
1130 if (ahci_sb600_enable_64bit(pdev))
1131 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
58a09b38 1132
31b239ad
TH		 1133 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1134 pci_intx(pdev, 1);
1da177e4 1135
d8993349
AV		 1136 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1137
4447d351 1138 /* save initial config */
394d6e53 1139 ahci_pci_save_initial_config(pdev, hpriv);
1da177e4 1140
4447d351 1141 /* prepare host */
453d3131
RH		 1142 if (hpriv->cap & HOST_CAP_NCQ) {
1143 pi.flags |= ATA_FLAG_NCQ;
83f2b963
TH		 1144 /*
1145 * Auto-activate optimization is supposed to be
1146 * supported on all AHCI controllers indicating NCQ
1147 * capability, but it seems to be broken on some
1148 * chipsets including NVIDIAs.
1149 */
1150 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
453d3131
RH		 1151 pi.flags |= ATA_FLAG_FPDMA_AA;
1152 }
1da177e4 1153
7d50b60b
TH		 1154 if (hpriv->cap & HOST_CAP_PMP)
1155 pi.flags |= ATA_FLAG_PMP;
1156
0cbb0e77 1157 ahci_set_em_messages(hpriv, &pi);
18f7ba4c 1158
1fd68434
RW		 1159 if (ahci_broken_system_poweroff(pdev)) {
1160 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1161 dev_info(&pdev->dev,
1162 "quirky BIOS, skipping spindown on poweroff\n");
1163 }
1164
9b10ae86
TH		 1165 if (ahci_broken_suspend(pdev)) {
1166 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1167 dev_printk(KERN_WARNING, &pdev->dev,
1168 "BIOS update required for suspend/resume\n");
1169 }
1170
5594639a
TH		 1171 if (ahci_broken_online(pdev)) {
1172 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1173 dev_info(&pdev->dev,
1174 "online status unreliable, applying workaround\n");
1175 }
1176
837f5f8f
TH		 1177 /* CAP.NP sometimes indicate the index of the last enabled
1178 * port, at other times, that of the last possible port, so
1179 * determining the maximum port number requires looking at
1180 * both CAP.NP and port_map.
1181 */
1182 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1183
1184 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 1185 if (!host)
1186 return -ENOMEM;
4447d351
TH		 1187 host->private_data = hpriv;
1188
f3d7f23f 1189 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
886ad09f 1190 host->flags |= ATA_HOST_PARALLEL_SCAN;
f3d7f23f
AV		 1191 else
1192 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
886ad09f 1193
18f7ba4c
KCA		 1194 if (pi.flags & ATA_FLAG_EM)
1195 ahci_reset_em(host);
1196
4447d351 1197 for (i = 0; i < host->n_ports; i++) {
dab632e8 1198 struct ata_port *ap = host->ports[i];
4447d351 1199
cbcdd875
TH		 1200 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1201 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1202 0x100 + ap->port_no * 0x80, "port");
1203
31556594
KCA		 1204 /* set initial link pm policy */
1205 ap->pm_policy = NOT_AVAILABLE;
1206
18f7ba4c
KCA		 1207 /* set enclosure management message type */
1208 if (ap->flags & ATA_FLAG_EM)
008dbd61 1209 ap->em_message_type = hpriv->em_msg_type;
18f7ba4c
KCA		 1210
1211
dab632e8 1212 /* disabled/not-implemented port */
350756f6 1213 if (!(hpriv->port_map & (1 << i)))
dab632e8 1214 ap->ops = &ata_dummy_port_ops;
4447d351 1215 }
d447df14 1216
edc93052
TH		 1217 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1218 ahci_p5wdh_workaround(host);
1219
f80ae7e4
TH		 1220 /* apply gtf filter quirk */
1221 ahci_gtf_filter_workaround(host);
1222
4447d351
TH		 1223 /* initialize adapter */
1224 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 1225 if (rc)
24dc5f33 1226 return rc;
1da177e4 1227
3303040d 1228 rc = ahci_pci_reset_controller(host);
4447d351
TH		 1229 if (rc)
1230 return rc;
1da177e4 1231
781d6550 1232 ahci_pci_init_controller(host);
439fcaec 1233 ahci_pci_print_info(host);
1da177e4 1234
4447d351
TH		 1235 pci_set_master(pdev);
1236 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1237 &ahci_sht);
907f4678 1238}
1da177e4
LT		 1239
1240static int __init ahci_init(void)
1241{
b7887196 1242 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 1243}
1244
1da177e4
LT		 1245static void __exit ahci_exit(void)
1246{
1247 pci_unregister_driver(&ahci_pci_driver);
1248}
1249
1250
1251MODULE_AUTHOR("Jeff Garzik");
1252MODULE_DESCRIPTION("AHCI SATA low-level driver");
1253MODULE_LICENSE("GPL");
1254MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1255MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1256
1257module_init(ahci_init);
1258module_exit(ahci_exit);
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