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KVM: fix typo in copyright notice
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
aec51dc4 46#include <trace/events/kvm.h>
2ed152af 47
229456fc
MT		 48#define CREATE_TRACE_POINTS
49#include "trace.h"
043405e1 50
24f1e32c 51#include <asm/debugreg.h>
d825ed0a 52#include <asm/msr.h>
a5f61300 53#include <asm/desc.h>
0bed3b56 54#include <asm/mtrr.h>
890ca9ae 55#include <asm/mce.h>
7cf30855 56#include <asm/i387.h>
98918833 57#include <asm/xcr.h>
1d5f066e 58#include <asm/pvclock.h>
217fc9cf 59#include <asm/div64.h>
043405e1 60
313a3dc7 61#define MAX_IO_MSRS 256
a03490ed
CO		 62#define CR0_RESERVED_BITS \
63 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
64 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
65 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
66#define CR4_RESERVED_BITS \
67 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
68 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
69 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
2acf923e 70 | X86_CR4_OSXSAVE \
a03490ed
CO		 71 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
72
73#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 74
75#define KVM_MAX_MCE_BANKS 32
76#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
77
50a37eb4
JR		 78/* EFER defaults:
79 * - enable syscall per default because its emulated by KVM
80 * - enable LME and LMA per default on 64 bit KVM
81 */
82#ifdef CONFIG_X86_64
83static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
84#else
85static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
86#endif
313a3dc7 87
ba1389b7
AK		 88#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
89#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 90
cb142eb7 91static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 92static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
93 struct kvm_cpuid_entry2 __user *entries);
94
97896d04 95struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 96EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 97
ed85c068
AP		 98int ignore_msrs = 0;
99module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
100
18863bdd
AK		 101#define KVM_NR_SHARED_MSRS 16
102
103struct kvm_shared_msrs_global {
104 int nr;
2bf78fa7 105 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 106};
107
108struct kvm_shared_msrs {
109 struct user_return_notifier urn;
110 bool registered;
2bf78fa7
SY		 111 struct kvm_shared_msr_values {
112 u64 host;
113 u64 curr;
114 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 115};
116
117static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
118static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
119
417bc304 120struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 121 { "pf_fixed", VCPU_STAT(pf_fixed) },
122 { "pf_guest", VCPU_STAT(pf_guest) },
123 { "tlb_flush", VCPU_STAT(tlb_flush) },
124 { "invlpg", VCPU_STAT(invlpg) },
125 { "exits", VCPU_STAT(exits) },
126 { "io_exits", VCPU_STAT(io_exits) },
127 { "mmio_exits", VCPU_STAT(mmio_exits) },
128 { "signal_exits", VCPU_STAT(signal_exits) },
129 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 130 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 131 { "halt_exits", VCPU_STAT(halt_exits) },
132 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 133 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 134 { "request_irq", VCPU_STAT(request_irq_exits) },
135 { "irq_exits", VCPU_STAT(irq_exits) },
136 { "host_state_reload", VCPU_STAT(host_state_reload) },
137 { "efer_reload", VCPU_STAT(efer_reload) },
138 { "fpu_reload", VCPU_STAT(fpu_reload) },
139 { "insn_emulation", VCPU_STAT(insn_emulation) },
140 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 141 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 142 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 143 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
144 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
145 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
146 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
147 { "mmu_flooded", VM_STAT(mmu_flooded) },
148 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 149 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 150 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 151 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 152 { "largepages", VM_STAT(lpages) },
417bc304
HB		 153 { NULL }
154};
155
2acf923e
DC		 156u64 __read_mostly host_xcr0;
157
158static inline u32 bit(int bitno)
159{
160 return 1 << (bitno & 31);
161}
162
18863bdd
AK		 163static void kvm_on_user_return(struct user_return_notifier *urn)
164{
165 unsigned slot;
18863bdd
AK		 166 struct kvm_shared_msrs *locals
167 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 168 struct kvm_shared_msr_values *values;
18863bdd
AK		 169
170 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 171 values = &locals->values[slot];
172 if (values->host != values->curr) {
173 wrmsrl(shared_msrs_global.msrs[slot], values->host);
174 values->curr = values->host;
18863bdd
AK		 175 }
176 }
177 locals->registered = false;
178 user_return_notifier_unregister(urn);
179}
180
2bf78fa7 181static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 182{
2bf78fa7 183 struct kvm_shared_msrs *smsr;
18863bdd
AK		 184 u64 value;
185
2bf78fa7
SY		 186 smsr = &__get_cpu_var(shared_msrs);
187 /* only read, and nobody should modify it at this time,
188 * so don't need lock */
189 if (slot >= shared_msrs_global.nr) {
190 printk(KERN_ERR "kvm: invalid MSR slot!");
191 return;
192 }
193 rdmsrl_safe(msr, &value);
194 smsr->values[slot].host = value;
195 smsr->values[slot].curr = value;
196}
197
198void kvm_define_shared_msr(unsigned slot, u32 msr)
199{
18863bdd
AK		 200 if (slot >= shared_msrs_global.nr)
201 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 202 shared_msrs_global.msrs[slot] = msr;
203 /* we need ensured the shared_msr_global have been updated */
204 smp_wmb();
18863bdd
AK		 205}
206EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
207
208static void kvm_shared_msr_cpu_online(void)
209{
210 unsigned i;
18863bdd
AK		 211
212 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 213 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 214}
215
d5696725 216void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 217{
218 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
219
2bf78fa7 220 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 221 return;
2bf78fa7
SY		 222 smsr->values[slot].curr = value;
223 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 224 if (!smsr->registered) {
225 smsr->urn.on_user_return = kvm_on_user_return;
226 user_return_notifier_register(&smsr->urn);
227 smsr->registered = true;
228 }
229}
230EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
231
3548bab5
AK		 232static void drop_user_return_notifiers(void *ignore)
233{
234 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
235
236 if (smsr->registered)
237 kvm_on_user_return(&smsr->urn);
238}
239
6866b83e
CO		 240u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
241{
242 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 243 return vcpu->arch.apic_base;
6866b83e 244 else
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e
CO		 246}
247EXPORT_SYMBOL_GPL(kvm_get_apic_base);
248
249void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
250{
251 /* TODO: reserve bits check */
252 if (irqchip_in_kernel(vcpu->kvm))
253 kvm_lapic_set_base(vcpu, data);
254 else
ad312c7c 255 vcpu->arch.apic_base = data;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_set_apic_base);
258
3fd28fce
ED		 259#define EXCPT_BENIGN 0
260#define EXCPT_CONTRIBUTORY 1
261#define EXCPT_PF 2
262
263static int exception_class(int vector)
264{
265 switch (vector) {
266 case PF_VECTOR:
267 return EXCPT_PF;
268 case DE_VECTOR:
269 case TS_VECTOR:
270 case NP_VECTOR:
271 case SS_VECTOR:
272 case GP_VECTOR:
273 return EXCPT_CONTRIBUTORY;
274 default:
275 break;
276 }
277 return EXCPT_BENIGN;
278}
279
280static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 281 unsigned nr, bool has_error, u32 error_code,
282 bool reinject)
3fd28fce
ED		 283{
284 u32 prev_nr;
285 int class1, class2;
286
3842d135
AK		 287 kvm_make_request(KVM_REQ_EVENT, vcpu);
288
3fd28fce
ED		 289 if (!vcpu->arch.exception.pending) {
290 queue:
291 vcpu->arch.exception.pending = true;
292 vcpu->arch.exception.has_error_code = has_error;
293 vcpu->arch.exception.nr = nr;
294 vcpu->arch.exception.error_code = error_code;
3f0fd292 295 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 296 return;
297 }
298
299 /* to check exception */
300 prev_nr = vcpu->arch.exception.nr;
301 if (prev_nr == DF_VECTOR) {
302 /* triple fault -> shutdown */
a8eeb04a 303 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 304 return;
305 }
306 class1 = exception_class(prev_nr);
307 class2 = exception_class(nr);
308 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
309 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
310 /* generate double fault per SDM Table 5-5 */
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = true;
313 vcpu->arch.exception.nr = DF_VECTOR;
314 vcpu->arch.exception.error_code = 0;
315 } else
316 /* replace previous exception with a new one in a hope
317 that instruction re-execution will regenerate lost
318 exception */
319 goto queue;
320}
321
298101da
AK		 322void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
323{
ce7ddec4 324 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 325}
326EXPORT_SYMBOL_GPL(kvm_queue_exception);
327
ce7ddec4
JR		 328void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
330 kvm_multiple_exception(vcpu, nr, false, 0, true);
331}
332EXPORT_SYMBOL_GPL(kvm_requeue_exception);
333
8df25a32 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu)
c3c91fee 335{
8df25a32
JR		 336 unsigned error_code = vcpu->arch.fault.error_code;
337
c3c91fee 338 ++vcpu->stat.pf_guest;
8df25a32 339 vcpu->arch.cr2 = vcpu->arch.fault.address;
c3c91fee
AK		 340 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
341}
342
d4f8cf66
JR		 343void kvm_propagate_fault(struct kvm_vcpu *vcpu)
344{
0959ffac 345 if (mmu_is_nested(vcpu) && !vcpu->arch.fault.nested)
d4f8cf66
JR		 346 vcpu->arch.nested_mmu.inject_page_fault(vcpu);
347 else
348 vcpu->arch.mmu.inject_page_fault(vcpu);
0959ffac
JR		 349
350 vcpu->arch.fault.nested = false;
d4f8cf66
JR		 351}
352
3419ffc8
SY		 353void kvm_inject_nmi(struct kvm_vcpu *vcpu)
354{
3842d135 355 kvm_make_request(KVM_REQ_EVENT, vcpu);
3419ffc8
SY		 356 vcpu->arch.nmi_pending = 1;
357}
358EXPORT_SYMBOL_GPL(kvm_inject_nmi);
359
298101da
AK		 360void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
361{
ce7ddec4 362 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 363}
364EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
365
ce7ddec4
JR		 366void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
368 kvm_multiple_exception(vcpu, nr, true, error_code, true);
369}
370EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
371
0a79b009
AK		 372/*
373 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
374 * a #GP and return false.
375 */
376bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 377{
0a79b009
AK		 378 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
379 return true;
380 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
381 return false;
298101da 382}
0a79b009 383EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 384
ec92fe44
JR		 385/*
386 * This function will be used to read from the physical memory of the currently
387 * running guest. The difference to kvm_read_guest_page is that this function
388 * can read from guest physical or from the guest's guest physical memory.
389 */
390int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
391 gfn_t ngfn, void *data, int offset, int len,
392 u32 access)
393{
394 gfn_t real_gfn;
395 gpa_t ngpa;
396
397 ngpa = gfn_to_gpa(ngfn);
398 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
399 if (real_gfn == UNMAPPED_GVA)
400 return -EFAULT;
401
402 real_gfn = gpa_to_gfn(real_gfn);
403
404 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
405}
406EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
407
3d06b8bf
JR		 408int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
409 void *data, int offset, int len, u32 access)
410{
411 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
412 data, offset, len, access);
413}
414
a03490ed
CO		 415/*
416 * Load the pae pdptrs. Return true is they are all valid.
417 */
ff03a073 418int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 419{
420 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
421 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
422 int i;
423 int ret;
ff03a073 424 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 425
ff03a073
JR		 426 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
427 offset * sizeof(u64), sizeof(pdpte),
428 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 429 if (ret < 0) {
430 ret = 0;
431 goto out;
432 }
433 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 434 if (is_present_gpte(pdpte[i]) &&
20c466b5 435 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 436 ret = 0;
437 goto out;
438 }
439 }
440 ret = 1;
441
ff03a073 442 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 443 __set_bit(VCPU_EXREG_PDPTR,
444 (unsigned long *)&vcpu->arch.regs_avail);
445 __set_bit(VCPU_EXREG_PDPTR,
446 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 447out:
a03490ed
CO		 448
449 return ret;
450}
cc4b6871 451EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 452
d835dfec
AK		 453static bool pdptrs_changed(struct kvm_vcpu *vcpu)
454{
ff03a073 455 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 456 bool changed = true;
3d06b8bf
JR		 457 int offset;
458 gfn_t gfn;
d835dfec
AK		 459 int r;
460
461 if (is_long_mode(vcpu) || !is_pae(vcpu))
462 return false;
463
6de4f3ad
AK		 464 if (!test_bit(VCPU_EXREG_PDPTR,
465 (unsigned long *)&vcpu->arch.regs_avail))
466 return true;
467
3d06b8bf
JR		 468 gfn = (vcpu->arch.cr3 & ~31u) >> PAGE_SHIFT;
469 offset = (vcpu->arch.cr3 & ~31u) & (PAGE_SIZE - 1);
470 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
471 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 472 if (r < 0)
473 goto out;
ff03a073 474 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 475out:
d835dfec
AK		 476
477 return changed;
478}
479
49a9b07e 480int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 481{
aad82703
SY		 482 unsigned long old_cr0 = kvm_read_cr0(vcpu);
483 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
484 X86_CR0_CD | X86_CR0_NW;
485
f9a48e6a
AK		 486 cr0 |= X86_CR0_ET;
487
ab344828 488#ifdef CONFIG_X86_64
0f12244f
GN		 489 if (cr0 & 0xffffffff00000000UL)
490 return 1;
ab344828
GN		 491#endif
492
493 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 494
0f12244f
GN		 495 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
496 return 1;
a03490ed 497
0f12244f
GN		 498 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
499 return 1;
a03490ed
CO		 500
501 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
502#ifdef CONFIG_X86_64
f6801dff 503 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 504 int cs_db, cs_l;
505
0f12244f
GN		 506 if (!is_pae(vcpu))
507 return 1;
a03490ed 508 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 509 if (cs_l)
510 return 1;
a03490ed
CO		 511 } else
512#endif
ff03a073
JR		 513 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
514 vcpu->arch.cr3))
0f12244f 515 return 1;
a03490ed
CO		 516 }
517
518 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 519
aad82703
SY		 520 if ((cr0 ^ old_cr0) & update_bits)
521 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 522 return 0;
523}
2d3ad1f4 524EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 525
2d3ad1f4 526void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 527{
49a9b07e 528 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 531
2acf923e
DC		 532int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
533{
534 u64 xcr0;
535
536 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
537 if (index != XCR_XFEATURE_ENABLED_MASK)
538 return 1;
539 xcr0 = xcr;
540 if (kvm_x86_ops->get_cpl(vcpu) != 0)
541 return 1;
542 if (!(xcr0 & XSTATE_FP))
543 return 1;
544 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
545 return 1;
546 if (xcr0 & ~host_xcr0)
547 return 1;
548 vcpu->arch.xcr0 = xcr0;
549 vcpu->guest_xcr0_loaded = 0;
550 return 0;
551}
552
553int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 if (__kvm_set_xcr(vcpu, index, xcr)) {
556 kvm_inject_gp(vcpu, 0);
557 return 1;
558 }
559 return 0;
560}
561EXPORT_SYMBOL_GPL(kvm_set_xcr);
562
563static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
564{
565 struct kvm_cpuid_entry2 *best;
566
567 best = kvm_find_cpuid_entry(vcpu, 1, 0);
568 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
569}
570
571static void update_cpuid(struct kvm_vcpu *vcpu)
572{
573 struct kvm_cpuid_entry2 *best;
574
575 best = kvm_find_cpuid_entry(vcpu, 1, 0);
576 if (!best)
577 return;
578
579 /* Update OSXSAVE bit */
580 if (cpu_has_xsave && best->function == 0x1) {
581 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
582 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
583 best->ecx |= bit(X86_FEATURE_OSXSAVE);
584 }
585}
586
a83b29c6 587int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 588{
fc78f519 589 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 590 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
591
0f12244f
GN		 592 if (cr4 & CR4_RESERVED_BITS)
593 return 1;
a03490ed 594
2acf923e
DC		 595 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
596 return 1;
597
a03490ed 598 if (is_long_mode(vcpu)) {
0f12244f
GN		 599 if (!(cr4 & X86_CR4_PAE))
600 return 1;
a2edf57f
AK		 601 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
602 && ((cr4 ^ old_cr4) & pdptr_bits)
ff03a073 603 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3))
0f12244f
GN		 604 return 1;
605
606 if (cr4 & X86_CR4_VMXE)
607 return 1;
a03490ed 608
a03490ed 609 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 610
aad82703
SY		 611 if ((cr4 ^ old_cr4) & pdptr_bits)
612 kvm_mmu_reset_context(vcpu);
0f12244f 613
2acf923e
DC		 614 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
615 update_cpuid(vcpu);
616
0f12244f
GN		 617 return 0;
618}
2d3ad1f4 619EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 620
2390218b 621int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 622{
ad312c7c 623 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 624 kvm_mmu_sync_roots(vcpu);
d835dfec 625 kvm_mmu_flush_tlb(vcpu);
0f12244f 626 return 0;
d835dfec
AK		 627 }
628
a03490ed 629 if (is_long_mode(vcpu)) {
0f12244f
GN		 630 if (cr3 & CR3_L_MODE_RESERVED_BITS)
631 return 1;
a03490ed
CO		 632 } else {
633 if (is_pae(vcpu)) {
0f12244f
GN		 634 if (cr3 & CR3_PAE_RESERVED_BITS)
635 return 1;
ff03a073
JR		 636 if (is_paging(vcpu) &&
637 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 638 return 1;
a03490ed
CO		 639 }
640 /*
641 * We don't check reserved bits in nonpae mode, because
642 * this isn't enforced, and VMware depends on this.
643 */
644 }
645
a03490ed
CO		 646 /*
647 * Does the new cr3 value map to physical memory? (Note, we
648 * catch an invalid cr3 even in real-mode, because it would
649 * cause trouble later on when we turn on paging anyway.)
650 *
651 * A real CPU would silently accept an invalid cr3 and would
652 * attempt to use it - with largely undefined (and often hard
653 * to debug) behavior on the guest side.
654 */
655 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 656 return 1;
657 vcpu->arch.cr3 = cr3;
658 vcpu->arch.mmu.new_cr3(vcpu);
659 return 0;
660}
2d3ad1f4 661EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 662
0f12244f 663int __kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 664{
0f12244f
GN		 665 if (cr8 & CR8_RESERVED_BITS)
666 return 1;
a03490ed
CO		 667 if (irqchip_in_kernel(vcpu->kvm))
668 kvm_lapic_set_tpr(vcpu, cr8);
669 else
ad312c7c 670 vcpu->arch.cr8 = cr8;
0f12244f
GN		 671 return 0;
672}
673
674void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
675{
676 if (__kvm_set_cr8(vcpu, cr8))
677 kvm_inject_gp(vcpu, 0);
a03490ed 678}
2d3ad1f4 679EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 680
2d3ad1f4 681unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 682{
683 if (irqchip_in_kernel(vcpu->kvm))
684 return kvm_lapic_get_cr8(vcpu);
685 else
ad312c7c 686 return vcpu->arch.cr8;
a03490ed 687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 689
338dbc97 690static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 691{
692 switch (dr) {
693 case 0 ... 3:
694 vcpu->arch.db[dr] = val;
695 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
696 vcpu->arch.eff_db[dr] = val;
697 break;
698 case 4:
338dbc97
GN		 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
700 return 1; /* #UD */
020df079
GN		 701 /* fall through */
702 case 6:
338dbc97
GN		 703 if (val & 0xffffffff00000000ULL)
704 return -1; /* #GP */
020df079
GN		 705 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
706 break;
707 case 5:
338dbc97
GN		 708 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
709 return 1; /* #UD */
020df079
GN		 710 /* fall through */
711 default: /* 7 */
338dbc97
GN		 712 if (val & 0xffffffff00000000ULL)
713 return -1; /* #GP */
020df079
GN		 714 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
715 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
716 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
717 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
718 }
719 break;
720 }
721
722 return 0;
723}
338dbc97
GN		 724
725int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
726{
727 int res;
728
729 res = __kvm_set_dr(vcpu, dr, val);
730 if (res > 0)
731 kvm_queue_exception(vcpu, UD_VECTOR);
732 else if (res < 0)
733 kvm_inject_gp(vcpu, 0);
734
735 return res;
736}
020df079
GN		 737EXPORT_SYMBOL_GPL(kvm_set_dr);
738
338dbc97 739static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 740{
741 switch (dr) {
742 case 0 ... 3:
743 *val = vcpu->arch.db[dr];
744 break;
745 case 4:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 case 6:
750 *val = vcpu->arch.dr6;
751 break;
752 case 5:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 default: /* 7 */
757 *val = vcpu->arch.dr7;
758 break;
759 }
760
761 return 0;
762}
338dbc97
GN		 763
764int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
765{
766 if (_kvm_get_dr(vcpu, dr, val)) {
767 kvm_queue_exception(vcpu, UD_VECTOR);
768 return 1;
769 }
770 return 0;
771}
020df079
GN		 772EXPORT_SYMBOL_GPL(kvm_get_dr);
773
043405e1
CO		 774/*
775 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
776 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
777 *
778 * This list is modified at module load time to reflect the
e3267cbb
GC		 779 * capabilities of the host cpu. This capabilities test skips MSRs that are
780 * kvm-specific. Those are put in the beginning of the list.
043405e1 781 */
e3267cbb 782
11c6bffa 783#define KVM_SAVE_MSRS_BEGIN 7
043405e1 784static u32 msrs_to_save[] = {
e3267cbb 785 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 786 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 787 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 788 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1 789 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 790 MSR_STAR,
043405e1
CO		 791#ifdef CONFIG_X86_64
792 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
793#endif
e90aa41e 794 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 795};
796
797static unsigned num_msrs_to_save;
798
799static u32 emulated_msrs[] = {
800 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 801 MSR_IA32_MCG_STATUS,
802 MSR_IA32_MCG_CTL,
043405e1
CO		 803};
804
b69e8cae 805static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 806{
aad82703
SY		 807 u64 old_efer = vcpu->arch.efer;
808
b69e8cae
RJ		 809 if (efer & efer_reserved_bits)
810 return 1;
15c4a640
CO		 811
812 if (is_paging(vcpu)
b69e8cae
RJ		 813 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
814 return 1;
15c4a640 815
1b2fd70c
AG		 816 if (efer & EFER_FFXSR) {
817 struct kvm_cpuid_entry2 *feat;
818
819 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 820 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
821 return 1;
1b2fd70c
AG		 822 }
823
d8017474
AG		 824 if (efer & EFER_SVME) {
825 struct kvm_cpuid_entry2 *feat;
826
827 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 828 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
829 return 1;
d8017474
AG		 830 }
831
15c4a640 832 efer &= ~EFER_LMA;
f6801dff 833 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 834
a3d204e2
SY		 835 kvm_x86_ops->set_efer(vcpu, efer);
836
9645bb56
AK		 837 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
838 kvm_mmu_reset_context(vcpu);
b69e8cae 839
aad82703
SY		 840 /* Update reserved bits */
841 if ((efer ^ old_efer) & EFER_NX)
842 kvm_mmu_reset_context(vcpu);
843
b69e8cae 844 return 0;
15c4a640
CO		 845}
846
f2b4b7dd
JR		 847void kvm_enable_efer_bits(u64 mask)
848{
849 efer_reserved_bits &= ~mask;
850}
851EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
852
853
15c4a640
CO		 854/*
855 * Writes msr value into into the appropriate "register".
856 * Returns 0 on success, non-0 otherwise.
857 * Assumes vcpu_load() was already called.
858 */
859int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
860{
861 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
862}
863
313a3dc7
CO		 864/*
865 * Adapt set_msr() to msr_io()'s calling convention
866 */
867static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
868{
869 return kvm_set_msr(vcpu, index, *data);
870}
871
18068523
GOC		 872static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
873{
9ed3c444
AK		 874 int version;
875 int r;
50d0a0f9 876 struct pvclock_wall_clock wc;
923de3cf 877 struct timespec boot;
18068523
GOC		 878
879 if (!wall_clock)
880 return;
881
9ed3c444
AK		 882 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
883 if (r)
884 return;
885
886 if (version & 1)
887 ++version; /* first time write, random junk */
888
889 ++version;
18068523 890
18068523
GOC		 891 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
892
50d0a0f9
GH		 893 /*
894 * The guest calculates current wall clock time by adding
34c238a1 895 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 896 * wall clock specified here. guest system time equals host
897 * system time for us, thus we must fill in host boot time here.
898 */
923de3cf 899 getboottime(&boot);
50d0a0f9
GH		 900
901 wc.sec = boot.tv_sec;
902 wc.nsec = boot.tv_nsec;
903 wc.version = version;
18068523
GOC		 904
905 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
906
907 version++;
908 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 909}
910
50d0a0f9
GH		 911static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
912{
913 uint32_t quotient, remainder;
914
915 /* Don't try to replace with do_div(), this one calculates
916 * "(dividend << 32) / divisor" */
917 __asm__ ( "divl %4"
918 : "=a" (quotient), "=d" (remainder)
919 : "0" (0), "1" (dividend), "r" (divisor) );
920 return quotient;
921}
922
5f4e3f88
ZA		 923static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
924 s8 *pshift, u32 *pmultiplier)
50d0a0f9 925{
5f4e3f88 926 uint64_t scaled64;
50d0a0f9
GH		 927 int32_t shift = 0;
928 uint64_t tps64;
929 uint32_t tps32;
930
5f4e3f88
ZA		 931 tps64 = base_khz * 1000LL;
932 scaled64 = scaled_khz * 1000LL;
50933623 933 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 934 tps64 >>= 1;
935 shift--;
936 }
937
938 tps32 = (uint32_t)tps64;
50933623
JK		 939 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
940 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 941 scaled64 >>= 1;
942 else
943 tps32 <<= 1;
50d0a0f9
GH		 944 shift++;
945 }
946
5f4e3f88
ZA		 947 *pshift = shift;
948 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 949
5f4e3f88
ZA		 950 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
951 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 952}
953
759379dd
ZA		 954static inline u64 get_kernel_ns(void)
955{
956 struct timespec ts;
957
958 WARN_ON(preemptible());
959 ktime_get_ts(&ts);
960 monotonic_to_bootbased(&ts);
961 return timespec_to_ns(&ts);
962}
963
c8076604 964static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 965unsigned long max_tsc_khz;
c8076604 966
8cfdc000
ZA		 967static inline int kvm_tsc_changes_freq(void)
968{
969 int cpu = get_cpu();
970 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
971 cpufreq_quick_get(cpu) != 0;
972 put_cpu();
973 return ret;
974}
975
759379dd
ZA		 976static inline u64 nsec_to_cycles(u64 nsec)
977{
217fc9cf
AK		 978 u64 ret;
979
759379dd
ZA		 980 WARN_ON(preemptible());
981 if (kvm_tsc_changes_freq())
982 printk_once(KERN_WARNING
983 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
217fc9cf
AK		 984 ret = nsec * __get_cpu_var(cpu_tsc_khz);
985 do_div(ret, USEC_PER_SEC);
986 return ret;
759379dd
ZA		 987}
988
c285545f
ZA		 989static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
990{
991 /* Compute a scale to convert nanoseconds in TSC cycles */
992 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
993 &kvm->arch.virtual_tsc_shift,
994 &kvm->arch.virtual_tsc_mult);
995 kvm->arch.virtual_tsc_khz = this_tsc_khz;
996}
997
998static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
999{
1000 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1001 vcpu->kvm->arch.virtual_tsc_mult,
1002 vcpu->kvm->arch.virtual_tsc_shift);
1003 tsc += vcpu->arch.last_tsc_write;
1004 return tsc;
1005}
1006
99e3e30a
ZA		 1007void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1008{
1009 struct kvm *kvm = vcpu->kvm;
f38e098f 1010 u64 offset, ns, elapsed;
99e3e30a 1011 unsigned long flags;
46543ba4 1012 s64 sdiff;
99e3e30a
ZA		 1013
1014 spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1015 offset = data - native_read_tsc();
759379dd 1016 ns = get_kernel_ns();
f38e098f 1017 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1018 sdiff = data - kvm->arch.last_tsc_write;
1019 if (sdiff < 0)
1020 sdiff = -sdiff;
f38e098f
ZA		 1021
1022 /*
46543ba4 1023 * Special case: close write to TSC within 5 seconds of
f38e098f 1024 * another CPU is interpreted as an attempt to synchronize
46543ba4
ZA		 1025 * The 5 seconds is to accomodate host load / swapping as
1026 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1027 *
1028 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1029 * or make a best guest using elapsed value.
f38e098f 1030 */
46543ba4
ZA		 1031 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1032 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1033 if (!check_tsc_unstable()) {
1034 offset = kvm->arch.last_tsc_offset;
1035 pr_debug("kvm: matched tsc offset for %llu\n", data);
1036 } else {
759379dd
ZA		 1037 u64 delta = nsec_to_cycles(elapsed);
1038 offset += delta;
1039 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1040 }
1041 ns = kvm->arch.last_tsc_nsec;
1042 }
1043 kvm->arch.last_tsc_nsec = ns;
1044 kvm->arch.last_tsc_write = data;
1045 kvm->arch.last_tsc_offset = offset;
99e3e30a
ZA		 1046 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1047 spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1048
1049 /* Reset of TSC must disable overshoot protection below */
1050 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1051 vcpu->arch.last_tsc_write = data;
1052 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1053}
1054EXPORT_SYMBOL_GPL(kvm_write_tsc);
1055
34c238a1 1056static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1057{
18068523
GOC		 1058 unsigned long flags;
1059 struct kvm_vcpu_arch *vcpu = &v->arch;
1060 void *shared_kaddr;
463656c0 1061 unsigned long this_tsc_khz;
1d5f066e
ZA		 1062 s64 kernel_ns, max_kernel_ns;
1063 u64 tsc_timestamp;
18068523 1064
18068523
GOC		 1065 /* Keep irq disabled to prevent changes to the clock */
1066 local_irq_save(flags);
1d5f066e 1067 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1068 kernel_ns = get_kernel_ns();
8cfdc000 1069 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
18068523 1070
8cfdc000 1071 if (unlikely(this_tsc_khz == 0)) {
c285545f 1072 local_irq_restore(flags);
34c238a1 1073 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1074 return 1;
1075 }
18068523 1076
c285545f
ZA		 1077 /*
1078 * We may have to catch up the TSC to match elapsed wall clock
1079 * time for two reasons, even if kvmclock is used.
1080 * 1) CPU could have been running below the maximum TSC rate
1081 * 2) Broken TSC compensation resets the base at each VCPU
1082 * entry to avoid unknown leaps of TSC even when running
1083 * again on the same CPU. This may cause apparent elapsed
1084 * time to disappear, and the guest to stand still or run
1085 * very slowly.
1086 */
1087 if (vcpu->tsc_catchup) {
1088 u64 tsc = compute_guest_tsc(v, kernel_ns);
1089 if (tsc > tsc_timestamp) {
1090 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1091 tsc_timestamp = tsc;
1092 }
1093 }
1094
1095 local_irq_restore(flags);
1096
1097 if (!vcpu->time_page)
1098 return 0;
1099
1d5f066e
ZA		 1100 /*
1101 * Time as measured by the TSC may go backwards when resetting the base
1102 * tsc_timestamp. The reason for this is that the TSC resolution is
1103 * higher than the resolution of the other clock scales. Thus, many
1104 * possible measurments of the TSC correspond to one measurement of any
1105 * other clock, and so a spread of values is possible. This is not a
1106 * problem for the computation of the nanosecond clock; with TSC rates
1107 * around 1GHZ, there can only be a few cycles which correspond to one
1108 * nanosecond value, and any path through this code will inevitably
1109 * take longer than that. However, with the kernel_ns value itself,
1110 * the precision may be much lower, down to HZ granularity. If the
1111 * first sampling of TSC against kernel_ns ends in the low part of the
1112 * range, and the second in the high end of the range, we can get:
1113 *
1114 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1115 *
1116 * As the sampling errors potentially range in the thousands of cycles,
1117 * it is possible such a time value has already been observed by the
1118 * guest. To protect against this, we must compute the system time as
1119 * observed by the guest and ensure the new system time is greater.
1120 */
1121 max_kernel_ns = 0;
1122 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1123 max_kernel_ns = vcpu->last_guest_tsc -
1124 vcpu->hv_clock.tsc_timestamp;
1125 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1126 vcpu->hv_clock.tsc_to_system_mul,
1127 vcpu->hv_clock.tsc_shift);
1128 max_kernel_ns += vcpu->last_kernel_ns;
1129 }
1130
e48672fa 1131 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1132 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1133 &vcpu->hv_clock.tsc_shift,
1134 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1135 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1136 }
1137
1d5f066e
ZA		 1138 if (max_kernel_ns > kernel_ns)
1139 kernel_ns = max_kernel_ns;
1140
8cfdc000 1141 /* With all the info we got, fill in the values */
1d5f066e 1142 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1143 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1144 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1145 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1146 vcpu->hv_clock.flags = 0;
1147
18068523
GOC		 1148 /*
1149 * The interface expects us to write an even number signaling that the
1150 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1151 * state, we just increase by 2 at the end.
18068523 1152 */
50d0a0f9 1153 vcpu->hv_clock.version += 2;
18068523
GOC		 1154
1155 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1156
1157 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1158 sizeof(vcpu->hv_clock));
18068523
GOC		 1159
1160 kunmap_atomic(shared_kaddr, KM_USER0);
1161
1162 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1163 return 0;
18068523
GOC		 1164}
1165
9ba075a6
AK		 1166static bool msr_mtrr_valid(unsigned msr)
1167{
1168 switch (msr) {
1169 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1170 case MSR_MTRRfix64K_00000:
1171 case MSR_MTRRfix16K_80000:
1172 case MSR_MTRRfix16K_A0000:
1173 case MSR_MTRRfix4K_C0000:
1174 case MSR_MTRRfix4K_C8000:
1175 case MSR_MTRRfix4K_D0000:
1176 case MSR_MTRRfix4K_D8000:
1177 case MSR_MTRRfix4K_E0000:
1178 case MSR_MTRRfix4K_E8000:
1179 case MSR_MTRRfix4K_F0000:
1180 case MSR_MTRRfix4K_F8000:
1181 case MSR_MTRRdefType:
1182 case MSR_IA32_CR_PAT:
1183 return true;
1184 case 0x2f8:
1185 return true;
1186 }
1187 return false;
1188}
1189
d6289b93
MT		 1190static bool valid_pat_type(unsigned t)
1191{
1192 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1193}
1194
1195static bool valid_mtrr_type(unsigned t)
1196{
1197 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1198}
1199
1200static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1201{
1202 int i;
1203
1204 if (!msr_mtrr_valid(msr))
1205 return false;
1206
1207 if (msr == MSR_IA32_CR_PAT) {
1208 for (i = 0; i < 8; i++)
1209 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1210 return false;
1211 return true;
1212 } else if (msr == MSR_MTRRdefType) {
1213 if (data & ~0xcff)
1214 return false;
1215 return valid_mtrr_type(data & 0xff);
1216 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1217 for (i = 0; i < 8 ; i++)
1218 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1219 return false;
1220 return true;
1221 }
1222
1223 /* variable MTRRs */
1224 return valid_mtrr_type(data & 0xff);
1225}
1226
9ba075a6
AK		 1227static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1228{
0bed3b56
SY		 1229 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1230
d6289b93 1231 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1232 return 1;
1233
0bed3b56
SY		 1234 if (msr == MSR_MTRRdefType) {
1235 vcpu->arch.mtrr_state.def_type = data;
1236 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1237 } else if (msr == MSR_MTRRfix64K_00000)
1238 p[0] = data;
1239 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1240 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1241 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1242 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1243 else if (msr == MSR_IA32_CR_PAT)
1244 vcpu->arch.pat = data;
1245 else { /* Variable MTRRs */
1246 int idx, is_mtrr_mask;
1247 u64 *pt;
1248
1249 idx = (msr - 0x200) / 2;
1250 is_mtrr_mask = msr - 0x200 - 2 * idx;
1251 if (!is_mtrr_mask)
1252 pt =
1253 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1254 else
1255 pt =
1256 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1257 *pt = data;
1258 }
1259
1260 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1261 return 0;
1262}
15c4a640 1263
890ca9ae 1264static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1265{
890ca9ae
HY		 1266 u64 mcg_cap = vcpu->arch.mcg_cap;
1267 unsigned bank_num = mcg_cap & 0xff;
1268
15c4a640 1269 switch (msr) {
15c4a640 1270 case MSR_IA32_MCG_STATUS:
890ca9ae 1271 vcpu->arch.mcg_status = data;
15c4a640 1272 break;
c7ac679c 1273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1274 if (!(mcg_cap & MCG_CTL_P))
1275 return 1;
1276 if (data != 0 && data != ~(u64)0)
1277 return -1;
1278 vcpu->arch.mcg_ctl = data;
1279 break;
1280 default:
1281 if (msr >= MSR_IA32_MC0_CTL &&
1282 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1283 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1284 /* only 0 or all 1s can be written to IA32_MCi_CTL
1285 * some Linux kernels though clear bit 10 in bank 4 to
1286 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1287 * this to avoid an uncatched #GP in the guest
1288 */
890ca9ae 1289 if ((offset & 0x3) == 0 &&
114be429 1290 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1291 return -1;
1292 vcpu->arch.mce_banks[offset] = data;
1293 break;
1294 }
1295 return 1;
1296 }
1297 return 0;
1298}
1299
ffde22ac
ES		 1300static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1301{
1302 struct kvm *kvm = vcpu->kvm;
1303 int lm = is_long_mode(vcpu);
1304 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1305 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1306 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1307 : kvm->arch.xen_hvm_config.blob_size_32;
1308 u32 page_num = data & ~PAGE_MASK;
1309 u64 page_addr = data & PAGE_MASK;
1310 u8 *page;
1311 int r;
1312
1313 r = -E2BIG;
1314 if (page_num >= blob_size)
1315 goto out;
1316 r = -ENOMEM;
1317 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1318 if (!page)
1319 goto out;
1320 r = -EFAULT;
1321 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1322 goto out_free;
1323 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1324 goto out_free;
1325 r = 0;
1326out_free:
1327 kfree(page);
1328out:
1329 return r;
1330}
1331
55cd8e5a
GN		 1332static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1333{
1334 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1335}
1336
1337static bool kvm_hv_msr_partition_wide(u32 msr)
1338{
1339 bool r = false;
1340 switch (msr) {
1341 case HV_X64_MSR_GUEST_OS_ID:
1342 case HV_X64_MSR_HYPERCALL:
1343 r = true;
1344 break;
1345 }
1346
1347 return r;
1348}
1349
1350static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1351{
1352 struct kvm *kvm = vcpu->kvm;
1353
1354 switch (msr) {
1355 case HV_X64_MSR_GUEST_OS_ID:
1356 kvm->arch.hv_guest_os_id = data;
1357 /* setting guest os id to zero disables hypercall page */
1358 if (!kvm->arch.hv_guest_os_id)
1359 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1360 break;
1361 case HV_X64_MSR_HYPERCALL: {
1362 u64 gfn;
1363 unsigned long addr;
1364 u8 instructions[4];
1365
1366 /* if guest os id is not set hypercall should remain disabled */
1367 if (!kvm->arch.hv_guest_os_id)
1368 break;
1369 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1370 kvm->arch.hv_hypercall = data;
1371 break;
1372 }
1373 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1374 addr = gfn_to_hva(kvm, gfn);
1375 if (kvm_is_error_hva(addr))
1376 return 1;
1377 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1378 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1379 if (copy_to_user((void __user *)addr, instructions, 4))
1380 return 1;
1381 kvm->arch.hv_hypercall = data;
1382 break;
1383 }
1384 default:
1385 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1386 "data 0x%llx\n", msr, data);
1387 return 1;
1388 }
1389 return 0;
1390}
1391
1392static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1393{
10388a07
GN		 1394 switch (msr) {
1395 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1396 unsigned long addr;
55cd8e5a 1397
10388a07
GN		 1398 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1399 vcpu->arch.hv_vapic = data;
1400 break;
1401 }
1402 addr = gfn_to_hva(vcpu->kvm, data >>
1403 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1404 if (kvm_is_error_hva(addr))
1405 return 1;
1406 if (clear_user((void __user *)addr, PAGE_SIZE))
1407 return 1;
1408 vcpu->arch.hv_vapic = data;
1409 break;
1410 }
1411 case HV_X64_MSR_EOI:
1412 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1413 case HV_X64_MSR_ICR:
1414 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1415 case HV_X64_MSR_TPR:
1416 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1417 default:
1418 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1419 "data 0x%llx\n", msr, data);
1420 return 1;
1421 }
1422
1423 return 0;
55cd8e5a
GN		 1424}
1425
15c4a640
CO		 1426int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1427{
1428 switch (msr) {
15c4a640 1429 case MSR_EFER:
b69e8cae 1430 return set_efer(vcpu, data);
8f1589d9
AP		 1431 case MSR_K7_HWCR:
1432 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1433 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1434 if (data != 0) {
1435 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1436 data);
1437 return 1;
1438 }
15c4a640 1439 break;
f7c6d140
AP		 1440 case MSR_FAM10H_MMIO_CONF_BASE:
1441 if (data != 0) {
1442 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1443 "0x%llx\n", data);
1444 return 1;
1445 }
15c4a640 1446 break;
c323c0e5 1447 case MSR_AMD64_NB_CFG:
c7ac679c 1448 break;
b5e2fec0
AG		 1449 case MSR_IA32_DEBUGCTLMSR:
1450 if (!data) {
1451 /* We support the non-activated case already */
1452 break;
1453 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1454 /* Values other than LBR and BTF are vendor-specific,
1455 thus reserved and should throw a #GP */
1456 return 1;
1457 }
1458 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1459 __func__, data);
1460 break;
15c4a640
CO		 1461 case MSR_IA32_UCODE_REV:
1462 case MSR_IA32_UCODE_WRITE:
61a6bd67 1463 case MSR_VM_HSAVE_PA:
6098ca93 1464 case MSR_AMD64_PATCH_LOADER:
15c4a640 1465 break;
9ba075a6
AK		 1466 case 0x200 ... 0x2ff:
1467 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1468 case MSR_IA32_APICBASE:
1469 kvm_set_apic_base(vcpu, data);
1470 break;
0105d1a5
GN		 1471 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1472 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1473 case MSR_IA32_MISC_ENABLE:
ad312c7c 1474 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1475 break;
11c6bffa 1476 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1477 case MSR_KVM_WALL_CLOCK:
1478 vcpu->kvm->arch.wall_clock = data;
1479 kvm_write_wall_clock(vcpu->kvm, data);
1480 break;
11c6bffa 1481 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1482 case MSR_KVM_SYSTEM_TIME: {
1483 if (vcpu->arch.time_page) {
1484 kvm_release_page_dirty(vcpu->arch.time_page);
1485 vcpu->arch.time_page = NULL;
1486 }
1487
1488 vcpu->arch.time = data;
c285545f 1489 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1490
1491 /* we verify if the enable bit is set... */
1492 if (!(data & 1))
1493 break;
1494
1495 /* ...but clean it before doing the actual write */
1496 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1497
18068523
GOC		 1498 vcpu->arch.time_page =
1499 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1500
1501 if (is_error_page(vcpu->arch.time_page)) {
1502 kvm_release_page_clean(vcpu->arch.time_page);
1503 vcpu->arch.time_page = NULL;
1504 }
18068523
GOC		 1505 break;
1506 }
890ca9ae
HY		 1507 case MSR_IA32_MCG_CTL:
1508 case MSR_IA32_MCG_STATUS:
1509 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1510 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1511
1512 /* Performance counters are not protected by a CPUID bit,
1513 * so we should check all of them in the generic path for the sake of
1514 * cross vendor migration.
1515 * Writing a zero into the event select MSRs disables them,
1516 * which we perfectly emulate ;-). Any other value should be at least
1517 * reported, some guests depend on them.
1518 */
1519 case MSR_P6_EVNTSEL0:
1520 case MSR_P6_EVNTSEL1:
1521 case MSR_K7_EVNTSEL0:
1522 case MSR_K7_EVNTSEL1:
1523 case MSR_K7_EVNTSEL2:
1524 case MSR_K7_EVNTSEL3:
1525 if (data != 0)
1526 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1527 "0x%x data 0x%llx\n", msr, data);
1528 break;
1529 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1530 * so we ignore writes to make it happy.
1531 */
1532 case MSR_P6_PERFCTR0:
1533 case MSR_P6_PERFCTR1:
1534 case MSR_K7_PERFCTR0:
1535 case MSR_K7_PERFCTR1:
1536 case MSR_K7_PERFCTR2:
1537 case MSR_K7_PERFCTR3:
1538 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1539 "0x%x data 0x%llx\n", msr, data);
1540 break;
84e0cefa
JS		 1541 case MSR_K7_CLK_CTL:
1542 /*
1543 * Ignore all writes to this no longer documented MSR.
1544 * Writes are only relevant for old K7 processors,
1545 * all pre-dating SVM, but a recommended workaround from
1546 * AMD for these chips. It is possible to speicify the
1547 * affected processor models on the command line, hence
1548 * the need to ignore the workaround.
1549 */
1550 break;
55cd8e5a
GN		 1551 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1552 if (kvm_hv_msr_partition_wide(msr)) {
1553 int r;
1554 mutex_lock(&vcpu->kvm->lock);
1555 r = set_msr_hyperv_pw(vcpu, msr, data);
1556 mutex_unlock(&vcpu->kvm->lock);
1557 return r;
1558 } else
1559 return set_msr_hyperv(vcpu, msr, data);
1560 break;
15c4a640 1561 default:
ffde22ac
ES		 1562 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1563 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1564 if (!ignore_msrs) {
1565 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1566 msr, data);
1567 return 1;
1568 } else {
1569 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1570 msr, data);
1571 break;
1572 }
15c4a640
CO		 1573 }
1574 return 0;
1575}
1576EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1577
1578
1579/*
1580 * Reads an msr value (of 'msr_index') into 'pdata'.
1581 * Returns 0 on success, non-0 otherwise.
1582 * Assumes vcpu_load() was already called.
1583 */
1584int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1585{
1586 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1587}
1588
9ba075a6
AK		 1589static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1590{
0bed3b56
SY		 1591 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1592
9ba075a6
AK		 1593 if (!msr_mtrr_valid(msr))
1594 return 1;
1595
0bed3b56
SY		 1596 if (msr == MSR_MTRRdefType)
1597 *pdata = vcpu->arch.mtrr_state.def_type +
1598 (vcpu->arch.mtrr_state.enabled << 10);
1599 else if (msr == MSR_MTRRfix64K_00000)
1600 *pdata = p[0];
1601 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1602 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1603 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1604 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1605 else if (msr == MSR_IA32_CR_PAT)
1606 *pdata = vcpu->arch.pat;
1607 else { /* Variable MTRRs */
1608 int idx, is_mtrr_mask;
1609 u64 *pt;
1610
1611 idx = (msr - 0x200) / 2;
1612 is_mtrr_mask = msr - 0x200 - 2 * idx;
1613 if (!is_mtrr_mask)
1614 pt =
1615 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1616 else
1617 pt =
1618 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1619 *pdata = *pt;
1620 }
1621
9ba075a6
AK		 1622 return 0;
1623}
1624
890ca9ae 1625static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1626{
1627 u64 data;
890ca9ae
HY		 1628 u64 mcg_cap = vcpu->arch.mcg_cap;
1629 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1630
1631 switch (msr) {
15c4a640
CO		 1632 case MSR_IA32_P5_MC_ADDR:
1633 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1634 data = 0;
1635 break;
15c4a640 1636 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1637 data = vcpu->arch.mcg_cap;
1638 break;
c7ac679c 1639 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1640 if (!(mcg_cap & MCG_CTL_P))
1641 return 1;
1642 data = vcpu->arch.mcg_ctl;
1643 break;
1644 case MSR_IA32_MCG_STATUS:
1645 data = vcpu->arch.mcg_status;
1646 break;
1647 default:
1648 if (msr >= MSR_IA32_MC0_CTL &&
1649 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1650 u32 offset = msr - MSR_IA32_MC0_CTL;
1651 data = vcpu->arch.mce_banks[offset];
1652 break;
1653 }
1654 return 1;
1655 }
1656 *pdata = data;
1657 return 0;
1658}
1659
55cd8e5a
GN		 1660static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1661{
1662 u64 data = 0;
1663 struct kvm *kvm = vcpu->kvm;
1664
1665 switch (msr) {
1666 case HV_X64_MSR_GUEST_OS_ID:
1667 data = kvm->arch.hv_guest_os_id;
1668 break;
1669 case HV_X64_MSR_HYPERCALL:
1670 data = kvm->arch.hv_hypercall;
1671 break;
1672 default:
1673 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1674 return 1;
1675 }
1676
1677 *pdata = data;
1678 return 0;
1679}
1680
1681static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1682{
1683 u64 data = 0;
1684
1685 switch (msr) {
1686 case HV_X64_MSR_VP_INDEX: {
1687 int r;
1688 struct kvm_vcpu *v;
1689 kvm_for_each_vcpu(r, v, vcpu->kvm)
1690 if (v == vcpu)
1691 data = r;
1692 break;
1693 }
10388a07
GN		 1694 case HV_X64_MSR_EOI:
1695 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1696 case HV_X64_MSR_ICR:
1697 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1698 case HV_X64_MSR_TPR:
1699 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1700 default:
1701 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1702 return 1;
1703 }
1704 *pdata = data;
1705 return 0;
1706}
1707
890ca9ae
HY		 1708int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1709{
1710 u64 data;
1711
1712 switch (msr) {
890ca9ae 1713 case MSR_IA32_PLATFORM_ID:
15c4a640 1714 case MSR_IA32_UCODE_REV:
15c4a640 1715 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1716 case MSR_IA32_DEBUGCTLMSR:
1717 case MSR_IA32_LASTBRANCHFROMIP:
1718 case MSR_IA32_LASTBRANCHTOIP:
1719 case MSR_IA32_LASTINTFROMIP:
1720 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1721 case MSR_K8_SYSCFG:
1722 case MSR_K7_HWCR:
61a6bd67 1723 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1724 case MSR_P6_PERFCTR0:
1725 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1726 case MSR_P6_EVNTSEL0:
1727 case MSR_P6_EVNTSEL1:
9e699624 1728 case MSR_K7_EVNTSEL0:
1f3ee616 1729 case MSR_K7_PERFCTR0:
1fdbd48c 1730 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1731 case MSR_AMD64_NB_CFG:
f7c6d140 1732 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1733 data = 0;
1734 break;
9ba075a6
AK		 1735 case MSR_MTRRcap:
1736 data = 0x500 | KVM_NR_VAR_MTRR;
1737 break;
1738 case 0x200 ... 0x2ff:
1739 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1740 case 0xcd: /* fsb frequency */
1741 data = 3;
1742 break;
7b914098
JS		 1743 /*
1744 * MSR_EBC_FREQUENCY_ID
1745 * Conservative value valid for even the basic CPU models.
1746 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1747 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1748 * and 266MHz for model 3, or 4. Set Core Clock
1749 * Frequency to System Bus Frequency Ratio to 1 (bits
1750 * 31:24) even though these are only valid for CPU
1751 * models > 2, however guests may end up dividing or
1752 * multiplying by zero otherwise.
1753 */
1754 case MSR_EBC_FREQUENCY_ID:
1755 data = 1 << 24;
1756 break;
15c4a640
CO		 1757 case MSR_IA32_APICBASE:
1758 data = kvm_get_apic_base(vcpu);
1759 break;
0105d1a5
GN		 1760 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1761 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1762 break;
15c4a640 1763 case MSR_IA32_MISC_ENABLE:
ad312c7c 1764 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1765 break;
847f0ad8
AG		 1766 case MSR_IA32_PERF_STATUS:
1767 /* TSC increment by tick */
1768 data = 1000ULL;
1769 /* CPU multiplier */
1770 data |= (((uint64_t)4ULL) << 40);
1771 break;
15c4a640 1772 case MSR_EFER:
f6801dff 1773 data = vcpu->arch.efer;
15c4a640 1774 break;
18068523 1775 case MSR_KVM_WALL_CLOCK:
11c6bffa 1776 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1777 data = vcpu->kvm->arch.wall_clock;
1778 break;
1779 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1780 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1781 data = vcpu->arch.time;
1782 break;
890ca9ae
HY		 1783 case MSR_IA32_P5_MC_ADDR:
1784 case MSR_IA32_P5_MC_TYPE:
1785 case MSR_IA32_MCG_CAP:
1786 case MSR_IA32_MCG_CTL:
1787 case MSR_IA32_MCG_STATUS:
1788 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1789 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1790 case MSR_K7_CLK_CTL:
1791 /*
1792 * Provide expected ramp-up count for K7. All other
1793 * are set to zero, indicating minimum divisors for
1794 * every field.
1795 *
1796 * This prevents guest kernels on AMD host with CPU
1797 * type 6, model 8 and higher from exploding due to
1798 * the rdmsr failing.
1799 */
1800 data = 0x20000000;
1801 break;
55cd8e5a
GN		 1802 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1803 if (kvm_hv_msr_partition_wide(msr)) {
1804 int r;
1805 mutex_lock(&vcpu->kvm->lock);
1806 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1807 mutex_unlock(&vcpu->kvm->lock);
1808 return r;
1809 } else
1810 return get_msr_hyperv(vcpu, msr, pdata);
1811 break;
15c4a640 1812 default:
ed85c068
AP		 1813 if (!ignore_msrs) {
1814 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1815 return 1;
1816 } else {
1817 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1818 data = 0;
1819 }
1820 break;
15c4a640
CO		 1821 }
1822 *pdata = data;
1823 return 0;
1824}
1825EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1826
313a3dc7
CO		 1827/*
1828 * Read or write a bunch of msrs. All parameters are kernel addresses.
1829 *
1830 * @return number of msrs set successfully.
1831 */
1832static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1833 struct kvm_msr_entry *entries,
1834 int (*do_msr)(struct kvm_vcpu *vcpu,
1835 unsigned index, u64 *data))
1836{
f656ce01 1837 int i, idx;
313a3dc7 1838
f656ce01 1839 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1840 for (i = 0; i < msrs->nmsrs; ++i)
1841 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1842 break;
f656ce01 1843 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1844
313a3dc7
CO		 1845 return i;
1846}
1847
1848/*
1849 * Read or write a bunch of msrs. Parameters are user addresses.
1850 *
1851 * @return number of msrs set successfully.
1852 */
1853static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1854 int (*do_msr)(struct kvm_vcpu *vcpu,
1855 unsigned index, u64 *data),
1856 int writeback)
1857{
1858 struct kvm_msrs msrs;
1859 struct kvm_msr_entry *entries;
1860 int r, n;
1861 unsigned size;
1862
1863 r = -EFAULT;
1864 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1865 goto out;
1866
1867 r = -E2BIG;
1868 if (msrs.nmsrs >= MAX_IO_MSRS)
1869 goto out;
1870
1871 r = -ENOMEM;
1872 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1873 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1874 if (!entries)
1875 goto out;
1876
1877 r = -EFAULT;
1878 if (copy_from_user(entries, user_msrs->entries, size))
1879 goto out_free;
1880
1881 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1882 if (r < 0)
1883 goto out_free;
1884
1885 r = -EFAULT;
1886 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1887 goto out_free;
1888
1889 r = n;
1890
1891out_free:
7a73c028 1892 kfree(entries);
313a3dc7
CO		 1893out:
1894 return r;
1895}
1896
018d00d2
ZX		 1897int kvm_dev_ioctl_check_extension(long ext)
1898{
1899 int r;
1900
1901 switch (ext) {
1902 case KVM_CAP_IRQCHIP:
1903 case KVM_CAP_HLT:
1904 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1905 case KVM_CAP_SET_TSS_ADDR:
07716717 1906 case KVM_CAP_EXT_CPUID:
c8076604 1907 case KVM_CAP_CLOCKSOURCE:
7837699f 1908 case KVM_CAP_PIT:
a28e4f5a 1909 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1910 case KVM_CAP_MP_STATE:
ed848624 1911 case KVM_CAP_SYNC_MMU:
52d939a0 1912 case KVM_CAP_REINJECT_CONTROL:
4925663a 1913 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1914 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1915 case KVM_CAP_IRQFD:
d34e6b17 1916 case KVM_CAP_IOEVENTFD:
c5ff41ce 1917 case KVM_CAP_PIT2:
e9f42757 1918 case KVM_CAP_PIT_STATE2:
b927a3ce 1919 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1920 case KVM_CAP_XEN_HVM:
afbcf7ab 1921 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1922 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1923 case KVM_CAP_HYPERV:
10388a07 1924 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1925 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1926 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1927 case KVM_CAP_DEBUGREGS:
d2be1651 1928 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1929 case KVM_CAP_XSAVE:
018d00d2
ZX		 1930 r = 1;
1931 break;
542472b5
LV		 1932 case KVM_CAP_COALESCED_MMIO:
1933 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1934 break;
774ead3a
AK		 1935 case KVM_CAP_VAPIC:
1936 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1937 break;
f725230a
AK		 1938 case KVM_CAP_NR_VCPUS:
1939 r = KVM_MAX_VCPUS;
1940 break;
a988b910
AK		 1941 case KVM_CAP_NR_MEMSLOTS:
1942 r = KVM_MEMORY_SLOTS;
1943 break;
a68a6a72
MT		 1944 case KVM_CAP_PV_MMU: /* obsolete */
1945 r = 0;
2f333bcb 1946 break;
62c476c7 1947 case KVM_CAP_IOMMU:
19de40a8 1948 r = iommu_found();
62c476c7 1949 break;
890ca9ae
HY		 1950 case KVM_CAP_MCE:
1951 r = KVM_MAX_MCE_BANKS;
1952 break;
2d5b5a66
SY		 1953 case KVM_CAP_XCRS:
1954 r = cpu_has_xsave;
1955 break;
018d00d2
ZX		 1956 default:
1957 r = 0;
1958 break;
1959 }
1960 return r;
1961
1962}
1963
043405e1
CO		 1964long kvm_arch_dev_ioctl(struct file *filp,
1965 unsigned int ioctl, unsigned long arg)
1966{
1967 void __user *argp = (void __user *)arg;
1968 long r;
1969
1970 switch (ioctl) {
1971 case KVM_GET_MSR_INDEX_LIST: {
1972 struct kvm_msr_list __user *user_msr_list = argp;
1973 struct kvm_msr_list msr_list;
1974 unsigned n;
1975
1976 r = -EFAULT;
1977 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1978 goto out;
1979 n = msr_list.nmsrs;
1980 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1981 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1982 goto out;
1983 r = -E2BIG;
e125e7b6 1984 if (n < msr_list.nmsrs)
043405e1
CO		 1985 goto out;
1986 r = -EFAULT;
1987 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1988 num_msrs_to_save * sizeof(u32)))
1989 goto out;
e125e7b6 1990 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1991 &emulated_msrs,
1992 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1993 goto out;
1994 r = 0;
1995 break;
1996 }
674eea0f
AK		 1997 case KVM_GET_SUPPORTED_CPUID: {
1998 struct kvm_cpuid2 __user *cpuid_arg = argp;
1999 struct kvm_cpuid2 cpuid;
2000
2001 r = -EFAULT;
2002 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2003 goto out;
2004 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2005 cpuid_arg->entries);
674eea0f
AK		 2006 if (r)
2007 goto out;
2008
2009 r = -EFAULT;
2010 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2011 goto out;
2012 r = 0;
2013 break;
2014 }
890ca9ae
HY		 2015 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2016 u64 mce_cap;
2017
2018 mce_cap = KVM_MCE_CAP_SUPPORTED;
2019 r = -EFAULT;
2020 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2021 goto out;
2022 r = 0;
2023 break;
2024 }
043405e1
CO		 2025 default:
2026 r = -EINVAL;
2027 }
2028out:
2029 return r;
2030}
2031
f5f48ee1
SY		 2032static void wbinvd_ipi(void *garbage)
2033{
2034 wbinvd();
2035}
2036
2037static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2038{
2039 return vcpu->kvm->arch.iommu_domain &&
2040 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2041}
2042
313a3dc7
CO		 2043void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2044{
f5f48ee1
SY		 2045 /* Address WBINVD may be executed by guest */
2046 if (need_emulate_wbinvd(vcpu)) {
2047 if (kvm_x86_ops->has_wbinvd_exit())
2048 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2049 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2050 smp_call_function_single(vcpu->cpu,
2051 wbinvd_ipi, NULL, 1);
2052 }
2053
313a3dc7 2054 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2055 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2056 /* Make sure TSC doesn't go backwards */
2057 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2058 native_read_tsc() - vcpu->arch.last_host_tsc;
2059 if (tsc_delta < 0)
2060 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2061 if (check_tsc_unstable()) {
e48672fa 2062 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f
ZA		 2063 vcpu->arch.tsc_catchup = 1;
2064 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2065 }
2066 if (vcpu->cpu != cpu)
2067 kvm_migrate_timers(vcpu);
e48672fa
ZA		 2068 vcpu->cpu = cpu;
2069 }
313a3dc7
CO		 2070}
2071
2072void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2073{
02daab21 2074 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2075 kvm_put_guest_fpu(vcpu);
e48672fa 2076 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2077}
2078
07716717 2079static int is_efer_nx(void)
313a3dc7 2080{
e286e86e 2081 unsigned long long efer = 0;
313a3dc7 2082
e286e86e 2083 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2084 return efer & EFER_NX;
2085}
2086
2087static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2088{
2089 int i;
2090 struct kvm_cpuid_entry2 *e, *entry;
2091
313a3dc7 2092 entry = NULL;
ad312c7c
ZX		 2093 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2094 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2095 if (e->function == 0x80000001) {
2096 entry = e;
2097 break;
2098 }
2099 }
07716717 2100 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2101 entry->edx &= ~(1 << 20);
2102 printk(KERN_INFO "kvm: guest NX capability removed\n");
2103 }
2104}
2105
07716717 2106/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2107static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2108 struct kvm_cpuid *cpuid,
2109 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2110{
2111 int r, i;
2112 struct kvm_cpuid_entry *cpuid_entries;
2113
2114 r = -E2BIG;
2115 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2116 goto out;
2117 r = -ENOMEM;
2118 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2119 if (!cpuid_entries)
2120 goto out;
2121 r = -EFAULT;
2122 if (copy_from_user(cpuid_entries, entries,
2123 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2124 goto out_free;
2125 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2126 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2127 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2128 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2129 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2130 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2131 vcpu->arch.cpuid_entries[i].index = 0;
2132 vcpu->arch.cpuid_entries[i].flags = 0;
2133 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2134 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2135 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2136 }
2137 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2138 cpuid_fix_nx_cap(vcpu);
2139 r = 0;
fc61b800 2140 kvm_apic_set_version(vcpu);
0e851880 2141 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2142 update_cpuid(vcpu);
07716717
DK		 2143
2144out_free:
2145 vfree(cpuid_entries);
2146out:
2147 return r;
2148}
2149
2150static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2151 struct kvm_cpuid2 *cpuid,
2152 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2153{
2154 int r;
2155
2156 r = -E2BIG;
2157 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2158 goto out;
2159 r = -EFAULT;
ad312c7c 2160 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2161 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2162 goto out;
ad312c7c 2163 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2164 kvm_apic_set_version(vcpu);
0e851880 2165 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2166 update_cpuid(vcpu);
313a3dc7
CO		 2167 return 0;
2168
2169out:
2170 return r;
2171}
2172
07716717 2173static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2174 struct kvm_cpuid2 *cpuid,
2175 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2176{
2177 int r;
2178
2179 r = -E2BIG;
ad312c7c 2180 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2181 goto out;
2182 r = -EFAULT;
ad312c7c 2183 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2184 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2185 goto out;
2186 return 0;
2187
2188out:
ad312c7c 2189 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2190 return r;
2191}
2192
07716717 2193static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2194 u32 index)
07716717
DK		 2195{
2196 entry->function = function;
2197 entry->index = index;
2198 cpuid_count(entry->function, entry->index,
19355475 2199 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2200 entry->flags = 0;
2201}
2202
7faa4ee1
AK		 2203#define F(x) bit(X86_FEATURE_##x)
2204
07716717
DK		 2205static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2206 u32 index, int *nent, int maxnent)
2207{
7faa4ee1 2208 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2209#ifdef CONFIG_X86_64
17cc3935
SY		 2210 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2211 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2212 unsigned f_lm = F(LM);
2213#else
17cc3935 2214 unsigned f_gbpages = 0;
7faa4ee1 2215 unsigned f_lm = 0;
07716717 2216#endif
4e47c7a6 2217 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2218
2219 /* cpuid 1.edx */
2220 const u32 kvm_supported_word0_x86_features =
2221 F(FPU) | F(VME) | F(DE) | F(PSE) |
2222 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2223 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2224 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2225 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2226 0 /* Reserved, DS, ACPI */ | F(MMX) |
2227 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2228 0 /* HTT, TM, Reserved, PBE */;
2229 /* cpuid 0x80000001.edx */
2230 const u32 kvm_supported_word1_x86_features =
2231 F(FPU) | F(VME) | F(DE) | F(PSE) |
2232 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2233 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2234 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2235 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2236 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2237 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2238 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2239 /* cpuid 1.ecx */
2240 const u32 kvm_supported_word4_x86_features =
6c3f6041 2241 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2242 0 /* DS-CPL, VMX, SMX, EST */ |
2243 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2244 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2245 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2246 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6c3f6041 2247 0 /* Reserved, AES */ | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX);
7faa4ee1 2248 /* cpuid 0x80000001.ecx */
07716717 2249 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2250 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1
AK		 2251 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
2252 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
2253 0 /* SKINIT */ | 0 /* WDT */;
07716717 2254
19355475 2255 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2256 get_cpu();
2257 do_cpuid_1_ent(entry, function, index);
2258 ++*nent;
2259
2260 switch (function) {
2261 case 0:
2acf923e 2262 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2263 break;
2264 case 1:
2265 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 2266 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 2267 /* we support x2apic emulation even if host does not support
2268 * it since we emulate x2apic in software */
2269 entry->ecx |= F(X2APIC);
07716717
DK		 2270 break;
2271 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2272 * may return different values. This forces us to get_cpu() before
2273 * issuing the first command, and also to emulate this annoying behavior
2274 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2275 case 2: {
2276 int t, times = entry->eax & 0xff;
2277
2278 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2279 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2280 for (t = 1; t < times && *nent < maxnent; ++t) {
2281 do_cpuid_1_ent(&entry[t], function, 0);
2282 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2283 ++*nent;
2284 }
2285 break;
2286 }
2287 /* function 4 and 0xb have additional index. */
2288 case 4: {
14af3f3c 2289 int i, cache_type;
07716717
DK		 2290
2291 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2292 /* read more entries until cache_type is zero */
14af3f3c
HH		 2293 for (i = 1; *nent < maxnent; ++i) {
2294 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2295 if (!cache_type)
2296 break;
14af3f3c
HH		 2297 do_cpuid_1_ent(&entry[i], function, i);
2298 entry[i].flags |=
07716717
DK		 2299 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2300 ++*nent;
2301 }
2302 break;
2303 }
2304 case 0xb: {
14af3f3c 2305 int i, level_type;
07716717
DK		 2306
2307 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2308 /* read more entries until level_type is zero */
14af3f3c 2309 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2310 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2311 if (!level_type)
2312 break;
14af3f3c
HH		 2313 do_cpuid_1_ent(&entry[i], function, i);
2314 entry[i].flags |=
07716717
DK		 2315 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2316 ++*nent;
2317 }
2318 break;
2319 }
2acf923e
DC		 2320 case 0xd: {
2321 int i;
2322
2323 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2324 for (i = 1; *nent < maxnent; ++i) {
2325 if (entry[i - 1].eax == 0 && i != 2)
2326 break;
2327 do_cpuid_1_ent(&entry[i], function, i);
2328 entry[i].flags |=
2329 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2330 ++*nent;
2331 }
2332 break;
2333 }
84478c82
GC		 2334 case KVM_CPUID_SIGNATURE: {
2335 char signature[12] = "KVMKVMKVM\0\0";
2336 u32 *sigptr = (u32 *)signature;
2337 entry->eax = 0;
2338 entry->ebx = sigptr[0];
2339 entry->ecx = sigptr[1];
2340 entry->edx = sigptr[2];
2341 break;
2342 }
2343 case KVM_CPUID_FEATURES:
2344 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2345 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64
GC		 2346 (1 << KVM_FEATURE_CLOCKSOURCE2) |
2347 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2348 entry->ebx = 0;
2349 entry->ecx = 0;
2350 entry->edx = 0;
2351 break;
07716717
DK		 2352 case 0x80000000:
2353 entry->eax = min(entry->eax, 0x8000001a);
2354 break;
2355 case 0x80000001:
2356 entry->edx &= kvm_supported_word1_x86_features;
2357 entry->ecx &= kvm_supported_word6_x86_features;
2358 break;
2359 }
d4330ef2
JR		 2360
2361 kvm_x86_ops->set_supported_cpuid(function, entry);
2362
07716717
DK		 2363 put_cpu();
2364}
2365
7faa4ee1
AK		 2366#undef F
2367
674eea0f 2368static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2369 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2370{
2371 struct kvm_cpuid_entry2 *cpuid_entries;
2372 int limit, nent = 0, r = -E2BIG;
2373 u32 func;
2374
2375 if (cpuid->nent < 1)
2376 goto out;
6a544355
AK		 2377 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2378 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2379 r = -ENOMEM;
2380 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2381 if (!cpuid_entries)
2382 goto out;
2383
2384 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2385 limit = cpuid_entries[0].eax;
2386 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2387 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2388 &nent, cpuid->nent);
07716717
DK		 2389 r = -E2BIG;
2390 if (nent >= cpuid->nent)
2391 goto out_free;
2392
2393 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2394 limit = cpuid_entries[nent - 1].eax;
2395 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2396 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2397 &nent, cpuid->nent);
84478c82
GC		 2398
2399
2400
2401 r = -E2BIG;
2402 if (nent >= cpuid->nent)
2403 goto out_free;
2404
2405 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2406 cpuid->nent);
2407
2408 r = -E2BIG;
2409 if (nent >= cpuid->nent)
2410 goto out_free;
2411
2412 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2413 cpuid->nent);
2414
cb007648
MM		 2415 r = -E2BIG;
2416 if (nent >= cpuid->nent)
2417 goto out_free;
2418
07716717
DK		 2419 r = -EFAULT;
2420 if (copy_to_user(entries, cpuid_entries,
19355475 2421 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2422 goto out_free;
2423 cpuid->nent = nent;
2424 r = 0;
2425
2426out_free:
2427 vfree(cpuid_entries);
2428out:
2429 return r;
2430}
2431
313a3dc7
CO		 2432static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2433 struct kvm_lapic_state *s)
2434{
ad312c7c 2435 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2436
2437 return 0;
2438}
2439
2440static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2441 struct kvm_lapic_state *s)
2442{
ad312c7c 2443 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2444 kvm_apic_post_state_restore(vcpu);
cb142eb7 2445 update_cr8_intercept(vcpu);
313a3dc7
CO		 2446
2447 return 0;
2448}
2449
f77bc6a4
ZX		 2450static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2451 struct kvm_interrupt *irq)
2452{
2453 if (irq->irq < 0 || irq->irq >= 256)
2454 return -EINVAL;
2455 if (irqchip_in_kernel(vcpu->kvm))
2456 return -ENXIO;
f77bc6a4 2457
66fd3f7f 2458 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2459 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2460
f77bc6a4
ZX		 2461 return 0;
2462}
2463
c4abb7c9
JK		 2464static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2465{
c4abb7c9 2466 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2467
2468 return 0;
2469}
2470
b209749f
AK		 2471static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2472 struct kvm_tpr_access_ctl *tac)
2473{
2474 if (tac->flags)
2475 return -EINVAL;
2476 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2477 return 0;
2478}
2479
890ca9ae
HY		 2480static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2481 u64 mcg_cap)
2482{
2483 int r;
2484 unsigned bank_num = mcg_cap & 0xff, bank;
2485
2486 r = -EINVAL;
a9e38c3e 2487 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2488 goto out;
2489 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2490 goto out;
2491 r = 0;
2492 vcpu->arch.mcg_cap = mcg_cap;
2493 /* Init IA32_MCG_CTL to all 1s */
2494 if (mcg_cap & MCG_CTL_P)
2495 vcpu->arch.mcg_ctl = ~(u64)0;
2496 /* Init IA32_MCi_CTL to all 1s */
2497 for (bank = 0; bank < bank_num; bank++)
2498 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2499out:
2500 return r;
2501}
2502
2503static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2504 struct kvm_x86_mce *mce)
2505{
2506 u64 mcg_cap = vcpu->arch.mcg_cap;
2507 unsigned bank_num = mcg_cap & 0xff;
2508 u64 *banks = vcpu->arch.mce_banks;
2509
2510 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2511 return -EINVAL;
2512 /*
2513 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2514 * reporting is disabled
2515 */
2516 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2517 vcpu->arch.mcg_ctl != ~(u64)0)
2518 return 0;
2519 banks += 4 * mce->bank;
2520 /*
2521 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2522 * reporting is disabled for the bank
2523 */
2524 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2525 return 0;
2526 if (mce->status & MCI_STATUS_UC) {
2527 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2528 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2529 printk(KERN_DEBUG "kvm: set_mce: "
2530 "injects mce exception while "
2531 "previous one is in progress!\n");
a8eeb04a 2532 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2533 return 0;
2534 }
2535 if (banks[1] & MCI_STATUS_VAL)
2536 mce->status |= MCI_STATUS_OVER;
2537 banks[2] = mce->addr;
2538 banks[3] = mce->misc;
2539 vcpu->arch.mcg_status = mce->mcg_status;
2540 banks[1] = mce->status;
2541 kvm_queue_exception(vcpu, MC_VECTOR);
2542 } else if (!(banks[1] & MCI_STATUS_VAL)
2543 || !(banks[1] & MCI_STATUS_UC)) {
2544 if (banks[1] & MCI_STATUS_VAL)
2545 mce->status |= MCI_STATUS_OVER;
2546 banks[2] = mce->addr;
2547 banks[3] = mce->misc;
2548 banks[1] = mce->status;
2549 } else
2550 banks[1] |= MCI_STATUS_OVER;
2551 return 0;
2552}
2553
3cfc3092
JK		 2554static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2555 struct kvm_vcpu_events *events)
2556{
03b82a30
JK		 2557 events->exception.injected =
2558 vcpu->arch.exception.pending &&
2559 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2560 events->exception.nr = vcpu->arch.exception.nr;
2561 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2562 events->exception.error_code = vcpu->arch.exception.error_code;
2563
03b82a30
JK		 2564 events->interrupt.injected =
2565 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2566 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2567 events->interrupt.soft = 0;
48005f64
JK		 2568 events->interrupt.shadow =
2569 kvm_x86_ops->get_interrupt_shadow(vcpu,
2570 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2571
2572 events->nmi.injected = vcpu->arch.nmi_injected;
2573 events->nmi.pending = vcpu->arch.nmi_pending;
2574 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2575
2576 events->sipi_vector = vcpu->arch.sipi_vector;
2577
dab4b911 2578 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2579 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2580 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2581}
2582
2583static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2584 struct kvm_vcpu_events *events)
2585{
dab4b911 2586 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2587 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2588 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2589 return -EINVAL;
2590
3cfc3092
JK		 2591 vcpu->arch.exception.pending = events->exception.injected;
2592 vcpu->arch.exception.nr = events->exception.nr;
2593 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2594 vcpu->arch.exception.error_code = events->exception.error_code;
2595
2596 vcpu->arch.interrupt.pending = events->interrupt.injected;
2597 vcpu->arch.interrupt.nr = events->interrupt.nr;
2598 vcpu->arch.interrupt.soft = events->interrupt.soft;
2599 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2600 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2601 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2602 kvm_x86_ops->set_interrupt_shadow(vcpu,
2603 events->interrupt.shadow);
3cfc3092
JK		 2604
2605 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2606 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2607 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2608 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2609
dab4b911
JK		 2610 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2611 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2612
3842d135
AK		 2613 kvm_make_request(KVM_REQ_EVENT, vcpu);
2614
3cfc3092
JK		 2615 return 0;
2616}
2617
a1efbe77
JK		 2618static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2619 struct kvm_debugregs *dbgregs)
2620{
a1efbe77
JK		 2621 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2622 dbgregs->dr6 = vcpu->arch.dr6;
2623 dbgregs->dr7 = vcpu->arch.dr7;
2624 dbgregs->flags = 0;
a1efbe77
JK		 2625}
2626
2627static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2628 struct kvm_debugregs *dbgregs)
2629{
2630 if (dbgregs->flags)
2631 return -EINVAL;
2632
a1efbe77
JK		 2633 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2634 vcpu->arch.dr6 = dbgregs->dr6;
2635 vcpu->arch.dr7 = dbgregs->dr7;
2636
a1efbe77
JK		 2637 return 0;
2638}
2639
2d5b5a66
SY		 2640static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2641 struct kvm_xsave *guest_xsave)
2642{
2643 if (cpu_has_xsave)
2644 memcpy(guest_xsave->region,
2645 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2646 xstate_size);
2d5b5a66
SY		 2647 else {
2648 memcpy(guest_xsave->region,
2649 &vcpu->arch.guest_fpu.state->fxsave,
2650 sizeof(struct i387_fxsave_struct));
2651 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2652 XSTATE_FPSSE;
2653 }
2654}
2655
2656static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2657 struct kvm_xsave *guest_xsave)
2658{
2659 u64 xstate_bv =
2660 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2661
2662 if (cpu_has_xsave)
2663 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2664 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2665 else {
2666 if (xstate_bv & ~XSTATE_FPSSE)
2667 return -EINVAL;
2668 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2669 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2670 }
2671 return 0;
2672}
2673
2674static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2675 struct kvm_xcrs *guest_xcrs)
2676{
2677 if (!cpu_has_xsave) {
2678 guest_xcrs->nr_xcrs = 0;
2679 return;
2680 }
2681
2682 guest_xcrs->nr_xcrs = 1;
2683 guest_xcrs->flags = 0;
2684 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2685 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2686}
2687
2688static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2689 struct kvm_xcrs *guest_xcrs)
2690{
2691 int i, r = 0;
2692
2693 if (!cpu_has_xsave)
2694 return -EINVAL;
2695
2696 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2697 return -EINVAL;
2698
2699 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2700 /* Only support XCR0 currently */
2701 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2702 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2703 guest_xcrs->xcrs[0].value);
2704 break;
2705 }
2706 if (r)
2707 r = -EINVAL;
2708 return r;
2709}
2710
313a3dc7
CO		 2711long kvm_arch_vcpu_ioctl(struct file *filp,
2712 unsigned int ioctl, unsigned long arg)
2713{
2714 struct kvm_vcpu *vcpu = filp->private_data;
2715 void __user *argp = (void __user *)arg;
2716 int r;
d1ac91d8
AK		 2717 union {
2718 struct kvm_lapic_state *lapic;
2719 struct kvm_xsave *xsave;
2720 struct kvm_xcrs *xcrs;
2721 void *buffer;
2722 } u;
2723
2724 u.buffer = NULL;
313a3dc7
CO		 2725 switch (ioctl) {
2726 case KVM_GET_LAPIC: {
2204ae3c
MT		 2727 r = -EINVAL;
2728 if (!vcpu->arch.apic)
2729 goto out;
d1ac91d8 2730 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2731
b772ff36 2732 r = -ENOMEM;
d1ac91d8 2733 if (!u.lapic)
b772ff36 2734 goto out;
d1ac91d8 2735 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2736 if (r)
2737 goto out;
2738 r = -EFAULT;
d1ac91d8 2739 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2740 goto out;
2741 r = 0;
2742 break;
2743 }
2744 case KVM_SET_LAPIC: {
2204ae3c
MT		 2745 r = -EINVAL;
2746 if (!vcpu->arch.apic)
2747 goto out;
d1ac91d8 2748 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2749 r = -ENOMEM;
d1ac91d8 2750 if (!u.lapic)
b772ff36 2751 goto out;
313a3dc7 2752 r = -EFAULT;
d1ac91d8 2753 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2754 goto out;
d1ac91d8 2755 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2756 if (r)
2757 goto out;
2758 r = 0;
2759 break;
2760 }
f77bc6a4
ZX		 2761 case KVM_INTERRUPT: {
2762 struct kvm_interrupt irq;
2763
2764 r = -EFAULT;
2765 if (copy_from_user(&irq, argp, sizeof irq))
2766 goto out;
2767 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2768 if (r)
2769 goto out;
2770 r = 0;
2771 break;
2772 }
c4abb7c9
JK		 2773 case KVM_NMI: {
2774 r = kvm_vcpu_ioctl_nmi(vcpu);
2775 if (r)
2776 goto out;
2777 r = 0;
2778 break;
2779 }
313a3dc7
CO		 2780 case KVM_SET_CPUID: {
2781 struct kvm_cpuid __user *cpuid_arg = argp;
2782 struct kvm_cpuid cpuid;
2783
2784 r = -EFAULT;
2785 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2786 goto out;
2787 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2788 if (r)
2789 goto out;
2790 break;
2791 }
07716717
DK		 2792 case KVM_SET_CPUID2: {
2793 struct kvm_cpuid2 __user *cpuid_arg = argp;
2794 struct kvm_cpuid2 cpuid;
2795
2796 r = -EFAULT;
2797 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2798 goto out;
2799 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2800 cpuid_arg->entries);
07716717
DK		 2801 if (r)
2802 goto out;
2803 break;
2804 }
2805 case KVM_GET_CPUID2: {
2806 struct kvm_cpuid2 __user *cpuid_arg = argp;
2807 struct kvm_cpuid2 cpuid;
2808
2809 r = -EFAULT;
2810 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2811 goto out;
2812 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2813 cpuid_arg->entries);
07716717
DK		 2814 if (r)
2815 goto out;
2816 r = -EFAULT;
2817 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2818 goto out;
2819 r = 0;
2820 break;
2821 }
313a3dc7
CO		 2822 case KVM_GET_MSRS:
2823 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2824 break;
2825 case KVM_SET_MSRS:
2826 r = msr_io(vcpu, argp, do_set_msr, 0);
2827 break;
b209749f
AK		 2828 case KVM_TPR_ACCESS_REPORTING: {
2829 struct kvm_tpr_access_ctl tac;
2830
2831 r = -EFAULT;
2832 if (copy_from_user(&tac, argp, sizeof tac))
2833 goto out;
2834 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2835 if (r)
2836 goto out;
2837 r = -EFAULT;
2838 if (copy_to_user(argp, &tac, sizeof tac))
2839 goto out;
2840 r = 0;
2841 break;
2842 };
b93463aa
AK		 2843 case KVM_SET_VAPIC_ADDR: {
2844 struct kvm_vapic_addr va;
2845
2846 r = -EINVAL;
2847 if (!irqchip_in_kernel(vcpu->kvm))
2848 goto out;
2849 r = -EFAULT;
2850 if (copy_from_user(&va, argp, sizeof va))
2851 goto out;
2852 r = 0;
2853 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2854 break;
2855 }
890ca9ae
HY		 2856 case KVM_X86_SETUP_MCE: {
2857 u64 mcg_cap;
2858
2859 r = -EFAULT;
2860 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2861 goto out;
2862 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2863 break;
2864 }
2865 case KVM_X86_SET_MCE: {
2866 struct kvm_x86_mce mce;
2867
2868 r = -EFAULT;
2869 if (copy_from_user(&mce, argp, sizeof mce))
2870 goto out;
2871 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2872 break;
2873 }
3cfc3092
JK		 2874 case KVM_GET_VCPU_EVENTS: {
2875 struct kvm_vcpu_events events;
2876
2877 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2878
2879 r = -EFAULT;
2880 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2881 break;
2882 r = 0;
2883 break;
2884 }
2885 case KVM_SET_VCPU_EVENTS: {
2886 struct kvm_vcpu_events events;
2887
2888 r = -EFAULT;
2889 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2890 break;
2891
2892 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2893 break;
2894 }
a1efbe77
JK		 2895 case KVM_GET_DEBUGREGS: {
2896 struct kvm_debugregs dbgregs;
2897
2898 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2899
2900 r = -EFAULT;
2901 if (copy_to_user(argp, &dbgregs,
2902 sizeof(struct kvm_debugregs)))
2903 break;
2904 r = 0;
2905 break;
2906 }
2907 case KVM_SET_DEBUGREGS: {
2908 struct kvm_debugregs dbgregs;
2909
2910 r = -EFAULT;
2911 if (copy_from_user(&dbgregs, argp,
2912 sizeof(struct kvm_debugregs)))
2913 break;
2914
2915 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2916 break;
2917 }
2d5b5a66 2918 case KVM_GET_XSAVE: {
d1ac91d8 2919 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2920 r = -ENOMEM;
d1ac91d8 2921 if (!u.xsave)
2d5b5a66
SY		 2922 break;
2923
d1ac91d8 2924 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2925
2926 r = -EFAULT;
d1ac91d8 2927 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2928 break;
2929 r = 0;
2930 break;
2931 }
2932 case KVM_SET_XSAVE: {
d1ac91d8 2933 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2934 r = -ENOMEM;
d1ac91d8 2935 if (!u.xsave)
2d5b5a66
SY		 2936 break;
2937
2938 r = -EFAULT;
d1ac91d8 2939 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2940 break;
2941
d1ac91d8 2942 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2943 break;
2944 }
2945 case KVM_GET_XCRS: {
d1ac91d8 2946 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2947 r = -ENOMEM;
d1ac91d8 2948 if (!u.xcrs)
2d5b5a66
SY		 2949 break;
2950
d1ac91d8 2951 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2952
2953 r = -EFAULT;
d1ac91d8 2954 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2955 sizeof(struct kvm_xcrs)))
2956 break;
2957 r = 0;
2958 break;
2959 }
2960 case KVM_SET_XCRS: {
d1ac91d8 2961 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2962 r = -ENOMEM;
d1ac91d8 2963 if (!u.xcrs)
2d5b5a66
SY		 2964 break;
2965
2966 r = -EFAULT;
d1ac91d8 2967 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 2968 sizeof(struct kvm_xcrs)))
2969 break;
2970
d1ac91d8 2971 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2972 break;
2973 }
313a3dc7
CO		 2974 default:
2975 r = -EINVAL;
2976 }
2977out:
d1ac91d8 2978 kfree(u.buffer);
313a3dc7
CO		 2979 return r;
2980}
2981
1fe779f8
CO		 2982static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2983{
2984 int ret;
2985
2986 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2987 return -1;
2988 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2989 return ret;
2990}
2991
b927a3ce
SY		 2992static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2993 u64 ident_addr)
2994{
2995 kvm->arch.ept_identity_map_addr = ident_addr;
2996 return 0;
2997}
2998
1fe779f8
CO		 2999static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3000 u32 kvm_nr_mmu_pages)
3001{
3002 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3003 return -EINVAL;
3004
79fac95e 3005 mutex_lock(&kvm->slots_lock);
7c8a83b7 3006 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3007
3008 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3009 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3010
7c8a83b7 3011 spin_unlock(&kvm->mmu_lock);
79fac95e 3012 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3013 return 0;
3014}
3015
3016static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3017{
39de71ec 3018 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3019}
3020
1fe779f8
CO		 3021static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3022{
3023 int r;
3024
3025 r = 0;
3026 switch (chip->chip_id) {
3027 case KVM_IRQCHIP_PIC_MASTER:
3028 memcpy(&chip->chip.pic,
3029 &pic_irqchip(kvm)->pics[0],
3030 sizeof(struct kvm_pic_state));
3031 break;
3032 case KVM_IRQCHIP_PIC_SLAVE:
3033 memcpy(&chip->chip.pic,
3034 &pic_irqchip(kvm)->pics[1],
3035 sizeof(struct kvm_pic_state));
3036 break;
3037 case KVM_IRQCHIP_IOAPIC:
eba0226b 3038 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3039 break;
3040 default:
3041 r = -EINVAL;
3042 break;
3043 }
3044 return r;
3045}
3046
3047static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3048{
3049 int r;
3050
3051 r = 0;
3052 switch (chip->chip_id) {
3053 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3054 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3055 memcpy(&pic_irqchip(kvm)->pics[0],
3056 &chip->chip.pic,
3057 sizeof(struct kvm_pic_state));
f4f51050 3058 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3059 break;
3060 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3061 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3062 memcpy(&pic_irqchip(kvm)->pics[1],
3063 &chip->chip.pic,
3064 sizeof(struct kvm_pic_state));
f4f51050 3065 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3066 break;
3067 case KVM_IRQCHIP_IOAPIC:
eba0226b 3068 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3069 break;
3070 default:
3071 r = -EINVAL;
3072 break;
3073 }
3074 kvm_pic_update_irq(pic_irqchip(kvm));
3075 return r;
3076}
3077
e0f63cb9
SY		 3078static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3079{
3080 int r = 0;
3081
894a9c55 3082 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3083 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3084 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3085 return r;
3086}
3087
3088static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3089{
3090 int r = 0;
3091
894a9c55 3092 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3093 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3094 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3095 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3096 return r;
3097}
3098
3099static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3100{
3101 int r = 0;
3102
3103 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3104 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3105 sizeof(ps->channels));
3106 ps->flags = kvm->arch.vpit->pit_state.flags;
3107 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3108 return r;
3109}
3110
3111static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3112{
3113 int r = 0, start = 0;
3114 u32 prev_legacy, cur_legacy;
3115 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3116 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3117 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3118 if (!prev_legacy && cur_legacy)
3119 start = 1;
3120 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3121 sizeof(kvm->arch.vpit->pit_state.channels));
3122 kvm->arch.vpit->pit_state.flags = ps->flags;
3123 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3124 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3125 return r;
3126}
3127
52d939a0
MT		 3128static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3129 struct kvm_reinject_control *control)
3130{
3131 if (!kvm->arch.vpit)
3132 return -ENXIO;
894a9c55 3133 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3134 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3135 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3136 return 0;
3137}
3138
5bb064dc
ZX		 3139/*
3140 * Get (and clear) the dirty memory log for a memory slot.
3141 */
3142int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3143 struct kvm_dirty_log *log)
3144{
87bf6e7d 3145 int r, i;
5bb064dc 3146 struct kvm_memory_slot *memslot;
87bf6e7d 3147 unsigned long n;
b050b015 3148 unsigned long is_dirty = 0;
5bb064dc 3149
79fac95e 3150 mutex_lock(&kvm->slots_lock);
5bb064dc 3151
b050b015
MT		 3152 r = -EINVAL;
3153 if (log->slot >= KVM_MEMORY_SLOTS)
3154 goto out;
3155
3156 memslot = &kvm->memslots->memslots[log->slot];
3157 r = -ENOENT;
3158 if (!memslot->dirty_bitmap)
3159 goto out;
3160
87bf6e7d 3161 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3162
b050b015
MT		 3163 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3164 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3165
3166 /* If nothing is dirty, don't bother messing with page tables. */
3167 if (is_dirty) {
b050b015 3168 struct kvm_memslots *slots, *old_slots;
914ebccd 3169 unsigned long *dirty_bitmap;
b050b015 3170
7c8a83b7 3171 spin_lock(&kvm->mmu_lock);
5bb064dc 3172 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 3173 spin_unlock(&kvm->mmu_lock);
b050b015 3174
914ebccd
TY		 3175 r = -ENOMEM;
3176 dirty_bitmap = vmalloc(n);
3177 if (!dirty_bitmap)
3178 goto out;
3179 memset(dirty_bitmap, 0, n);
b050b015 3180
914ebccd
TY		 3181 r = -ENOMEM;
3182 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
3183 if (!slots) {
3184 vfree(dirty_bitmap);
3185 goto out;
3186 }
b050b015
MT		 3187 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3188 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
3189
3190 old_slots = kvm->memslots;
3191 rcu_assign_pointer(kvm->memslots, slots);
3192 synchronize_srcu_expedited(&kvm->srcu);
3193 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3194 kfree(old_slots);
914ebccd
TY		 3195
3196 r = -EFAULT;
3197 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n)) {
3198 vfree(dirty_bitmap);
3199 goto out;
3200 }
3201 vfree(dirty_bitmap);
3202 } else {
3203 r = -EFAULT;
3204 if (clear_user(log->dirty_bitmap, n))
3205 goto out;
5bb064dc 3206 }
b050b015 3207
5bb064dc
ZX		 3208 r = 0;
3209out:
79fac95e 3210 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3211 return r;
3212}
3213
1fe779f8
CO		 3214long kvm_arch_vm_ioctl(struct file *filp,
3215 unsigned int ioctl, unsigned long arg)
3216{
3217 struct kvm *kvm = filp->private_data;
3218 void __user *argp = (void __user *)arg;
367e1319 3219 int r = -ENOTTY;
f0d66275
DH		 3220 /*
3221 * This union makes it completely explicit to gcc-3.x
3222 * that these two variables' stack usage should be
3223 * combined, not added together.
3224 */
3225 union {
3226 struct kvm_pit_state ps;
e9f42757 3227 struct kvm_pit_state2 ps2;
c5ff41ce 3228 struct kvm_pit_config pit_config;
f0d66275 3229 } u;
1fe779f8
CO		 3230
3231 switch (ioctl) {
3232 case KVM_SET_TSS_ADDR:
3233 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3234 if (r < 0)
3235 goto out;
3236 break;
b927a3ce
SY		 3237 case KVM_SET_IDENTITY_MAP_ADDR: {
3238 u64 ident_addr;
3239
3240 r = -EFAULT;
3241 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3242 goto out;
3243 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3244 if (r < 0)
3245 goto out;
3246 break;
3247 }
1fe779f8
CO		 3248 case KVM_SET_NR_MMU_PAGES:
3249 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3250 if (r)
3251 goto out;
3252 break;
3253 case KVM_GET_NR_MMU_PAGES:
3254 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3255 break;
3ddea128
MT		 3256 case KVM_CREATE_IRQCHIP: {
3257 struct kvm_pic *vpic;
3258
3259 mutex_lock(&kvm->lock);
3260 r = -EEXIST;
3261 if (kvm->arch.vpic)
3262 goto create_irqchip_unlock;
1fe779f8 3263 r = -ENOMEM;
3ddea128
MT		 3264 vpic = kvm_create_pic(kvm);
3265 if (vpic) {
1fe779f8
CO		 3266 r = kvm_ioapic_init(kvm);
3267 if (r) {
72bb2fcd
WY		 3268 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3269 &vpic->dev);
3ddea128
MT		 3270 kfree(vpic);
3271 goto create_irqchip_unlock;
1fe779f8
CO		 3272 }
3273 } else
3ddea128
MT		 3274 goto create_irqchip_unlock;
3275 smp_wmb();
3276 kvm->arch.vpic = vpic;
3277 smp_wmb();
399ec807
AK		 3278 r = kvm_setup_default_irq_routing(kvm);
3279 if (r) {
3ddea128 3280 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3281 kvm_ioapic_destroy(kvm);
3282 kvm_destroy_pic(kvm);
3ddea128 3283 mutex_unlock(&kvm->irq_lock);
399ec807 3284 }
3ddea128
MT		 3285 create_irqchip_unlock:
3286 mutex_unlock(&kvm->lock);
1fe779f8 3287 break;
3ddea128 3288 }
7837699f 3289 case KVM_CREATE_PIT:
c5ff41ce
JK		 3290 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3291 goto create_pit;
3292 case KVM_CREATE_PIT2:
3293 r = -EFAULT;
3294 if (copy_from_user(&u.pit_config, argp,
3295 sizeof(struct kvm_pit_config)))
3296 goto out;
3297 create_pit:
79fac95e 3298 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3299 r = -EEXIST;
3300 if (kvm->arch.vpit)
3301 goto create_pit_unlock;
7837699f 3302 r = -ENOMEM;
c5ff41ce 3303 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3304 if (kvm->arch.vpit)
3305 r = 0;
269e05e4 3306 create_pit_unlock:
79fac95e 3307 mutex_unlock(&kvm->slots_lock);
7837699f 3308 break;
4925663a 3309 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3310 case KVM_IRQ_LINE: {
3311 struct kvm_irq_level irq_event;
3312
3313 r = -EFAULT;
3314 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3315 goto out;
160d2f6c 3316 r = -ENXIO;
1fe779f8 3317 if (irqchip_in_kernel(kvm)) {
4925663a 3318 __s32 status;
4925663a
GN		 3319 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3320 irq_event.irq, irq_event.level);
4925663a 3321 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3322 r = -EFAULT;
4925663a
GN		 3323 irq_event.status = status;
3324 if (copy_to_user(argp, &irq_event,
3325 sizeof irq_event))
3326 goto out;
3327 }
1fe779f8
CO		 3328 r = 0;
3329 }
3330 break;
3331 }
3332 case KVM_GET_IRQCHIP: {
3333 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3334 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3335
f0d66275
DH		 3336 r = -ENOMEM;
3337 if (!chip)
1fe779f8 3338 goto out;
f0d66275
DH		 3339 r = -EFAULT;
3340 if (copy_from_user(chip, argp, sizeof *chip))
3341 goto get_irqchip_out;
1fe779f8
CO		 3342 r = -ENXIO;
3343 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3344 goto get_irqchip_out;
3345 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3346 if (r)
f0d66275 3347 goto get_irqchip_out;
1fe779f8 3348 r = -EFAULT;
f0d66275
DH		 3349 if (copy_to_user(argp, chip, sizeof *chip))
3350 goto get_irqchip_out;
1fe779f8 3351 r = 0;
f0d66275
DH		 3352 get_irqchip_out:
3353 kfree(chip);
3354 if (r)
3355 goto out;
1fe779f8
CO		 3356 break;
3357 }
3358 case KVM_SET_IRQCHIP: {
3359 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3360 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3361
f0d66275
DH		 3362 r = -ENOMEM;
3363 if (!chip)
1fe779f8 3364 goto out;
f0d66275
DH		 3365 r = -EFAULT;
3366 if (copy_from_user(chip, argp, sizeof *chip))
3367 goto set_irqchip_out;
1fe779f8
CO		 3368 r = -ENXIO;
3369 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3370 goto set_irqchip_out;
3371 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3372 if (r)
f0d66275 3373 goto set_irqchip_out;
1fe779f8 3374 r = 0;
f0d66275
DH		 3375 set_irqchip_out:
3376 kfree(chip);
3377 if (r)
3378 goto out;
1fe779f8
CO		 3379 break;
3380 }
e0f63cb9 3381 case KVM_GET_PIT: {
e0f63cb9 3382 r = -EFAULT;
f0d66275 3383 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3384 goto out;
3385 r = -ENXIO;
3386 if (!kvm->arch.vpit)
3387 goto out;
f0d66275 3388 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3389 if (r)
3390 goto out;
3391 r = -EFAULT;
f0d66275 3392 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3393 goto out;
3394 r = 0;
3395 break;
3396 }
3397 case KVM_SET_PIT: {
e0f63cb9 3398 r = -EFAULT;
f0d66275 3399 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3400 goto out;
3401 r = -ENXIO;
3402 if (!kvm->arch.vpit)
3403 goto out;
f0d66275 3404 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3405 if (r)
3406 goto out;
3407 r = 0;
3408 break;
3409 }
e9f42757
BK		 3410 case KVM_GET_PIT2: {
3411 r = -ENXIO;
3412 if (!kvm->arch.vpit)
3413 goto out;
3414 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3415 if (r)
3416 goto out;
3417 r = -EFAULT;
3418 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3419 goto out;
3420 r = 0;
3421 break;
3422 }
3423 case KVM_SET_PIT2: {
3424 r = -EFAULT;
3425 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3426 goto out;
3427 r = -ENXIO;
3428 if (!kvm->arch.vpit)
3429 goto out;
3430 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3431 if (r)
3432 goto out;
3433 r = 0;
3434 break;
3435 }
52d939a0
MT		 3436 case KVM_REINJECT_CONTROL: {
3437 struct kvm_reinject_control control;
3438 r = -EFAULT;
3439 if (copy_from_user(&control, argp, sizeof(control)))
3440 goto out;
3441 r = kvm_vm_ioctl_reinject(kvm, &control);
3442 if (r)
3443 goto out;
3444 r = 0;
3445 break;
3446 }
ffde22ac
ES		 3447 case KVM_XEN_HVM_CONFIG: {
3448 r = -EFAULT;
3449 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3450 sizeof(struct kvm_xen_hvm_config)))
3451 goto out;
3452 r = -EINVAL;
3453 if (kvm->arch.xen_hvm_config.flags)
3454 goto out;
3455 r = 0;
3456 break;
3457 }
afbcf7ab 3458 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3459 struct kvm_clock_data user_ns;
3460 u64 now_ns;
3461 s64 delta;
3462
3463 r = -EFAULT;
3464 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3465 goto out;
3466
3467 r = -EINVAL;
3468 if (user_ns.flags)
3469 goto out;
3470
3471 r = 0;
395c6b0a 3472 local_irq_disable();
759379dd 3473 now_ns = get_kernel_ns();
afbcf7ab 3474 delta = user_ns.clock - now_ns;
395c6b0a 3475 local_irq_enable();
afbcf7ab
GC		 3476 kvm->arch.kvmclock_offset = delta;
3477 break;
3478 }
3479 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3480 struct kvm_clock_data user_ns;
3481 u64 now_ns;
3482
395c6b0a 3483 local_irq_disable();
759379dd 3484 now_ns = get_kernel_ns();
afbcf7ab 3485 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3486 local_irq_enable();
afbcf7ab
GC		 3487 user_ns.flags = 0;
3488
3489 r = -EFAULT;
3490 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3491 goto out;
3492 r = 0;
3493 break;
3494 }
3495
1fe779f8
CO		 3496 default:
3497 ;
3498 }
3499out:
3500 return r;
3501}
3502
a16b043c 3503static void kvm_init_msr_list(void)
043405e1
CO		 3504{
3505 u32 dummy[2];
3506 unsigned i, j;
3507
e3267cbb
GC		 3508 /* skip the first msrs in the list. KVM-specific */
3509 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3510 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3511 continue;
3512 if (j < i)
3513 msrs_to_save[j] = msrs_to_save[i];
3514 j++;
3515 }
3516 num_msrs_to_save = j;
3517}
3518
bda9020e
MT		 3519static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3520 const void *v)
bbd9b64e 3521{
bda9020e
MT		 3522 if (vcpu->arch.apic &&
3523 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3524 return 0;
bbd9b64e 3525
e93f8a0f 3526 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3527}
3528
bda9020e 3529static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3530{
bda9020e
MT		 3531 if (vcpu->arch.apic &&
3532 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3533 return 0;
bbd9b64e 3534
e93f8a0f 3535 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3536}
3537
2dafc6c2
GN		 3538static void kvm_set_segment(struct kvm_vcpu *vcpu,
3539 struct kvm_segment *var, int seg)
3540{
3541 kvm_x86_ops->set_segment(vcpu, var, seg);
3542}
3543
3544void kvm_get_segment(struct kvm_vcpu *vcpu,
3545 struct kvm_segment *var, int seg)
3546{
3547 kvm_x86_ops->get_segment(vcpu, var, seg);
3548}
3549
c30a358d
JR		 3550static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3551{
3552 return gpa;
3553}
3554
02f59dc9
JR		 3555static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3556{
3557 gpa_t t_gpa;
3558 u32 error;
3559
3560 BUG_ON(!mmu_is_nested(vcpu));
3561
3562 /* NPT walks are always user-walks */
3563 access |= PFERR_USER_MASK;
3564 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &error);
3565 if (t_gpa == UNMAPPED_GVA)
0959ffac 3566 vcpu->arch.fault.nested = true;
02f59dc9
JR		 3567
3568 return t_gpa;
3569}
3570
1871c602
GN		 3571gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3572{
3573 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
14dfe855 3574 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3575}
3576
3577 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3578{
3579 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3580 access |= PFERR_FETCH_MASK;
14dfe855 3581 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3582}
3583
3584gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3585{
3586 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3587 access |= PFERR_WRITE_MASK;
14dfe855 3588 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, error);
1871c602
GN		 3589}
3590
3591/* uses this to access any guest's mapped memory without checking CPL */
3592gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3593{
14dfe855 3594 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, error);
1871c602
GN		 3595}
3596
3597static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3598 struct kvm_vcpu *vcpu, u32 access,
3599 u32 *error)
bbd9b64e
CO		 3600{
3601 void *data = val;
10589a46 3602 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3603
3604 while (bytes) {
14dfe855
JR		 3605 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3606 error);
bbd9b64e 3607 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3608 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3609 int ret;
3610
10589a46
MT		 3611 if (gpa == UNMAPPED_GVA) {
3612 r = X86EMUL_PROPAGATE_FAULT;
3613 goto out;
3614 }
77c2002e 3615 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3616 if (ret < 0) {
c3cd7ffa 3617 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3618 goto out;
3619 }
bbd9b64e 3620
77c2002e
IE		 3621 bytes -= toread;
3622 data += toread;
3623 addr += toread;
bbd9b64e 3624 }
10589a46 3625out:
10589a46 3626 return r;
bbd9b64e 3627}
77c2002e 3628
1871c602
GN		 3629/* used for instruction fetching */
3630static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3631 struct kvm_vcpu *vcpu, u32 *error)
3632{
3633 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3634 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3635 access | PFERR_FETCH_MASK, error);
3636}
3637
3638static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3639 struct kvm_vcpu *vcpu, u32 *error)
3640{
3641 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3642 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3643 error);
3644}
3645
3646static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3647 struct kvm_vcpu *vcpu, u32 *error)
3648{
3649 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3650}
3651
7972995b 3652static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3653 unsigned int bytes,
7972995b 3654 struct kvm_vcpu *vcpu,
2dafc6c2 3655 u32 *error)
77c2002e
IE		 3656{
3657 void *data = val;
3658 int r = X86EMUL_CONTINUE;
3659
3660 while (bytes) {
14dfe855
JR		 3661 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3662 PFERR_WRITE_MASK,
3663 error);
77c2002e
IE		 3664 unsigned offset = addr & (PAGE_SIZE-1);
3665 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3666 int ret;
3667
3668 if (gpa == UNMAPPED_GVA) {
3669 r = X86EMUL_PROPAGATE_FAULT;
3670 goto out;
3671 }
3672 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3673 if (ret < 0) {
c3cd7ffa 3674 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3675 goto out;
3676 }
3677
3678 bytes -= towrite;
3679 data += towrite;
3680 addr += towrite;
3681 }
3682out:
3683 return r;
3684}
3685
bbd9b64e
CO		 3686static int emulator_read_emulated(unsigned long addr,
3687 void *val,
3688 unsigned int bytes,
8fe681e9 3689 unsigned int *error_code,
bbd9b64e
CO		 3690 struct kvm_vcpu *vcpu)
3691{
bbd9b64e
CO		 3692 gpa_t gpa;
3693
3694 if (vcpu->mmio_read_completed) {
3695 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3696 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3697 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3698 vcpu->mmio_read_completed = 0;
3699 return X86EMUL_CONTINUE;
3700 }
3701
8fe681e9 3702 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, error_code);
1871c602 3703
8fe681e9 3704 if (gpa == UNMAPPED_GVA)
1871c602 3705 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3706
3707 /* For APIC access vmexit */
3708 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3709 goto mmio;
3710
1871c602 3711 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3712 == X86EMUL_CONTINUE)
bbd9b64e 3713 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3714
3715mmio:
3716 /*
3717 * Is this MMIO handled locally?
3718 */
aec51dc4
AK		 3719 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3720 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3721 return X86EMUL_CONTINUE;
3722 }
aec51dc4
AK		 3723
3724 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3725
3726 vcpu->mmio_needed = 1;
411c35b7
GN		 3727 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3728 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3729 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3730 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
bbd9b64e 3731
c3cd7ffa 3732 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3733}
3734
3200f405 3735int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3736 const void *val, int bytes)
bbd9b64e
CO		 3737{
3738 int ret;
3739
3740 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3741 if (ret < 0)
bbd9b64e 3742 return 0;
ad218f85 3743 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3744 return 1;
3745}
3746
3747static int emulator_write_emulated_onepage(unsigned long addr,
3748 const void *val,
3749 unsigned int bytes,
8fe681e9 3750 unsigned int *error_code,
bbd9b64e
CO		 3751 struct kvm_vcpu *vcpu)
3752{
10589a46
MT		 3753 gpa_t gpa;
3754
8fe681e9 3755 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error_code);
bbd9b64e 3756
8fe681e9 3757 if (gpa == UNMAPPED_GVA)
bbd9b64e 3758 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3759
3760 /* For APIC access vmexit */
3761 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3762 goto mmio;
3763
3764 if (emulator_write_phys(vcpu, gpa, val, bytes))
3765 return X86EMUL_CONTINUE;
3766
3767mmio:
aec51dc4 3768 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3769 /*
3770 * Is this MMIO handled locally?
3771 */
bda9020e 3772 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3773 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3774
3775 vcpu->mmio_needed = 1;
411c35b7
GN		 3776 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3777 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
3778 vcpu->run->mmio.len = vcpu->mmio_size = bytes;
3779 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
3780 memcpy(vcpu->run->mmio.data, val, bytes);
bbd9b64e
CO		 3781
3782 return X86EMUL_CONTINUE;
3783}
3784
3785int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3786 const void *val,
3787 unsigned int bytes,
8fe681e9 3788 unsigned int *error_code,
8f6abd06 3789 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3790{
3791 /* Crossing a page boundary? */
3792 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3793 int rc, now;
3794
3795 now = -addr & ~PAGE_MASK;
8fe681e9
GN		 3796 rc = emulator_write_emulated_onepage(addr, val, now, error_code,
3797 vcpu);
bbd9b64e
CO		 3798 if (rc != X86EMUL_CONTINUE)
3799 return rc;
3800 addr += now;
3801 val += now;
3802 bytes -= now;
3803 }
8fe681e9
GN		 3804 return emulator_write_emulated_onepage(addr, val, bytes, error_code,
3805 vcpu);
bbd9b64e 3806}
bbd9b64e 3807
daea3e73
AK		 3808#define CMPXCHG_TYPE(t, ptr, old, new) \
3809 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3810
3811#ifdef CONFIG_X86_64
3812# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3813#else
3814# define CMPXCHG64(ptr, old, new) \
9749a6c0 3815 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3816#endif
3817
bbd9b64e
CO		 3818static int emulator_cmpxchg_emulated(unsigned long addr,
3819 const void *old,
3820 const void *new,
3821 unsigned int bytes,
8fe681e9 3822 unsigned int *error_code,
bbd9b64e
CO		 3823 struct kvm_vcpu *vcpu)
3824{
daea3e73
AK		 3825 gpa_t gpa;
3826 struct page *page;
3827 char *kaddr;
3828 bool exchanged;
2bacc55c 3829
daea3e73
AK		 3830 /* guests cmpxchg8b have to be emulated atomically */
3831 if (bytes > 8 || (bytes & (bytes - 1)))
3832 goto emul_write;
10589a46 3833
daea3e73 3834 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3835
daea3e73
AK		 3836 if (gpa == UNMAPPED_GVA ||
3837 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3838 goto emul_write;
2bacc55c 3839
daea3e73
AK		 3840 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3841 goto emul_write;
72dc67a6 3842
daea3e73 3843 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3844 if (is_error_page(page)) {
3845 kvm_release_page_clean(page);
3846 goto emul_write;
3847 }
72dc67a6 3848
daea3e73
AK		 3849 kaddr = kmap_atomic(page, KM_USER0);
3850 kaddr += offset_in_page(gpa);
3851 switch (bytes) {
3852 case 1:
3853 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3854 break;
3855 case 2:
3856 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3857 break;
3858 case 4:
3859 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3860 break;
3861 case 8:
3862 exchanged = CMPXCHG64(kaddr, old, new);
3863 break;
3864 default:
3865 BUG();
2bacc55c 3866 }
daea3e73
AK		 3867 kunmap_atomic(kaddr, KM_USER0);
3868 kvm_release_page_dirty(page);
3869
3870 if (!exchanged)
3871 return X86EMUL_CMPXCHG_FAILED;
3872
8f6abd06
GN		 3873 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3874
3875 return X86EMUL_CONTINUE;
4a5f48f6 3876
3200f405 3877emul_write:
daea3e73 3878 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3879
8fe681e9 3880 return emulator_write_emulated(addr, new, bytes, error_code, vcpu);
bbd9b64e
CO		 3881}
3882
cf8f70bf
GN		 3883static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3884{
3885 /* TODO: String I/O for in kernel device */
3886 int r;
3887
3888 if (vcpu->arch.pio.in)
3889 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3890 vcpu->arch.pio.size, pd);
3891 else
3892 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3893 vcpu->arch.pio.port, vcpu->arch.pio.size,
3894 pd);
3895 return r;
3896}
3897
3898
3899static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
3900 unsigned int count, struct kvm_vcpu *vcpu)
3901{
7972995b 3902 if (vcpu->arch.pio.count)
cf8f70bf
GN		 3903 goto data_avail;
3904
c41a15dd 3905 trace_kvm_pio(0, port, size, 1);
cf8f70bf
GN		 3906
3907 vcpu->arch.pio.port = port;
3908 vcpu->arch.pio.in = 1;
7972995b 3909 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3910 vcpu->arch.pio.size = size;
3911
3912 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
3913 data_avail:
3914 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3915 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3916 return 1;
3917 }
3918
3919 vcpu->run->exit_reason = KVM_EXIT_IO;
3920 vcpu->run->io.direction = KVM_EXIT_IO_IN;
3921 vcpu->run->io.size = size;
3922 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3923 vcpu->run->io.count = count;
3924 vcpu->run->io.port = port;
3925
3926 return 0;
3927}
3928
3929static int emulator_pio_out_emulated(int size, unsigned short port,
3930 const void *val, unsigned int count,
3931 struct kvm_vcpu *vcpu)
3932{
c41a15dd 3933 trace_kvm_pio(1, port, size, 1);
cf8f70bf
GN		 3934
3935 vcpu->arch.pio.port = port;
3936 vcpu->arch.pio.in = 0;
7972995b 3937 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3938 vcpu->arch.pio.size = size;
3939
3940 memcpy(vcpu->arch.pio_data, val, size * count);
3941
3942 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3943 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3944 return 1;
3945 }
3946
3947 vcpu->run->exit_reason = KVM_EXIT_IO;
3948 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
3949 vcpu->run->io.size = size;
3950 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3951 vcpu->run->io.count = count;
3952 vcpu->run->io.port = port;
3953
3954 return 0;
3955}
3956
bbd9b64e
CO		 3957static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3958{
3959 return kvm_x86_ops->get_segment_base(vcpu, seg);
3960}
3961
3962int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3963{
a7052897 3964 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3965 return X86EMUL_CONTINUE;
3966}
3967
f5f48ee1
SY		 3968int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3969{
3970 if (!need_emulate_wbinvd(vcpu))
3971 return X86EMUL_CONTINUE;
3972
3973 if (kvm_x86_ops->has_wbinvd_exit()) {
3974 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3975 wbinvd_ipi, NULL, 1);
3976 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
3977 }
3978 wbinvd();
3979 return X86EMUL_CONTINUE;
3980}
3981EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3982
bbd9b64e
CO		 3983int emulate_clts(struct kvm_vcpu *vcpu)
3984{
4d4ec087 3985 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3986 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3987 return X86EMUL_CONTINUE;
3988}
3989
35aa5375 3990int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 3991{
338dbc97 3992 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 3993}
3994
35aa5375 3995int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 3996{
338dbc97
GN		 3997
3998 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 3999}
4000
52a46617 4001static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4002{
52a46617 4003 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4004}
4005
52a46617 4006static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4007{
52a46617
GN		 4008 unsigned long value;
4009
4010 switch (cr) {
4011 case 0:
4012 value = kvm_read_cr0(vcpu);
4013 break;
4014 case 2:
4015 value = vcpu->arch.cr2;
4016 break;
4017 case 3:
4018 value = vcpu->arch.cr3;
4019 break;
4020 case 4:
4021 value = kvm_read_cr4(vcpu);
4022 break;
4023 case 8:
4024 value = kvm_get_cr8(vcpu);
4025 break;
4026 default:
4027 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4028 return 0;
4029 }
4030
4031 return value;
4032}
4033
0f12244f 4034static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4035{
0f12244f
GN		 4036 int res = 0;
4037
52a46617
GN		 4038 switch (cr) {
4039 case 0:
49a9b07e 4040 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4041 break;
4042 case 2:
4043 vcpu->arch.cr2 = val;
4044 break;
4045 case 3:
2390218b 4046 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4047 break;
4048 case 4:
a83b29c6 4049 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4050 break;
4051 case 8:
0f12244f 4052 res = __kvm_set_cr8(vcpu, val & 0xfUL);
52a46617
GN		 4053 break;
4054 default:
4055 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4056 res = -1;
52a46617 4057 }
0f12244f
GN		 4058
4059 return res;
52a46617
GN		 4060}
4061
9c537244
GN		 4062static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4063{
4064 return kvm_x86_ops->get_cpl(vcpu);
4065}
4066
2dafc6c2
GN		 4067static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4068{
4069 kvm_x86_ops->get_gdt(vcpu, dt);
4070}
4071
160ce1f1
MG		 4072static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4073{
4074 kvm_x86_ops->get_idt(vcpu, dt);
4075}
4076
5951c442
GN		 4077static unsigned long emulator_get_cached_segment_base(int seg,
4078 struct kvm_vcpu *vcpu)
4079{
4080 return get_segment_base(vcpu, seg);
4081}
4082
2dafc6c2
GN		 4083static bool emulator_get_cached_descriptor(struct desc_struct *desc, int seg,
4084 struct kvm_vcpu *vcpu)
4085{
4086 struct kvm_segment var;
4087
4088 kvm_get_segment(vcpu, &var, seg);
4089
4090 if (var.unusable)
4091 return false;
4092
4093 if (var.g)
4094 var.limit >>= 12;
4095 set_desc_limit(desc, var.limit);
4096 set_desc_base(desc, (unsigned long)var.base);
4097 desc->type = var.type;
4098 desc->s = var.s;
4099 desc->dpl = var.dpl;
4100 desc->p = var.present;
4101 desc->avl = var.avl;
4102 desc->l = var.l;
4103 desc->d = var.db;
4104 desc->g = var.g;
4105
4106 return true;
4107}
4108
4109static void emulator_set_cached_descriptor(struct desc_struct *desc, int seg,
4110 struct kvm_vcpu *vcpu)
4111{
4112 struct kvm_segment var;
4113
4114 /* needed to preserve selector */
4115 kvm_get_segment(vcpu, &var, seg);
4116
4117 var.base = get_desc_base(desc);
4118 var.limit = get_desc_limit(desc);
4119 if (desc->g)
4120 var.limit = (var.limit << 12) | 0xfff;
4121 var.type = desc->type;
4122 var.present = desc->p;
4123 var.dpl = desc->dpl;
4124 var.db = desc->d;
4125 var.s = desc->s;
4126 var.l = desc->l;
4127 var.g = desc->g;
4128 var.avl = desc->avl;
4129 var.present = desc->p;
4130 var.unusable = !var.present;
4131 var.padding = 0;
4132
4133 kvm_set_segment(vcpu, &var, seg);
4134 return;
4135}
4136
4137static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4138{
4139 struct kvm_segment kvm_seg;
4140
4141 kvm_get_segment(vcpu, &kvm_seg, seg);
4142 return kvm_seg.selector;
4143}
4144
4145static void emulator_set_segment_selector(u16 sel, int seg,
4146 struct kvm_vcpu *vcpu)
4147{
4148 struct kvm_segment kvm_seg;
4149
4150 kvm_get_segment(vcpu, &kvm_seg, seg);
4151 kvm_seg.selector = sel;
4152 kvm_set_segment(vcpu, &kvm_seg, seg);
4153}
4154
14af3f3c 4155static struct x86_emulate_ops emulate_ops = {
1871c602 4156 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4157 .write_std = kvm_write_guest_virt_system,
1871c602 4158 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4159 .read_emulated = emulator_read_emulated,
4160 .write_emulated = emulator_write_emulated,
4161 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4162 .pio_in_emulated = emulator_pio_in_emulated,
4163 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4164 .get_cached_descriptor = emulator_get_cached_descriptor,
4165 .set_cached_descriptor = emulator_set_cached_descriptor,
4166 .get_segment_selector = emulator_get_segment_selector,
4167 .set_segment_selector = emulator_set_segment_selector,
5951c442 4168 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4169 .get_gdt = emulator_get_gdt,
160ce1f1 4170 .get_idt = emulator_get_idt,
52a46617
GN		 4171 .get_cr = emulator_get_cr,
4172 .set_cr = emulator_set_cr,
9c537244 4173 .cpl = emulator_get_cpl,
35aa5375
GN		 4174 .get_dr = emulator_get_dr,
4175 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4176 .set_msr = kvm_set_msr,
4177 .get_msr = kvm_get_msr,
bbd9b64e
CO		 4178};
4179
5fdbf976
MT		 4180static void cache_all_regs(struct kvm_vcpu *vcpu)
4181{
4182 kvm_register_read(vcpu, VCPU_REGS_RAX);
4183 kvm_register_read(vcpu, VCPU_REGS_RSP);
4184 kvm_register_read(vcpu, VCPU_REGS_RIP);
4185 vcpu->arch.regs_dirty = ~0;
4186}
4187
95cb2295
GN		 4188static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4189{
4190 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4191 /*
4192 * an sti; sti; sequence only disable interrupts for the first
4193 * instruction. So, if the last instruction, be it emulated or
4194 * not, left the system with the INT_STI flag enabled, it
4195 * means that the last instruction is an sti. We should not
4196 * leave the flag on in this case. The same goes for mov ss
4197 */
4198 if (!(int_shadow & mask))
4199 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4200}
4201
54b8486f
GN		 4202static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4203{
4204 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4205 if (ctxt->exception == PF_VECTOR)
d4f8cf66 4206 kvm_propagate_fault(vcpu);
54b8486f
GN		 4207 else if (ctxt->error_code_valid)
4208 kvm_queue_exception_e(vcpu, ctxt->exception, ctxt->error_code);
4209 else
4210 kvm_queue_exception(vcpu, ctxt->exception);
4211}
4212
8ec4722d
MG		 4213static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4214{
4215 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4216 int cs_db, cs_l;
4217
4218 cache_all_regs(vcpu);
4219
4220 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4221
4222 vcpu->arch.emulate_ctxt.vcpu = vcpu;
4223 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
4224 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4225 vcpu->arch.emulate_ctxt.mode =
4226 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4227 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4228 ? X86EMUL_MODE_VM86 : cs_l
4229 ? X86EMUL_MODE_PROT64 : cs_db
4230 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
4231 memset(c, 0, sizeof(struct decode_cache));
4232 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4233}
4234
63995653
MG		 4235int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4236{
4237 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4238 int ret;
4239
4240 init_emulate_ctxt(vcpu);
4241
4242 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4243 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4244 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4245 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4246
4247 if (ret != X86EMUL_CONTINUE)
4248 return EMULATE_FAIL;
4249
4250 vcpu->arch.emulate_ctxt.eip = c->eip;
4251 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4252 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4253 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4254
4255 if (irq == NMI_VECTOR)
4256 vcpu->arch.nmi_pending = false;
4257 else
4258 vcpu->arch.interrupt.pending = false;
4259
4260 return EMULATE_DONE;
4261}
4262EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4263
6d77dbfc
GN		 4264static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4265{
6d77dbfc
GN		 4266 ++vcpu->stat.insn_emulation_fail;
4267 trace_kvm_emulate_insn_failed(vcpu);
4268 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4269 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4270 vcpu->run->internal.ndata = 0;
4271 kvm_queue_exception(vcpu, UD_VECTOR);
4272 return EMULATE_FAIL;
4273}
4274
a6f177ef
GN		 4275static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4276{
4277 gpa_t gpa;
4278
68be0803
GN		 4279 if (tdp_enabled)
4280 return false;
4281
a6f177ef
GN		 4282 /*
4283 * if emulation was due to access to shadowed page table
4284 * and it failed try to unshadow page and re-entetr the
4285 * guest to let CPU execute the instruction.
4286 */
4287 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4288 return true;
4289
4290 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4291
4292 if (gpa == UNMAPPED_GVA)
4293 return true; /* let cpu generate fault */
4294
4295 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4296 return true;
4297
4298 return false;
4299}
4300
bbd9b64e 4301int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 4302 unsigned long cr2,
4303 u16 error_code,
571008da 4304 int emulation_type)
bbd9b64e 4305{
95cb2295 4306 int r;
4d2179e1 4307 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4308
26eef70c 4309 kvm_clear_exception_queue(vcpu);
ad312c7c 4310 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4311 /*
56e82318 4312 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4313 * instead of direct ->regs accesses, can save hundred cycles
4314 * on Intel for instructions that don't read/change RSP, for
4315 * for example.
4316 */
4317 cache_all_regs(vcpu);
bbd9b64e 4318
571008da 4319 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4320 init_emulate_ctxt(vcpu);
95cb2295 4321 vcpu->arch.emulate_ctxt.interruptibility = 0;
54b8486f 4322 vcpu->arch.emulate_ctxt.exception = -1;
4fc40f07 4323 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4324
9aabc88f 4325 r = x86_decode_insn(&vcpu->arch.emulate_ctxt);
d47f00a6
JR		 4326 if (r == X86EMUL_PROPAGATE_FAULT)
4327 goto done;
4328
e46479f8 4329 trace_kvm_emulate_insn_start(vcpu);
571008da 4330
0cb5762e
AP		 4331 /* Only allow emulation of specific instructions on #UD
4332 * (namely VMMCALL, sysenter, sysexit, syscall)*/
0cb5762e
AP		 4333 if (emulation_type & EMULTYPE_TRAP_UD) {
4334 if (!c->twobyte)
4335 return EMULATE_FAIL;
4336 switch (c->b) {
4337 case 0x01: /* VMMCALL */
4338 if (c->modrm_mod != 3 || c->modrm_rm != 1)
4339 return EMULATE_FAIL;
4340 break;
4341 case 0x34: /* sysenter */
4342 case 0x35: /* sysexit */
4343 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4344 return EMULATE_FAIL;
4345 break;
4346 case 0x05: /* syscall */
4347 if (c->modrm_mod != 0 || c->modrm_rm != 0)
4348 return EMULATE_FAIL;
4349 break;
4350 default:
4351 return EMULATE_FAIL;
4352 }
4353
4354 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
4355 return EMULATE_FAIL;
4356 }
571008da 4357
f2b5756b 4358 ++vcpu->stat.insn_emulation;
bbd9b64e 4359 if (r) {
a6f177ef 4360 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4361 return EMULATE_DONE;
6d77dbfc
GN		 4362 if (emulation_type & EMULTYPE_SKIP)
4363 return EMULATE_FAIL;
4364 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4365 }
4366 }
4367
ba8afb6b
GN		 4368 if (emulation_type & EMULTYPE_SKIP) {
4369 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4370 return EMULATE_DONE;
4371 }
4372
4d2179e1
GN		 4373 /* this is needed for vmware backdor interface to work since it
4374 changes registers values during IO operation */
4375 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4376
5cd21917 4377restart:
9aabc88f 4378 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4379
d2ddd1c4 4380 if (r == EMULATION_FAILED) {
a6f177ef 4381 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4382 return EMULATE_DONE;
4383
6d77dbfc 4384 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4385 }
4386
d47f00a6 4387done:
d2ddd1c4 4388 if (vcpu->arch.emulate_ctxt.exception >= 0) {
54b8486f 4389 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4390 r = EMULATE_DONE;
4391 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4392 if (!vcpu->arch.pio.in)
4393 vcpu->arch.pio.count = 0;
e85d28f8
GN		 4394 r = EMULATE_DO_MMIO;
4395 } else if (vcpu->mmio_needed) {
3457e419
GN		 4396 if (vcpu->mmio_is_write)
4397 vcpu->mmio_needed = 0;
e85d28f8 4398 r = EMULATE_DO_MMIO;
d2ddd1c4 4399 } else if (r == EMULATION_RESTART)
5cd21917 4400 goto restart;
d2ddd1c4
GN		 4401 else
4402 r = EMULATE_DONE;
f850e2e6 4403
e85d28f8
GN		 4404 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
4405 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4406 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4407 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4408 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4409
4410 return r;
de7d789a 4411}
bbd9b64e 4412EXPORT_SYMBOL_GPL(emulate_instruction);
de7d789a 4413
cf8f70bf 4414int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4415{
cf8f70bf
GN		 4416 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4417 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4418 /* do not return to emulator after return from userspace */
7972995b 4419 vcpu->arch.pio.count = 0;
de7d789a
CO		 4420 return ret;
4421}
cf8f70bf 4422EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4423
8cfdc000
ZA		 4424static void tsc_bad(void *info)
4425{
4426 __get_cpu_var(cpu_tsc_khz) = 0;
4427}
4428
4429static void tsc_khz_changed(void *data)
c8076604 4430{
8cfdc000
ZA		 4431 struct cpufreq_freqs *freq = data;
4432 unsigned long khz = 0;
4433
4434 if (data)
4435 khz = freq->new;
4436 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4437 khz = cpufreq_quick_get(raw_smp_processor_id());
4438 if (!khz)
4439 khz = tsc_khz;
4440 __get_cpu_var(cpu_tsc_khz) = khz;
c8076604
GH		 4441}
4442
c8076604
GH		 4443static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4444 void *data)
4445{
4446 struct cpufreq_freqs *freq = data;
4447 struct kvm *kvm;
4448 struct kvm_vcpu *vcpu;
4449 int i, send_ipi = 0;
4450
8cfdc000
ZA		 4451 /*
4452 * We allow guests to temporarily run on slowing clocks,
4453 * provided we notify them after, or to run on accelerating
4454 * clocks, provided we notify them before. Thus time never
4455 * goes backwards.
4456 *
4457 * However, we have a problem. We can't atomically update
4458 * the frequency of a given CPU from this function; it is
4459 * merely a notifier, which can be called from any CPU.
4460 * Changing the TSC frequency at arbitrary points in time
4461 * requires a recomputation of local variables related to
4462 * the TSC for each VCPU. We must flag these local variables
4463 * to be updated and be sure the update takes place with the
4464 * new frequency before any guests proceed.
4465 *
4466 * Unfortunately, the combination of hotplug CPU and frequency
4467 * change creates an intractable locking scenario; the order
4468 * of when these callouts happen is undefined with respect to
4469 * CPU hotplug, and they can race with each other. As such,
4470 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4471 * undefined; you can actually have a CPU frequency change take
4472 * place in between the computation of X and the setting of the
4473 * variable. To protect against this problem, all updates of
4474 * the per_cpu tsc_khz variable are done in an interrupt
4475 * protected IPI, and all callers wishing to update the value
4476 * must wait for a synchronous IPI to complete (which is trivial
4477 * if the caller is on the CPU already). This establishes the
4478 * necessary total order on variable updates.
4479 *
4480 * Note that because a guest time update may take place
4481 * anytime after the setting of the VCPU's request bit, the
4482 * correct TSC value must be set before the request. However,
4483 * to ensure the update actually makes it to any guest which
4484 * starts running in hardware virtualization between the set
4485 * and the acquisition of the spinlock, we must also ping the
4486 * CPU after setting the request bit.
4487 *
4488 */
4489
c8076604
GH		 4490 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4491 return 0;
4492 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4493 return 0;
8cfdc000
ZA		 4494
4495 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4496
4497 spin_lock(&kvm_lock);
4498 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4499 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4500 if (vcpu->cpu != freq->cpu)
4501 continue;
c285545f 4502 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4503 if (vcpu->cpu != smp_processor_id())
8cfdc000 4504 send_ipi = 1;
c8076604
GH		 4505 }
4506 }
4507 spin_unlock(&kvm_lock);
4508
4509 if (freq->old < freq->new && send_ipi) {
4510 /*
4511 * We upscale the frequency. Must make the guest
4512 * doesn't see old kvmclock values while running with
4513 * the new frequency, otherwise we risk the guest sees
4514 * time go backwards.
4515 *
4516 * In case we update the frequency for another cpu
4517 * (which might be in guest context) send an interrupt
4518 * to kick the cpu out of guest context. Next time
4519 * guest context is entered kvmclock will be updated,
4520 * so the guest will not see stale values.
4521 */
8cfdc000 4522 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4523 }
4524 return 0;
4525}
4526
4527static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4528 .notifier_call = kvmclock_cpufreq_notifier
4529};
4530
4531static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4532 unsigned long action, void *hcpu)
4533{
4534 unsigned int cpu = (unsigned long)hcpu;
4535
4536 switch (action) {
4537 case CPU_ONLINE:
4538 case CPU_DOWN_FAILED:
4539 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4540 break;
4541 case CPU_DOWN_PREPARE:
4542 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4543 break;
4544 }
4545 return NOTIFY_OK;
4546}
4547
4548static struct notifier_block kvmclock_cpu_notifier_block = {
4549 .notifier_call = kvmclock_cpu_notifier,
4550 .priority = -INT_MAX
c8076604
GH		 4551};
4552
b820cc0c
ZA		 4553static void kvm_timer_init(void)
4554{
4555 int cpu;
4556
c285545f 4557 max_tsc_khz = tsc_khz;
8cfdc000 4558 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4559 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4560#ifdef CONFIG_CPU_FREQ
4561 struct cpufreq_policy policy;
4562 memset(&policy, 0, sizeof(policy));
4563 cpufreq_get_policy(&policy, get_cpu());
4564 if (policy.cpuinfo.max_freq)
4565 max_tsc_khz = policy.cpuinfo.max_freq;
4566#endif
b820cc0c
ZA		 4567 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4568 CPUFREQ_TRANSITION_NOTIFIER);
4569 }
c285545f 4570 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4571 for_each_online_cpu(cpu)
4572 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4573}
4574
ff9d07a0
ZY		 4575static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4576
4577static int kvm_is_in_guest(void)
4578{
4579 return percpu_read(current_vcpu) != NULL;
4580}
4581
4582static int kvm_is_user_mode(void)
4583{
4584 int user_mode = 3;
dcf46b94 4585
ff9d07a0
ZY		 4586 if (percpu_read(current_vcpu))
4587 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4588
ff9d07a0
ZY		 4589 return user_mode != 0;
4590}
4591
4592static unsigned long kvm_get_guest_ip(void)
4593{
4594 unsigned long ip = 0;
dcf46b94 4595
ff9d07a0
ZY		 4596 if (percpu_read(current_vcpu))
4597 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4598
ff9d07a0
ZY		 4599 return ip;
4600}
4601
4602static struct perf_guest_info_callbacks kvm_guest_cbs = {
4603 .is_in_guest = kvm_is_in_guest,
4604 .is_user_mode = kvm_is_user_mode,
4605 .get_guest_ip = kvm_get_guest_ip,
4606};
4607
4608void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4609{
4610 percpu_write(current_vcpu, vcpu);
4611}
4612EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4613
4614void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4615{
4616 percpu_write(current_vcpu, NULL);
4617}
4618EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4619
f8c16bba 4620int kvm_arch_init(void *opaque)
043405e1 4621{
b820cc0c 4622 int r;
f8c16bba
ZX		 4623 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4624
f8c16bba
ZX		 4625 if (kvm_x86_ops) {
4626 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4627 r = -EEXIST;
4628 goto out;
f8c16bba
ZX		 4629 }
4630
4631 if (!ops->cpu_has_kvm_support()) {
4632 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4633 r = -EOPNOTSUPP;
4634 goto out;
f8c16bba
ZX		 4635 }
4636 if (ops->disabled_by_bios()) {
4637 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4638 r = -EOPNOTSUPP;
4639 goto out;
f8c16bba
ZX		 4640 }
4641
97db56ce
AK		 4642 r = kvm_mmu_module_init();
4643 if (r)
4644 goto out;
4645
4646 kvm_init_msr_list();
4647
f8c16bba 4648 kvm_x86_ops = ops;
56c6d28a 4649 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 4650 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
4651 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4652 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4653
b820cc0c 4654 kvm_timer_init();
c8076604 4655
ff9d07a0
ZY		 4656 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4657
2acf923e
DC		 4658 if (cpu_has_xsave)
4659 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4660
f8c16bba 4661 return 0;
56c6d28a
ZX		 4662
4663out:
56c6d28a 4664 return r;
043405e1 4665}
8776e519 4666
f8c16bba
ZX		 4667void kvm_arch_exit(void)
4668{
ff9d07a0
ZY		 4669 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4670
888d256e
JK		 4671 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4672 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4673 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4674 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4675 kvm_x86_ops = NULL;
56c6d28a
ZX		 4676 kvm_mmu_module_exit();
4677}
f8c16bba 4678
8776e519
HB		 4679int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4680{
4681 ++vcpu->stat.halt_exits;
4682 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4683 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4684 return 1;
4685 } else {
4686 vcpu->run->exit_reason = KVM_EXIT_HLT;
4687 return 0;
4688 }
4689}
4690EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4691
2f333bcb
MT		 4692static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4693 unsigned long a1)
4694{
4695 if (is_long_mode(vcpu))
4696 return a0;
4697 else
4698 return a0 | ((gpa_t)a1 << 32);
4699}
4700
55cd8e5a
GN		 4701int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4702{
4703 u64 param, ingpa, outgpa, ret;
4704 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4705 bool fast, longmode;
4706 int cs_db, cs_l;
4707
4708 /*
4709 * hypercall generates UD from non zero cpl and real mode
4710 * per HYPER-V spec
4711 */
3eeb3288 4712 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4713 kvm_queue_exception(vcpu, UD_VECTOR);
4714 return 0;
4715 }
4716
4717 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4718 longmode = is_long_mode(vcpu) && cs_l == 1;
4719
4720 if (!longmode) {
ccd46936
GN		 4721 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4722 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4723 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4724 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4725 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4726 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4727 }
4728#ifdef CONFIG_X86_64
4729 else {
4730 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4731 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4732 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4733 }
4734#endif
4735
4736 code = param & 0xffff;
4737 fast = (param >> 16) & 0x1;
4738 rep_cnt = (param >> 32) & 0xfff;
4739 rep_idx = (param >> 48) & 0xfff;
4740
4741 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4742
c25bc163
GN		 4743 switch (code) {
4744 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4745 kvm_vcpu_on_spin(vcpu);
4746 break;
4747 default:
4748 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4749 break;
4750 }
55cd8e5a
GN		 4751
4752 ret = res | (((u64)rep_done & 0xfff) << 32);
4753 if (longmode) {
4754 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4755 } else {
4756 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4757 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4758 }
4759
4760 return 1;
4761}
4762
8776e519
HB		 4763int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4764{
4765 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4766 int r = 1;
8776e519 4767
55cd8e5a
GN		 4768 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4769 return kvm_hv_hypercall(vcpu);
4770
5fdbf976
MT		 4771 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4772 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4773 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4774 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4775 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4776
229456fc 4777 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4778
8776e519
HB		 4779 if (!is_long_mode(vcpu)) {
4780 nr &= 0xFFFFFFFF;
4781 a0 &= 0xFFFFFFFF;
4782 a1 &= 0xFFFFFFFF;
4783 a2 &= 0xFFFFFFFF;
4784 a3 &= 0xFFFFFFFF;
4785 }
4786
07708c4a
JK		 4787 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4788 ret = -KVM_EPERM;
4789 goto out;
4790 }
4791
8776e519 4792 switch (nr) {
b93463aa
AK		 4793 case KVM_HC_VAPIC_POLL_IRQ:
4794 ret = 0;
4795 break;
2f333bcb
MT		 4796 case KVM_HC_MMU_OP:
4797 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4798 break;
8776e519
HB		 4799 default:
4800 ret = -KVM_ENOSYS;
4801 break;
4802 }
07708c4a 4803out:
5fdbf976 4804 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4805 ++vcpu->stat.hypercalls;
2f333bcb 4806 return r;
8776e519
HB		 4807}
4808EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4809
4810int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4811{
4812 char instruction[3];
5fdbf976 4813 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4814
8776e519
HB		 4815 /*
4816 * Blow out the MMU to ensure that no other VCPU has an active mapping
4817 * to ensure that the updated hypercall appears atomically across all
4818 * VCPUs.
4819 */
4820 kvm_mmu_zap_all(vcpu->kvm);
4821
8776e519 4822 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4823
8fe681e9 4824 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4825}
4826
8776e519
HB		 4827void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4828{
89a27f4d 4829 struct desc_ptr dt = { limit, base };
8776e519
HB		 4830
4831 kvm_x86_ops->set_gdt(vcpu, &dt);
4832}
4833
4834void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4835{
89a27f4d 4836 struct desc_ptr dt = { limit, base };
8776e519
HB		 4837
4838 kvm_x86_ops->set_idt(vcpu, &dt);
4839}
4840
07716717
DK		 4841static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4842{
ad312c7c
ZX		 4843 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4844 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4845
4846 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4847 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4848 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4849 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4850 if (ej->function == e->function) {
4851 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4852 return j;
4853 }
4854 }
4855 return 0; /* silence gcc, even though control never reaches here */
4856}
4857
4858/* find an entry with matching function, matching index (if needed), and that
4859 * should be read next (if it's stateful) */
4860static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4861 u32 function, u32 index)
4862{
4863 if (e->function != function)
4864 return 0;
4865 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4866 return 0;
4867 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4868 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4869 return 0;
4870 return 1;
4871}
4872
d8017474
AG		 4873struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4874 u32 function, u32 index)
8776e519
HB		 4875{
4876 int i;
d8017474 4877 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4878
ad312c7c 4879 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4880 struct kvm_cpuid_entry2 *e;
4881
ad312c7c 4882 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4883 if (is_matching_cpuid_entry(e, function, index)) {
4884 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4885 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4886 best = e;
4887 break;
4888 }
4889 /*
4890 * Both basic or both extended?
4891 */
4892 if (((e->function ^ function) & 0x80000000) == 0)
4893 if (!best || e->function > best->function)
4894 best = e;
4895 }
d8017474
AG		 4896 return best;
4897}
0e851880 4898EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4899
82725b20
DE		 4900int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4901{
4902 struct kvm_cpuid_entry2 *best;
4903
f7a71197
AK		 4904 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
4905 if (!best || best->eax < 0x80000008)
4906 goto not_found;
82725b20
DE		 4907 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4908 if (best)
4909 return best->eax & 0xff;
f7a71197 4910not_found:
82725b20
DE		 4911 return 36;
4912}
4913
d8017474
AG		 4914void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4915{
4916 u32 function, index;
4917 struct kvm_cpuid_entry2 *best;
4918
4919 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4920 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4921 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4922 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4923 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4924 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4925 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4926 if (best) {
5fdbf976
MT		 4927 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4928 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4929 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4930 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4931 }
8776e519 4932 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4933 trace_kvm_cpuid(function,
4934 kvm_register_read(vcpu, VCPU_REGS_RAX),
4935 kvm_register_read(vcpu, VCPU_REGS_RBX),
4936 kvm_register_read(vcpu, VCPU_REGS_RCX),
4937 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4938}
4939EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4940
b6c7a5dc
HB		 4941/*
4942 * Check if userspace requested an interrupt window, and that the
4943 * interrupt window is open.
4944 *
4945 * No need to exit to userspace if we already have an interrupt queued.
4946 */
851ba692 4947static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4948{
8061823a 4949 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4950 vcpu->run->request_interrupt_window &&
5df56646 4951 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4952}
4953
851ba692 4954static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4955{
851ba692
AK		 4956 struct kvm_run *kvm_run = vcpu->run;
4957
91586a3b 4958 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4959 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4960 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4961 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4962 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4963 else
b6c7a5dc 4964 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4965 kvm_arch_interrupt_allowed(vcpu) &&
4966 !kvm_cpu_has_interrupt(vcpu) &&
4967 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4968}
4969
b93463aa
AK		 4970static void vapic_enter(struct kvm_vcpu *vcpu)
4971{
4972 struct kvm_lapic *apic = vcpu->arch.apic;
4973 struct page *page;
4974
4975 if (!apic || !apic->vapic_addr)
4976 return;
4977
4978 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4979
4980 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4981}
4982
4983static void vapic_exit(struct kvm_vcpu *vcpu)
4984{
4985 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4986 int idx;
b93463aa
AK		 4987
4988 if (!apic || !apic->vapic_addr)
4989 return;
4990
f656ce01 4991 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4992 kvm_release_page_dirty(apic->vapic_page);
4993 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4994 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4995}
4996
95ba8273
GN		 4997static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4998{
4999 int max_irr, tpr;
5000
5001 if (!kvm_x86_ops->update_cr8_intercept)
5002 return;
5003
88c808fd
AK		 5004 if (!vcpu->arch.apic)
5005 return;
5006
8db3baa2
GN		 5007 if (!vcpu->arch.apic->vapic_addr)
5008 max_irr = kvm_lapic_find_highest_irr(vcpu);
5009 else
5010 max_irr = -1;
95ba8273
GN		 5011
5012 if (max_irr != -1)
5013 max_irr >>= 4;
5014
5015 tpr = kvm_lapic_get_cr8(vcpu);
5016
5017 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5018}
5019
851ba692 5020static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5021{
5022 /* try to reinject previous events if any */
b59bb7bd 5023 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5024 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5025 vcpu->arch.exception.has_error_code,
5026 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5027 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5028 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5029 vcpu->arch.exception.error_code,
5030 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5031 return;
5032 }
5033
95ba8273
GN		 5034 if (vcpu->arch.nmi_injected) {
5035 kvm_x86_ops->set_nmi(vcpu);
5036 return;
5037 }
5038
5039 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5040 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5041 return;
5042 }
5043
5044 /* try to inject new event if pending */
5045 if (vcpu->arch.nmi_pending) {
5046 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5047 vcpu->arch.nmi_pending = false;
5048 vcpu->arch.nmi_injected = true;
5049 kvm_x86_ops->set_nmi(vcpu);
5050 }
5051 } else if (kvm_cpu_has_interrupt(vcpu)) {
5052 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5053 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5054 false);
5055 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5056 }
5057 }
5058}
5059
2acf923e
DC		 5060static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5061{
5062 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5063 !vcpu->guest_xcr0_loaded) {
5064 /* kvm_set_xcr() also depends on this */
5065 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5066 vcpu->guest_xcr0_loaded = 1;
5067 }
5068}
5069
5070static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5071{
5072 if (vcpu->guest_xcr0_loaded) {
5073 if (vcpu->arch.xcr0 != host_xcr0)
5074 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5075 vcpu->guest_xcr0_loaded = 0;
5076 }
5077}
5078
851ba692 5079static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5080{
5081 int r;
6a8b1d13 5082 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5083 vcpu->run->request_interrupt_window;
b6c7a5dc 5084
3e007509 5085 if (vcpu->requests) {
a8eeb04a 5086 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5087 kvm_mmu_unload(vcpu);
a8eeb04a 5088 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5089 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5090 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5091 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5092 if (unlikely(r))
5093 goto out;
5094 }
a8eeb04a 5095 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5096 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5097 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5098 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5099 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5100 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5101 r = 0;
5102 goto out;
5103 }
a8eeb04a 5104 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5105 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5106 r = 0;
5107 goto out;
5108 }
a8eeb04a 5109 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5110 vcpu->fpu_active = 0;
5111 kvm_x86_ops->fpu_deactivate(vcpu);
5112 }
2f52d58c 5113 }
b93463aa 5114
3e007509
AK		 5115 r = kvm_mmu_reload(vcpu);
5116 if (unlikely(r))
5117 goto out;
5118
b463a6f7
AK		 5119 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5120 inject_pending_event(vcpu);
5121
5122 /* enable NMI/IRQ window open exits if needed */
5123 if (vcpu->arch.nmi_pending)
5124 kvm_x86_ops->enable_nmi_window(vcpu);
5125 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5126 kvm_x86_ops->enable_irq_window(vcpu);
5127
5128 if (kvm_lapic_enabled(vcpu)) {
5129 update_cr8_intercept(vcpu);
5130 kvm_lapic_sync_to_vapic(vcpu);
5131 }
5132 }
5133
b6c7a5dc
HB		 5134 preempt_disable();
5135
5136 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5137 if (vcpu->fpu_active)
5138 kvm_load_guest_fpu(vcpu);
2acf923e 5139 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5140
d94e1dc9
AK		 5141 atomic_set(&vcpu->guest_mode, 1);
5142 smp_wmb();
b6c7a5dc 5143
d94e1dc9 5144 local_irq_disable();
32f88400 5145
d94e1dc9
AK		 5146 if (!atomic_read(&vcpu->guest_mode) || vcpu->requests
5147 || need_resched() || signal_pending(current)) {
5148 atomic_set(&vcpu->guest_mode, 0);
5149 smp_wmb();
6c142801
AK		 5150 local_irq_enable();
5151 preempt_enable();
b463a6f7 5152 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5153 r = 1;
5154 goto out;
5155 }
5156
f656ce01 5157 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5158
b6c7a5dc
HB		 5159 kvm_guest_enter();
5160
42dbaa5a 5161 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5162 set_debugreg(0, 7);
5163 set_debugreg(vcpu->arch.eff_db[0], 0);
5164 set_debugreg(vcpu->arch.eff_db[1], 1);
5165 set_debugreg(vcpu->arch.eff_db[2], 2);
5166 set_debugreg(vcpu->arch.eff_db[3], 3);
5167 }
b6c7a5dc 5168
229456fc 5169 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5170 kvm_x86_ops->run(vcpu);
b6c7a5dc 5171
24f1e32c
FW		 5172 /*
5173 * If the guest has used debug registers, at least dr7
5174 * will be disabled while returning to the host.
5175 * If we don't have active breakpoints in the host, we don't
5176 * care about the messed up debug address registers. But if
5177 * we have some of them active, restore the old state.
5178 */
59d8eb53 5179 if (hw_breakpoint_active())
24f1e32c 5180 hw_breakpoint_restore();
42dbaa5a 5181
1d5f066e
ZA		 5182 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5183
d94e1dc9
AK		 5184 atomic_set(&vcpu->guest_mode, 0);
5185 smp_wmb();
b6c7a5dc
HB		 5186 local_irq_enable();
5187
5188 ++vcpu->stat.exits;
5189
5190 /*
5191 * We must have an instruction between local_irq_enable() and
5192 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5193 * the interrupt shadow. The stat.exits increment will do nicely.
5194 * But we need to prevent reordering, hence this barrier():
5195 */
5196 barrier();
5197
5198 kvm_guest_exit();
5199
5200 preempt_enable();
5201
f656ce01 5202 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5203
b6c7a5dc
HB		 5204 /*
5205 * Profile KVM exit RIPs:
5206 */
5207 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5208 unsigned long rip = kvm_rip_read(vcpu);
5209 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5210 }
5211
298101da 5212
b93463aa
AK		 5213 kvm_lapic_sync_from_vapic(vcpu);
5214
851ba692 5215 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5216out:
5217 return r;
5218}
b6c7a5dc 5219
09cec754 5220
851ba692 5221static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5222{
5223 int r;
f656ce01 5224 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5225
5226 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5227 pr_debug("vcpu %d received sipi with vector # %x\n",
5228 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5229 kvm_lapic_reset(vcpu);
5f179287 5230 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5231 if (r)
5232 return r;
5233 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5234 }
5235
f656ce01 5236 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5237 vapic_enter(vcpu);
5238
5239 r = 1;
5240 while (r > 0) {
af2152f5 5241 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 5242 r = vcpu_enter_guest(vcpu);
d7690175 5243 else {
f656ce01 5244 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5245 kvm_vcpu_block(vcpu);
f656ce01 5246 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5247 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5248 {
5249 switch(vcpu->arch.mp_state) {
5250 case KVM_MP_STATE_HALTED:
d7690175 5251 vcpu->arch.mp_state =
09cec754
GN		 5252 KVM_MP_STATE_RUNNABLE;
5253 case KVM_MP_STATE_RUNNABLE:
5254 break;
5255 case KVM_MP_STATE_SIPI_RECEIVED:
5256 default:
5257 r = -EINTR;
5258 break;
5259 }
5260 }
d7690175
MT		 5261 }
5262
09cec754
GN		 5263 if (r <= 0)
5264 break;
5265
5266 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5267 if (kvm_cpu_has_pending_timer(vcpu))
5268 kvm_inject_pending_timer_irqs(vcpu);
5269
851ba692 5270 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5271 r = -EINTR;
851ba692 5272 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5273 ++vcpu->stat.request_irq_exits;
5274 }
5275 if (signal_pending(current)) {
5276 r = -EINTR;
851ba692 5277 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5278 ++vcpu->stat.signal_exits;
5279 }
5280 if (need_resched()) {
f656ce01 5281 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5282 kvm_resched(vcpu);
f656ce01 5283 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5284 }
b6c7a5dc
HB		 5285 }
5286
f656ce01 5287 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5288
b93463aa
AK		 5289 vapic_exit(vcpu);
5290
b6c7a5dc
HB		 5291 return r;
5292}
5293
5294int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5295{
5296 int r;
5297 sigset_t sigsaved;
5298
ac9f6dc0
AK		 5299 if (vcpu->sigset_active)
5300 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5301
a4535290 5302 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5303 kvm_vcpu_block(vcpu);
d7690175 5304 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5305 r = -EAGAIN;
5306 goto out;
b6c7a5dc
HB		 5307 }
5308
b6c7a5dc
HB		 5309 /* re-sync apic's tpr */
5310 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 5311 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 5312
d2ddd1c4 5313 if (vcpu->arch.pio.count || vcpu->mmio_needed) {
92bf9748
GN		 5314 if (vcpu->mmio_needed) {
5315 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
5316 vcpu->mmio_read_completed = 1;
5317 vcpu->mmio_needed = 0;
b6c7a5dc 5318 }
f656ce01 5319 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5cd21917 5320 r = emulate_instruction(vcpu, 0, 0, EMULTYPE_NO_DECODE);
f656ce01 5321 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6d77dbfc 5322 if (r != EMULATE_DONE) {
b6c7a5dc
HB		 5323 r = 0;
5324 goto out;
5325 }
5326 }
5fdbf976
MT		 5327 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5328 kvm_register_write(vcpu, VCPU_REGS_RAX,
5329 kvm_run->hypercall.ret);
b6c7a5dc 5330
851ba692 5331 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5332
5333out:
f1d86e46 5334 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5335 if (vcpu->sigset_active)
5336 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5337
b6c7a5dc
HB		 5338 return r;
5339}
5340
5341int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5342{
5fdbf976
MT		 5343 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5344 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5345 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5346 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5347 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5348 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5349 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5350 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5351#ifdef CONFIG_X86_64
5fdbf976
MT		 5352 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5353 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5354 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5355 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5356 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5357 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5358 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5359 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5360#endif
5361
5fdbf976 5362 regs->rip = kvm_rip_read(vcpu);
91586a3b 5363 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5364
b6c7a5dc
HB		 5365 return 0;
5366}
5367
5368int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5369{
5fdbf976
MT		 5370 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5371 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5372 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5373 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5374 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5375 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5376 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5377 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5378#ifdef CONFIG_X86_64
5fdbf976
MT		 5379 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5380 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5381 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5382 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5383 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5384 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5385 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5386 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5387#endif
5388
5fdbf976 5389 kvm_rip_write(vcpu, regs->rip);
91586a3b 5390 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5391
b4f14abd
JK		 5392 vcpu->arch.exception.pending = false;
5393
3842d135
AK		 5394 kvm_make_request(KVM_REQ_EVENT, vcpu);
5395
b6c7a5dc
HB		 5396 return 0;
5397}
5398
b6c7a5dc
HB		 5399void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5400{
5401 struct kvm_segment cs;
5402
3e6e0aab 5403 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5404 *db = cs.db;
5405 *l = cs.l;
5406}
5407EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5408
5409int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5410 struct kvm_sregs *sregs)
5411{
89a27f4d 5412 struct desc_ptr dt;
b6c7a5dc 5413
3e6e0aab
GT		 5414 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5415 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5416 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5417 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5418 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5419 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5420
3e6e0aab
GT		 5421 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5422 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5423
5424 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5425 sregs->idt.limit = dt.size;
5426 sregs->idt.base = dt.address;
b6c7a5dc 5427 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5428 sregs->gdt.limit = dt.size;
5429 sregs->gdt.base = dt.address;
b6c7a5dc 5430
4d4ec087 5431 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 5432 sregs->cr2 = vcpu->arch.cr2;
5433 sregs->cr3 = vcpu->arch.cr3;
fc78f519 5434 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5435 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5436 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5437 sregs->apic_base = kvm_get_apic_base(vcpu);
5438
923c61bb 5439 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5440
36752c9b 5441 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5442 set_bit(vcpu->arch.interrupt.nr,
5443 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5444
b6c7a5dc
HB		 5445 return 0;
5446}
5447
62d9f0db
MT		 5448int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5449 struct kvm_mp_state *mp_state)
5450{
62d9f0db 5451 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5452 return 0;
5453}
5454
5455int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5456 struct kvm_mp_state *mp_state)
5457{
62d9f0db 5458 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5459 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5460 return 0;
5461}
5462
e269fb21
JK		 5463int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5464 bool has_error_code, u32 error_code)
b6c7a5dc 5465{
4d2179e1 5466 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5467 int ret;
e01c2426 5468
8ec4722d 5469 init_emulate_ctxt(vcpu);
c697518a 5470
9aabc88f 5471 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5472 tss_selector, reason, has_error_code,
5473 error_code);
c697518a 5474
c697518a 5475 if (ret)
19d04437 5476 return EMULATE_FAIL;
37817f29 5477
4d2179e1 5478 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5479 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
19d04437 5480 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5481 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5482 return EMULATE_DONE;
37817f29
IE		 5483}
5484EXPORT_SYMBOL_GPL(kvm_task_switch);
5485
b6c7a5dc
HB		 5486int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5487 struct kvm_sregs *sregs)
5488{
5489 int mmu_reset_needed = 0;
923c61bb 5490 int pending_vec, max_bits;
89a27f4d 5491 struct desc_ptr dt;
b6c7a5dc 5492
89a27f4d
GN		 5493 dt.size = sregs->idt.limit;
5494 dt.address = sregs->idt.base;
b6c7a5dc 5495 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5496 dt.size = sregs->gdt.limit;
5497 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5498 kvm_x86_ops->set_gdt(vcpu, &dt);
5499
ad312c7c
ZX		 5500 vcpu->arch.cr2 = sregs->cr2;
5501 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5502 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5503
2d3ad1f4 5504 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5505
f6801dff 5506 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5507 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5508 kvm_set_apic_base(vcpu, sregs->apic_base);
5509
4d4ec087 5510 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5511 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5512 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5513
fc78f519 5514 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5515 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5516 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ff03a073 5517 load_pdptrs(vcpu, vcpu->arch.walk_mmu, vcpu->arch.cr3);
7c93be44
MT		 5518 mmu_reset_needed = 1;
5519 }
b6c7a5dc
HB		 5520
5521 if (mmu_reset_needed)
5522 kvm_mmu_reset_context(vcpu);
5523
923c61bb
GN		 5524 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5525 pending_vec = find_first_bit(
5526 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5527 if (pending_vec < max_bits) {
66fd3f7f 5528 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5529 pr_debug("Set back pending irq %d\n", pending_vec);
5530 if (irqchip_in_kernel(vcpu->kvm))
5531 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5532 }
5533
3e6e0aab
GT		 5534 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5535 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5536 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5537 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5538 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5539 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5540
3e6e0aab
GT		 5541 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5542 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5543
5f0269f5
ME		 5544 update_cr8_intercept(vcpu);
5545
9c3e4aab 5546 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5547 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5548 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5549 !is_protmode(vcpu))
9c3e4aab
MT		 5550 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5551
3842d135
AK		 5552 kvm_make_request(KVM_REQ_EVENT, vcpu);
5553
b6c7a5dc
HB		 5554 return 0;
5555}
5556
d0bfb940
JK		 5557int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5558 struct kvm_guest_debug *dbg)
b6c7a5dc 5559{
355be0b9 5560 unsigned long rflags;
ae675ef0 5561 int i, r;
b6c7a5dc 5562
4f926bf2
JK		 5563 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5564 r = -EBUSY;
5565 if (vcpu->arch.exception.pending)
2122ff5e 5566 goto out;
4f926bf2
JK		 5567 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5568 kvm_queue_exception(vcpu, DB_VECTOR);
5569 else
5570 kvm_queue_exception(vcpu, BP_VECTOR);
5571 }
5572
91586a3b
JK		 5573 /*
5574 * Read rflags as long as potentially injected trace flags are still
5575 * filtered out.
5576 */
5577 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5578
5579 vcpu->guest_debug = dbg->control;
5580 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5581 vcpu->guest_debug = 0;
5582
5583 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5584 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5585 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5586 vcpu->arch.switch_db_regs =
5587 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5588 } else {
5589 for (i = 0; i < KVM_NR_DB_REGS; i++)
5590 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5591 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5592 }
5593
f92653ee
JK		 5594 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5595 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5596 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5597
91586a3b
JK		 5598 /*
5599 * Trigger an rflags update that will inject or remove the trace
5600 * flags.
5601 */
5602 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5603
355be0b9 5604 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5605
4f926bf2 5606 r = 0;
d0bfb940 5607
2122ff5e 5608out:
b6c7a5dc
HB		 5609
5610 return r;
5611}
5612
8b006791
ZX		 5613/*
5614 * Translate a guest virtual address to a guest physical address.
5615 */
5616int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5617 struct kvm_translation *tr)
5618{
5619 unsigned long vaddr = tr->linear_address;
5620 gpa_t gpa;
f656ce01 5621 int idx;
8b006791 5622
f656ce01 5623 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5624 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5625 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5626 tr->physical_address = gpa;
5627 tr->valid = gpa != UNMAPPED_GVA;
5628 tr->writeable = 1;
5629 tr->usermode = 0;
8b006791
ZX		 5630
5631 return 0;
5632}
5633
d0752060
HB		 5634int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5635{
98918833
SY		 5636 struct i387_fxsave_struct *fxsave =
5637 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5638
d0752060
HB		 5639 memcpy(fpu->fpr, fxsave->st_space, 128);
5640 fpu->fcw = fxsave->cwd;
5641 fpu->fsw = fxsave->swd;
5642 fpu->ftwx = fxsave->twd;
5643 fpu->last_opcode = fxsave->fop;
5644 fpu->last_ip = fxsave->rip;
5645 fpu->last_dp = fxsave->rdp;
5646 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5647
d0752060
HB		 5648 return 0;
5649}
5650
5651int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5652{
98918833
SY		 5653 struct i387_fxsave_struct *fxsave =
5654 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5655
d0752060
HB		 5656 memcpy(fxsave->st_space, fpu->fpr, 128);
5657 fxsave->cwd = fpu->fcw;
5658 fxsave->swd = fpu->fsw;
5659 fxsave->twd = fpu->ftwx;
5660 fxsave->fop = fpu->last_opcode;
5661 fxsave->rip = fpu->last_ip;
5662 fxsave->rdp = fpu->last_dp;
5663 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5664
d0752060
HB		 5665 return 0;
5666}
5667
10ab25cd 5668int fx_init(struct kvm_vcpu *vcpu)
d0752060 5669{
10ab25cd
JK		 5670 int err;
5671
5672 err = fpu_alloc(&vcpu->arch.guest_fpu);
5673 if (err)
5674 return err;
5675
98918833 5676 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5677
2acf923e
DC		 5678 /*
5679 * Ensure guest xcr0 is valid for loading
5680 */
5681 vcpu->arch.xcr0 = XSTATE_FP;
5682
ad312c7c 5683 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5684
5685 return 0;
d0752060
HB		 5686}
5687EXPORT_SYMBOL_GPL(fx_init);
5688
98918833
SY		 5689static void fx_free(struct kvm_vcpu *vcpu)
5690{
5691 fpu_free(&vcpu->arch.guest_fpu);
5692}
5693
d0752060
HB		 5694void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5695{
2608d7a1 5696 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5697 return;
5698
2acf923e
DC		 5699 /*
5700 * Restore all possible states in the guest,
5701 * and assume host would use all available bits.
5702 * Guest xcr0 would be loaded later.
5703 */
5704 kvm_put_guest_xcr0(vcpu);
d0752060 5705 vcpu->guest_fpu_loaded = 1;
7cf30855 5706 unlazy_fpu(current);
98918833 5707 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5708 trace_kvm_fpu(1);
d0752060 5709}
d0752060
HB		 5710
5711void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5712{
2acf923e
DC		 5713 kvm_put_guest_xcr0(vcpu);
5714
d0752060
HB		 5715 if (!vcpu->guest_fpu_loaded)
5716 return;
5717
5718 vcpu->guest_fpu_loaded = 0;
98918833 5719 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5720 ++vcpu->stat.fpu_reload;
a8eeb04a 5721 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5722 trace_kvm_fpu(0);
d0752060 5723}
e9b11c17
ZX		 5724
5725void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5726{
7f1ea208
JR		 5727 if (vcpu->arch.time_page) {
5728 kvm_release_page_dirty(vcpu->arch.time_page);
5729 vcpu->arch.time_page = NULL;
5730 }
5731
f5f48ee1 5732 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5733 fx_free(vcpu);
e9b11c17
ZX		 5734 kvm_x86_ops->vcpu_free(vcpu);
5735}
5736
5737struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5738 unsigned int id)
5739{
6755bae8
ZA		 5740 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5741 printk_once(KERN_WARNING
5742 "kvm: SMP vm created on host with unstable TSC; "
5743 "guest TSC will not be reliable\n");
26e5215f
AK		 5744 return kvm_x86_ops->vcpu_create(kvm, id);
5745}
e9b11c17 5746
26e5215f
AK		 5747int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5748{
5749 int r;
e9b11c17 5750
0bed3b56 5751 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5752 vcpu_load(vcpu);
5753 r = kvm_arch_vcpu_reset(vcpu);
5754 if (r == 0)
5755 r = kvm_mmu_setup(vcpu);
5756 vcpu_put(vcpu);
5757 if (r < 0)
5758 goto free_vcpu;
5759
26e5215f 5760 return 0;
e9b11c17
ZX		 5761free_vcpu:
5762 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5763 return r;
e9b11c17
ZX		 5764}
5765
d40ccc62 5766void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5767{
5768 vcpu_load(vcpu);
5769 kvm_mmu_unload(vcpu);
5770 vcpu_put(vcpu);
5771
98918833 5772 fx_free(vcpu);
e9b11c17
ZX		 5773 kvm_x86_ops->vcpu_free(vcpu);
5774}
5775
5776int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5777{
448fa4a9
JK		 5778 vcpu->arch.nmi_pending = false;
5779 vcpu->arch.nmi_injected = false;
5780
42dbaa5a
JK		 5781 vcpu->arch.switch_db_regs = 0;
5782 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5783 vcpu->arch.dr6 = DR6_FIXED_1;
5784 vcpu->arch.dr7 = DR7_FIXED_1;
5785
3842d135
AK		 5786 kvm_make_request(KVM_REQ_EVENT, vcpu);
5787
e9b11c17
ZX		 5788 return kvm_x86_ops->vcpu_reset(vcpu);
5789}
5790
10474ae8 5791int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5792{
ca84d1a2
ZA		 5793 struct kvm *kvm;
5794 struct kvm_vcpu *vcpu;
5795 int i;
5796
18863bdd 5797 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5798 list_for_each_entry(kvm, &vm_list, vm_list)
5799 kvm_for_each_vcpu(i, vcpu, kvm)
5800 if (vcpu->cpu == smp_processor_id())
c285545f 5801 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5802 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5803}
5804
5805void kvm_arch_hardware_disable(void *garbage)
5806{
5807 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5808 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5809}
5810
5811int kvm_arch_hardware_setup(void)
5812{
5813 return kvm_x86_ops->hardware_setup();
5814}
5815
5816void kvm_arch_hardware_unsetup(void)
5817{
5818 kvm_x86_ops->hardware_unsetup();
5819}
5820
5821void kvm_arch_check_processor_compat(void *rtn)
5822{
5823 kvm_x86_ops->check_processor_compatibility(rtn);
5824}
5825
5826int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5827{
5828 struct page *page;
5829 struct kvm *kvm;
5830 int r;
5831
5832 BUG_ON(vcpu->kvm == NULL);
5833 kvm = vcpu->kvm;
5834
9aabc88f 5835 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 5836 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 5837 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 5838 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 5839 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 5840 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5841 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5842 else
a4535290 5843 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5844
5845 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5846 if (!page) {
5847 r = -ENOMEM;
5848 goto fail;
5849 }
ad312c7c 5850 vcpu->arch.pio_data = page_address(page);
e9b11c17 5851
c285545f
ZA		 5852 if (!kvm->arch.virtual_tsc_khz)
5853 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
5854
e9b11c17
ZX		 5855 r = kvm_mmu_create(vcpu);
5856 if (r < 0)
5857 goto fail_free_pio_data;
5858
5859 if (irqchip_in_kernel(kvm)) {
5860 r = kvm_create_lapic(vcpu);
5861 if (r < 0)
5862 goto fail_mmu_destroy;
5863 }
5864
890ca9ae
HY		 5865 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5866 GFP_KERNEL);
5867 if (!vcpu->arch.mce_banks) {
5868 r = -ENOMEM;
443c39bc 5869 goto fail_free_lapic;
890ca9ae
HY		 5870 }
5871 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5872
f5f48ee1
SY		 5873 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
5874 goto fail_free_mce_banks;
5875
e9b11c17 5876 return 0;
f5f48ee1
SY		 5877fail_free_mce_banks:
5878 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 5879fail_free_lapic:
5880 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5881fail_mmu_destroy:
5882 kvm_mmu_destroy(vcpu);
5883fail_free_pio_data:
ad312c7c 5884 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5885fail:
5886 return r;
5887}
5888
5889void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5890{
f656ce01
MT		 5891 int idx;
5892
36cb93fd 5893 kfree(vcpu->arch.mce_banks);
e9b11c17 5894 kvm_free_lapic(vcpu);
f656ce01 5895 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5896 kvm_mmu_destroy(vcpu);
f656ce01 5897 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5898 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5899}
d19a9cd2
ZX		 5900
5901struct kvm *kvm_arch_create_vm(void)
5902{
5903 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5904
5905 if (!kvm)
5906 return ERR_PTR(-ENOMEM);
5907
f05e70ac 5908 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5909 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5910
5550af4d
SY		 5911 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5912 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5913
99e3e30a
ZA		 5914 spin_lock_init(&kvm->arch.tsc_write_lock);
5915
d19a9cd2
ZX		 5916 return kvm;
5917}
5918
5919static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5920{
5921 vcpu_load(vcpu);
5922 kvm_mmu_unload(vcpu);
5923 vcpu_put(vcpu);
5924}
5925
5926static void kvm_free_vcpus(struct kvm *kvm)
5927{
5928 unsigned int i;
988a2cae 5929 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5930
5931 /*
5932 * Unpin any mmu pages first.
5933 */
988a2cae
GN		 5934 kvm_for_each_vcpu(i, vcpu, kvm)
5935 kvm_unload_vcpu_mmu(vcpu);
5936 kvm_for_each_vcpu(i, vcpu, kvm)
5937 kvm_arch_vcpu_free(vcpu);
5938
5939 mutex_lock(&kvm->lock);
5940 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5941 kvm->vcpus[i] = NULL;
d19a9cd2 5942
988a2cae
GN		 5943 atomic_set(&kvm->online_vcpus, 0);
5944 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5945}
5946
ad8ba2cd
SY		 5947void kvm_arch_sync_events(struct kvm *kvm)
5948{
ba4cef31 5949 kvm_free_all_assigned_devices(kvm);
aea924f6 5950 kvm_free_pit(kvm);
ad8ba2cd
SY		 5951}
5952
d19a9cd2
ZX		 5953void kvm_arch_destroy_vm(struct kvm *kvm)
5954{
6eb55818 5955 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 5956 kfree(kvm->arch.vpic);
5957 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5958 kvm_free_vcpus(kvm);
5959 kvm_free_physmem(kvm);
3d45830c
AK		 5960 if (kvm->arch.apic_access_page)
5961 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5962 if (kvm->arch.ept_identity_pagetable)
5963 put_page(kvm->arch.ept_identity_pagetable);
64749204 5964 cleanup_srcu_struct(&kvm->srcu);
d19a9cd2
ZX		 5965 kfree(kvm);
5966}
0de10343 5967
f7784b8e
MT		 5968int kvm_arch_prepare_memory_region(struct kvm *kvm,
5969 struct kvm_memory_slot *memslot,
0de10343 5970 struct kvm_memory_slot old,
f7784b8e 5971 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5972 int user_alloc)
5973{
f7784b8e 5974 int npages = memslot->npages;
7ac77099
AK		 5975 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
5976
5977 /* Prevent internal slot pages from being moved by fork()/COW. */
5978 if (memslot->id >= KVM_MEMORY_SLOTS)
5979 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 5980
5981 /*To keep backward compatibility with older userspace,
5982 *x86 needs to hanlde !user_alloc case.
5983 */
5984 if (!user_alloc) {
5985 if (npages && !old.rmap) {
604b38ac
AA		 5986 unsigned long userspace_addr;
5987
72dc67a6 5988 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5989 userspace_addr = do_mmap(NULL, 0,
5990 npages * PAGE_SIZE,
5991 PROT_READ | PROT_WRITE,
7ac77099 5992 map_flags,
604b38ac 5993 0);
72dc67a6 5994 up_write(&current->mm->mmap_sem);
0de10343 5995
604b38ac
AA		 5996 if (IS_ERR((void *)userspace_addr))
5997 return PTR_ERR((void *)userspace_addr);
5998
604b38ac 5999 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6000 }
6001 }
6002
f7784b8e
MT		 6003
6004 return 0;
6005}
6006
6007void kvm_arch_commit_memory_region(struct kvm *kvm,
6008 struct kvm_userspace_memory_region *mem,
6009 struct kvm_memory_slot old,
6010 int user_alloc)
6011{
6012
6013 int npages = mem->memory_size >> PAGE_SHIFT;
6014
6015 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6016 int ret;
6017
6018 down_write(&current->mm->mmap_sem);
6019 ret = do_munmap(current->mm, old.userspace_addr,
6020 old.npages * PAGE_SIZE);
6021 up_write(&current->mm->mmap_sem);
6022 if (ret < 0)
6023 printk(KERN_WARNING
6024 "kvm_vm_ioctl_set_memory_region: "
6025 "failed to munmap memory\n");
6026 }
6027
7c8a83b7 6028 spin_lock(&kvm->mmu_lock);
f05e70ac 6029 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 6030 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6031 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
6032 }
6033
6034 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6035 spin_unlock(&kvm->mmu_lock);
0de10343 6036}
1d737c8a 6037
34d4cb8f
MT		 6038void kvm_arch_flush_shadow(struct kvm *kvm)
6039{
6040 kvm_mmu_zap_all(kvm);
8986ecc0 6041 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6042}
6043
1d737c8a
ZX		 6044int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6045{
a4535290 6046 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 6047 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6048 || vcpu->arch.nmi_pending ||
6049 (kvm_arch_interrupt_allowed(vcpu) &&
6050 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6051}
5736199a 6052
5736199a
ZX		 6053void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6054{
32f88400
MT		 6055 int me;
6056 int cpu = vcpu->cpu;
5736199a
ZX		 6057
6058 if (waitqueue_active(&vcpu->wq)) {
6059 wake_up_interruptible(&vcpu->wq);
6060 ++vcpu->stat.halt_wakeup;
6061 }
32f88400
MT		 6062
6063 me = get_cpu();
6064 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
d94e1dc9 6065 if (atomic_xchg(&vcpu->guest_mode, 0))
32f88400 6066 smp_send_reschedule(cpu);
e9571ed5 6067 put_cpu();
5736199a 6068}
78646121
GN		 6069
6070int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6071{
6072 return kvm_x86_ops->interrupt_allowed(vcpu);
6073}
229456fc 6074
f92653ee
JK		 6075bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6076{
6077 unsigned long current_rip = kvm_rip_read(vcpu) +
6078 get_segment_base(vcpu, VCPU_SREG_CS);
6079
6080 return current_rip == linear_rip;
6081}
6082EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6083
94fe45da
JK		 6084unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6085{
6086 unsigned long rflags;
6087
6088 rflags = kvm_x86_ops->get_rflags(vcpu);
6089 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6090 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6091 return rflags;
6092}
6093EXPORT_SYMBOL_GPL(kvm_get_rflags);
6094
6095void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6096{
6097 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6098 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6099 rflags |= X86_EFLAGS_TF;
94fe45da 6100 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6101 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6102}
6103EXPORT_SYMBOL_GPL(kvm_set_rflags);
6104
229456fc
MT		 6105EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6106EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6107EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6108EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6109EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6110EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6111EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6112EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6113EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6114EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6115EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6116EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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