[net-next-2.6.git] / arch / x86 / kernel / cpu / mcheck / k7.c

/*
 * Athlon specific Machine Check Exception Reporting
 * (C) Copyright 2002 Dave Jones <davej@redhat.com>
 */

#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/smp.h>

#include <asm/processor.h>
#include <asm/system.h>
#include <asm/msr.h>

#include "mce.h"

/* Machine Check Handler For AMD Athlon/Duron */
static void k7_machine_check(struct pt_regs *regs, long error_code)
{
	int recover = 1;
	u32 alow, ahigh, high, low;
	u32 mcgstl, mcgsth;
	int i;

	rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
	if (mcgstl & (1<<0))	/* Recoverable ? */
		recover = 0;

	printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
		smp_processor_id(), mcgsth, mcgstl);

	for (i = 1; i < nr_mce_banks; i++) {
		rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
		if (high&(1<<31)) {
			char misc[20];
			char addr[24];
			misc[0] = addr[0] = '\0';
			if (high & (1<<29))
				recover |= 1;
			if (high & (1<<25))
				recover |= 2;
			high &= ~(1<<31);
			if (high & (1<<27)) {
				rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
				snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
			}
			if (high & (1<<26)) {
				rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
				snprintf(addr, 24, " at %08x%08x", ahigh, alow);
			}
			printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
				smp_processor_id(), i, high, low, misc, addr);
			/* Clear it */
			wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
			/* Serialize */
			wmb();
			add_taint(TAINT_MACHINE_CHECK);
		}
	}

	if (recover&2)
		panic("CPU context corrupt");
	if (recover&1)
		panic("Unable to continue");
	printk(KERN_EMERG "Attempting to continue.\n");
	mcgstl &= ~(1<<2);
	wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
}


/* AMD K7 machine check is Intel like */
void amd_mcheck_init(struct cpuinfo_x86 *c)
{
	u32 l, h;
	int i;

	if (!cpu_has(c, X86_FEATURE_MCE))
		return;

	machine_check_vector = k7_machine_check;
	wmb();

	printk(KERN_INFO "Intel machine check architecture supported.\n");
	rdmsr(MSR_IA32_MCG_CAP, l, h);
	if (l & (1<<8))	/* Control register present ? */
		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
	nr_mce_banks = l & 0xff;

	/* Clear status for MC index 0 separately, we don't touch CTL,
	 * as some K7 Athlons cause spurious MCEs when its enabled. */
	if (boot_cpu_data.x86 == 6) {
		wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
		i = 1;
	} else
		i = 0;
	for (; i < nr_mce_banks; i++) {
		wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
		wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
	}

	set_in_cr4(X86_CR4_MCE);
	printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
		smp_processor_id());
}
Commit	Line	Data
1da177e4	1	/*
f4432c5c DJ	2	* Athlon specific Machine Check Exception Reporting
f4432c5c DJ	3	* (C) Copyright 2002 Dave Jones <davej@redhat.com>
1da177e4 LT	4	*/
	5
	6	#include <linux/init.h>
	7	#include <linux/types.h>
	8	#include <linux/kernel.h>
1da177e4 LT	9	#include <linux/interrupt.h>
	10	#include <linux/smp.h>
	11
5175676a	12	#include <asm/processor.h>
1da177e4 LT	13	#include <asm/system.h>
	14	#include <asm/msr.h>
	15
	16	#include "mce.h"
	17
	18	/* Machine Check Handler For AMD Athlon/Duron */
5175676a	19	static void k7_machine_check(struct pt_regs *regs, long error_code)
1da177e4	20	{
5175676a	21	int recover = 1;
1da177e4 LT	22	u32 alow, ahigh, high, low;
	23	u32 mcgstl, mcgsth;
	24	int i;
	25
5175676a	26	rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
1da177e4	27	if (mcgstl & (1<<0)) /* Recoverable ? */
5175676a	28	recover = 0;
1da177e4	29
b912a1c7	30	printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
1da177e4 LT	31	smp_processor_id(), mcgsth, mcgstl);
1da177e4 LT	32
b912a1c7	33	for (i = 1; i < nr_mce_banks; i++) {
72713393	34	rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
1da177e4	35	if (high&(1<<31)) {
9e8b6d90 MZ	36	char misc[20];
	37	char addr[24];
	38	misc[0] = addr[0] = '\0';
1da177e4 LT	39	if (high & (1<<29))
	40	recover \|= 1;
	41	if (high & (1<<25))
	42	recover \|= 2;
1da177e4 LT	43	high &= ~(1<<31);
1da177e4 LT	44	if (high & (1<<27)) {
b912a1c7 AM	45	rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
b912a1c7 AM	46	snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
1da177e4 LT	47	}
1da177e4 LT	48	if (high & (1<<26)) {
b912a1c7 AM	49	rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
b912a1c7 AM	50	snprintf(addr, 24, " at %08x%08x", ahigh, alow);
1da177e4	51	}
b912a1c7	52	printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
9e8b6d90	53	smp_processor_id(), i, high, low, misc, addr);
1da177e4	54	/* Clear it */
b912a1c7	55	wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
1da177e4 LT	56	/* Serialize */
	57	wmb();
	58	add_taint(TAINT_MACHINE_CHECK);
	59	}
	60	}
	61
	62	if (recover&2)
5175676a	63	panic("CPU context corrupt");
1da177e4	64	if (recover&1)
5175676a PC	65	panic("Unable to continue");
5175676a PC	66	printk(KERN_EMERG "Attempting to continue.\n");
1da177e4	67	mcgstl &= ~(1<<2);
5175676a	68	wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
1da177e4 LT	69	}
	70
	71
	72	/* AMD K7 machine check is Intel like */
31ab269a	73	void amd_mcheck_init(struct cpuinfo_x86 *c)
1da177e4 LT	74	{
	75	u32 l, h;
	76	int i;
	77
2f3c30e6 JD	78	if (!cpu_has(c, X86_FEATURE_MCE))
	79	return;
	80
c12ceb76 AK	81	machine_check_vector = k7_machine_check;
	82	wmb();
	83
5175676a PC	84	printk(KERN_INFO "Intel machine check architecture supported.\n");
5175676a PC	85	rdmsr(MSR_IA32_MCG_CAP, l, h);
1da177e4	86	if (l & (1<<8)) /* Control register present ? */
5175676a	87	wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1da177e4 LT	88	nr_mce_banks = l & 0xff;
	89
	90	/* Clear status for MC index 0 separately, we don't touch CTL,
de90c5ce AK	91	* as some K7 Athlons cause spurious MCEs when its enabled. */
de90c5ce AK	92	if (boot_cpu_data.x86 == 6) {
5175676a	93	wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
de90c5ce AK	94	i = 1;
	95	} else
	96	i = 0;
5175676a PC	97	for (; i < nr_mce_banks; i++) {
	98	wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
	99	wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
1da177e4 LT	100	}
1da177e4 LT	101
5175676a PC	102	set_in_cr4(X86_CR4_MCE);
5175676a PC	103	printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
1da177e4 LT	104	smp_processor_id());
1da177e4 LT	105	}