[net-next-2.6.git] / arch / ppc / platforms / 85xx / mpc85xx_ads_common.c

/*
 * arch/ppc/platforms/85xx/mpc85xx_ads_common.c
 *
 * MPC85xx ADS board common routines
 *
 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
 *
 * Copyright 2004 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/reboot.h>
#include <linux/pci.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/seq_file.h>
#include <linux/serial.h>
#include <linux/module.h>

#include <asm/system.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/atomic.h>
#include <asm/time.h>
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/open_pic.h>
#include <asm/bootinfo.h>
#include <asm/pci-bridge.h>
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <asm/immap_85xx.h>
#include <asm/ppc_sys.h>

#include <mm/mmu_decl.h>

#include <syslib/ppc85xx_rio.h>

#include <platforms/85xx/mpc85xx_ads_common.h>

#ifndef CONFIG_PCI
unsigned long isa_io_base = 0;
unsigned long isa_mem_base = 0;
#endif

extern unsigned long total_memory;	/* in mm/init */

unsigned char __res[sizeof (bd_t)];

/* Internal interrupts are all Level Sensitive, and Positive Polarity */
static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
	MPC85XX_INTERNAL_IRQ_SENSES,
	0x0,						/* External  0: */
#if defined(CONFIG_PCI)
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 1: PCI slot 0 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 2: PCI slot 1 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 3: PCI slot 2 */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 4: PCI slot 3 */
#else
	0x0,				/* External  1: */
	0x0,				/* External  2: */
	0x0,				/* External  3: */
	0x0,				/* External  4: */
#endif
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 5: PHY */
	0x0,				/* External  6: */
	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* External 7: PHY */
	0x0,				/* External  8: */
	0x0,				/* External  9: */
	0x0,				/* External 10: */
	0x0,				/* External 11: */
};

/* ************************************************************************ */
int
mpc85xx_ads_show_cpuinfo(struct seq_file *m)
{
	uint pvid, svid, phid1;
	uint memsize = total_memory;
	bd_t *binfo = (bd_t *) __res;
	unsigned int freq;

	/* get the core frequency */
	freq = binfo->bi_intfreq;

	pvid = mfspr(SPRN_PVR);
	svid = mfspr(SPRN_SVR);

	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
	seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	seq_printf(m, "SVR\t\t: 0x%x\n", svid);

	/* Display cpu Pll setting */
	phid1 = mfspr(SPRN_HID1);
	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));

	/* Display the amount of memory */
	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));

	return 0;
}

void __init
mpc85xx_ads_init_IRQ(void)
{
	bd_t *binfo = (bd_t *) __res;
	/* Determine the Physical Address of the OpenPIC regs */
	phys_addr_t OpenPIC_PAddr =
	    binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
	OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
	OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);

	/* Skip reserved space and internal sources */
	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
	/* Map PIC IRQs 0-11 */
	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);

	/* we let openpic interrupts starting from an offset, to
	 * leave space for cascading interrupts underneath.
	 */
	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);

	return;
}

#ifdef CONFIG_PCI
/*
 * interrupt routing
 */

int
mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
	static char pci_irq_table[][4] =
	    /*
	     * This is little evil, but works around the fact
	     * that revA boards have IDSEL starting at 18
	     * and others boards (older) start at 12
	     *
	     *      PCI IDSEL/INTPIN->INTLINE
	     *       A      B      C      D
	     */
	{
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 2 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 5 */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 12 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 15 */
		{0, 0, 0, 0},	/* -- */
		{0, 0, 0, 0},	/* -- */
		{PIRQA, PIRQB, PIRQC, PIRQD},	/* IDSEL 18 */
		{PIRQD, PIRQA, PIRQB, PIRQC},
		{PIRQC, PIRQD, PIRQA, PIRQB},
		{PIRQB, PIRQC, PIRQD, PIRQA},	/* IDSEL 21 */
	};

	const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
	return PCI_IRQ_TABLE_LOOKUP;
}

int
mpc85xx_exclude_device(u_char bus, u_char devfn)
{
	if (bus == 0 && PCI_SLOT(devfn) == 0)
		return PCIBIOS_DEVICE_NOT_FOUND;
	else
		return PCIBIOS_SUCCESSFUL;
}

#endif /* CONFIG_PCI */

#ifdef CONFIG_RAPIDIO
void platform_rio_init(void)
{
	/* 512MB RIO LAW at 0xc0000000 */
	mpc85xx_rio_setup(0xc0000000, 0x20000000);
}
#endif /* CONFIG_RAPIDIO */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* arch/ppc/platforms/85xx/mpc85xx_ads_common.c
	3	*
	4	* MPC85xx ADS board common routines
	5	*
4c8d3d99	6	* Maintainer: Kumar Gala <galak@kernel.crashing.org>
1da177e4 LT	7	*
	8	* Copyright 2004 Freescale Semiconductor Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/config.h>
	17	#include <linux/stddef.h>
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/errno.h>
	21	#include <linux/reboot.h>
	22	#include <linux/pci.h>
	23	#include <linux/kdev_t.h>
	24	#include <linux/major.h>
	25	#include <linux/console.h>
	26	#include <linux/delay.h>
1da177e4 LT	27	#include <linux/seq_file.h>
	28	#include <linux/serial.h>
	29	#include <linux/module.h>
	30
	31	#include <asm/system.h>
	32	#include <asm/pgtable.h>
	33	#include <asm/page.h>
	34	#include <asm/atomic.h>
	35	#include <asm/time.h>
	36	#include <asm/io.h>
	37	#include <asm/machdep.h>
1da177e4 LT	38	#include <asm/open_pic.h>
	39	#include <asm/bootinfo.h>
	40	#include <asm/pci-bridge.h>
	41	#include <asm/mpc85xx.h>
	42	#include <asm/irq.h>
	43	#include <asm/immap_85xx.h>
	44	#include <asm/ppc_sys.h>
	45
	46	#include <mm/mmu_decl.h>
	47
2b0c28d7 MP	48	#include <syslib/ppc85xx_rio.h>
2b0c28d7 MP	49
1da177e4 LT	50	#include <platforms/85xx/mpc85xx_ads_common.h>
	51
	52	#ifndef CONFIG_PCI
	53	unsigned long isa_io_base = 0;
	54	unsigned long isa_mem_base = 0;
	55	#endif
	56
	57	extern unsigned long total_memory; /* in mm/init */
	58
	59	unsigned char __res[sizeof (bd_t)];
	60
	61	/* Internal interrupts are all Level Sensitive, and Positive Polarity */
1da177e4	62	static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
65145e06	63	MPC85XX_INTERNAL_IRQ_SENSES,
1da177e4 LT	64	0x0, /* External 0: */
	65	#if defined(CONFIG_PCI)
	66	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 1: PCI slot 0 */
	67	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 2: PCI slot 1 */
	68	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 3: PCI slot 2 */
	69	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 4: PCI slot 3 */
	70	#else
	71	0x0, /* External 1: */
	72	0x0, /* External 2: */
	73	0x0, /* External 3: */
	74	0x0, /* External 4: */
	75	#endif
	76	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
	77	0x0, /* External 6: */
	78	(IRQ_SENSE_LEVEL \| IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
	79	0x0, /* External 8: */
	80	0x0, /* External 9: */
	81	0x0, /* External 10: */
	82	0x0, /* External 11: */
	83	};
	84
	85	/* ************************************************************************ */
	86	int
	87	mpc85xx_ads_show_cpuinfo(struct seq_file *m)
	88	{
	89	uint pvid, svid, phid1;
	90	uint memsize = total_memory;
	91	bd_t binfo = (bd_t ) __res;
	92	unsigned int freq;
	93
	94	/* get the core frequency */
	95	freq = binfo->bi_intfreq;
	96
	97	pvid = mfspr(SPRN_PVR);
	98	svid = mfspr(SPRN_SVR);
	99
	100	seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
	101	seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
	102	seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
	103	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
	104	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
	105
	106	/* Display cpu Pll setting */
	107	phid1 = mfspr(SPRN_HID1);
	108	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
	109
	110	/* Display the amount of memory */
	111	seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
	112
	113	return 0;
	114	}
	115
	116	void __init
	117	mpc85xx_ads_init_IRQ(void)
	118	{
	119	bd_t binfo = (bd_t ) __res;
	120	/* Determine the Physical Address of the OpenPIC regs */
	121	phys_addr_t OpenPIC_PAddr =
	122	binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
	123	OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
	124	OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
	125	OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
	126
	127	/* Skip reserved space and internal sources */
128	openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
129	/* Map PIC IRQs 0-11 */
65145e06	130	openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
1da177e4 LT	131
	132	/* we let openpic interrupts starting from an offset, to
	133	* leave space for cascading interrupts underneath.
	134	*/
	135	openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
	136
	137	return;
	138	}
	139
	140	#ifdef CONFIG_PCI
	141	/*
	142	* interrupt routing
	143	*/
	144
	145	int
	146	mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
	147	{
	148	static char pci_irq_table[][4] =
	149	/*
	150	* This is little evil, but works around the fact
	151	* that revA boards have IDSEL starting at 18
	152	* and others boards (older) start at 12
	153	*
	154	* PCI IDSEL/INTPIN->INTLINE
	155	* A B C D
	156	*/
	157	{
	158	{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 2 */
	159	{PIRQD, PIRQA, PIRQB, PIRQC},
	160	{PIRQC, PIRQD, PIRQA, PIRQB},
	161	{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 5 */
	162	{0, 0, 0, 0}, /* -- */
	163	{0, 0, 0, 0}, /* -- */
	164	{0, 0, 0, 0}, /* -- */
	165	{0, 0, 0, 0}, /* -- */
	166	{0, 0, 0, 0}, /* -- */
	167	{0, 0, 0, 0}, /* -- */
	168	{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 12 */
	169	{PIRQD, PIRQA, PIRQB, PIRQC},
	170	{PIRQC, PIRQD, PIRQA, PIRQB},
	171	{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 15 */
	172	{0, 0, 0, 0}, /* -- */
	173	{0, 0, 0, 0}, /* -- */
	174	{PIRQA, PIRQB, PIRQC, PIRQD}, /* IDSEL 18 */
	175	{PIRQD, PIRQA, PIRQB, PIRQC},
	176	{PIRQC, PIRQD, PIRQA, PIRQB},
	177	{PIRQB, PIRQC, PIRQD, PIRQA}, /* IDSEL 21 */
	178	};
	179
	180	const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
	181	return PCI_IRQ_TABLE_LOOKUP;
	182	}
	183
	184	int
	185	mpc85xx_exclude_device(u_char bus, u_char devfn)
	186	{
	187	if (bus == 0 && PCI_SLOT(devfn) == 0)
	188	return PCIBIOS_DEVICE_NOT_FOUND;
	189	else
	190	return PCIBIOS_SUCCESSFUL;
	191	}
	192
	193	#endif /* CONFIG_PCI */
2b0c28d7 MP	194
	195	#ifdef CONFIG_RAPIDIO
	196	void platform_rio_init(void)
	197	{
	198	/* 512MB RIO LAW at 0xc0000000 */
	199	mpc85xx_rio_setup(0xc0000000, 0x20000000);
	200	}
	201	#endif /* CONFIG_RAPIDIO */