[net-next-2.6.git] / arch / powerpc / sysdev / fsl_msi.c

/*
 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
 *
 * Author: Tony Li <tony.li@freescale.com>
 *	   Jason Jin <Jason.jin@freescale.com>
 *
 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; version 2 of the
 * License.
 *
 */
#include <linux/irq.h>
#include <linux/bootmem.h>
#include <linux/msi.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
#include <asm/prom.h>
#include <asm/hw_irq.h>
#include <asm/ppc-pci.h>
#include <asm/mpic.h>
#include "fsl_msi.h"

LIST_HEAD(msi_head);

struct fsl_msi_feature {
	u32 fsl_pic_ip;
	u32 msiir_offset;
};

struct fsl_msi_cascade_data {
	struct fsl_msi *msi_data;
	int index;
};

static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
{
	return in_be32(base + (reg >> 2));
}

/*
 * We do not need this actually. The MSIR register has been read once
 * in the cascade interrupt. So, this MSI interrupt has been acked
*/
static void fsl_msi_end_irq(unsigned int virq)
{
}

static struct irq_chip fsl_msi_chip = {
	.mask		= mask_msi_irq,
	.unmask		= unmask_msi_irq,
	.ack		= fsl_msi_end_irq,
	.name		= "FSL-MSI",
};

static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
				irq_hw_number_t hw)
{
	struct fsl_msi *msi_data = h->host_data;
	struct irq_chip *chip = &fsl_msi_chip;

	irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;

	set_irq_chip_data(virq, msi_data);
	set_irq_chip_and_handler(virq, chip, handle_edge_irq);

	return 0;
}

static struct irq_host_ops fsl_msi_host_ops = {
	.map = fsl_msi_host_map,
};

static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
{
	int rc;

	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
			      msi_data->irqhost->of_node);
	if (rc)
		return rc;

	rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
	if (rc < 0) {
		msi_bitmap_free(&msi_data->bitmap);
		return rc;
	}

	return 0;
}

static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
{
	if (type == PCI_CAP_ID_MSIX)
		pr_debug("fslmsi: MSI-X untested, trying anyway.\n");

	return 0;
}

static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
{
	struct msi_desc *entry;
	struct fsl_msi *msi_data;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		if (entry->irq == NO_IRQ)
			continue;
		msi_data = get_irq_data(entry->irq);
		set_irq_msi(entry->irq, NULL);
		msi_bitmap_free_hwirqs(&msi_data->bitmap,
				       virq_to_hw(entry->irq), 1);
		irq_dispose_mapping(entry->irq);
	}

	return;
}

static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
				struct msi_msg *msg,
				struct fsl_msi *fsl_msi_data)
{
	struct fsl_msi *msi_data = fsl_msi_data;
	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
	u32 base = 0;

	pci_bus_read_config_dword(hose->bus,
		PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);

	msg->address_lo = msi_data->msi_addr_lo + base;
	msg->address_hi = msi_data->msi_addr_hi;
	msg->data = hwirq;

	pr_debug("%s: allocated srs: %d, ibs: %d\n",
		__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
}

static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
{
	int rc, hwirq = -ENOMEM;
	unsigned int virq;
	struct msi_desc *entry;
	struct msi_msg msg;
	struct fsl_msi *msi_data;

	list_for_each_entry(entry, &pdev->msi_list, list) {
		list_for_each_entry(msi_data, &msi_head, list) {
			hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
			if (hwirq >= 0)
				break;
		}

		if (hwirq < 0) {
			rc = hwirq;
			pr_debug("%s: fail allocating msi interrupt\n",
					__func__);
			goto out_free;
		}

		virq = irq_create_mapping(msi_data->irqhost, hwirq);

		if (virq == NO_IRQ) {
			pr_debug("%s: fail mapping hwirq 0x%x\n",
					__func__, hwirq);
			msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
			rc = -ENOSPC;
			goto out_free;
		}
		set_irq_data(virq, msi_data);
		set_irq_msi(virq, entry);

		fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
		write_msi_msg(virq, &msg);
	}
	return 0;

out_free:
	/* free by the caller of this function */
	return rc;
}

static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
{
	unsigned int cascade_irq;
	struct fsl_msi *msi_data;
	int msir_index = -1;
	u32 msir_value = 0;
	u32 intr_index;
	u32 have_shift = 0;
	struct fsl_msi_cascade_data *cascade_data;

	cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
	msi_data = cascade_data->msi_data;

	raw_spin_lock(&desc->lock);
	if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
		if (desc->chip->mask_ack)
			desc->chip->mask_ack(irq);
		else {
			desc->chip->mask(irq);
			desc->chip->ack(irq);
		}
	}

	if (unlikely(desc->status & IRQ_INPROGRESS))
		goto unlock;

	msir_index = cascade_data->index;

	if (msir_index >= NR_MSI_REG)
		cascade_irq = NO_IRQ;

	desc->status |= IRQ_INPROGRESS;
	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs,
			msir_index * 0x10);
		break;
	case FSL_PIC_IP_IPIC:
		msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
		break;
	}

	while (msir_value) {
		intr_index = ffs(msir_value) - 1;

		cascade_irq = irq_linear_revmap(msi_data->irqhost,
				msir_index * IRQS_PER_MSI_REG +
					intr_index + have_shift);
		if (cascade_irq != NO_IRQ)
			generic_handle_irq(cascade_irq);
		have_shift += intr_index + 1;
		msir_value = msir_value >> (intr_index + 1);
	}
	desc->status &= ~IRQ_INPROGRESS;

	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	case FSL_PIC_IP_MPIC:
		desc->chip->eoi(irq);
		break;
	case FSL_PIC_IP_IPIC:
		if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
			desc->chip->unmask(irq);
		break;
	}
unlock:
	raw_spin_unlock(&desc->lock);
}

static int fsl_of_msi_remove(struct of_device *ofdev)
{
	struct fsl_msi *msi = ofdev->dev.platform_data;
	int virq, i;
	struct fsl_msi_cascade_data *cascade_data;

	if (msi->list.prev != NULL)
		list_del(&msi->list);
	for (i = 0; i < NR_MSI_REG; i++) {
		virq = msi->msi_virqs[i];
		if (virq != NO_IRQ) {
			cascade_data = get_irq_data(virq);
			kfree(cascade_data);
			irq_dispose_mapping(virq);
		}
	}
	if (msi->bitmap.bitmap)
		msi_bitmap_free(&msi->bitmap);
	iounmap(msi->msi_regs);
	kfree(msi);

	return 0;
}

static int __devinit fsl_of_msi_probe(struct of_device *dev,
				const struct of_device_id *match)
{
	struct fsl_msi *msi;
	struct resource res;
	int err, i, count;
	int rc;
	int virt_msir;
	const u32 *p;
	struct fsl_msi_feature *features = match->data;
	struct fsl_msi_cascade_data *cascade_data = NULL;
	int len;
	u32 offset;

	printk(KERN_DEBUG "Setting up Freescale MSI support\n");

	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	if (!msi) {
		dev_err(&dev->dev, "No memory for MSI structure\n");
		return -ENOMEM;
	}
	dev->dev.platform_data = msi;

	msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
				      NR_MSI_IRQS, &fsl_msi_host_ops, 0);

	if (msi->irqhost == NULL) {
		dev_err(&dev->dev, "No memory for MSI irqhost\n");
		err = -ENOMEM;
		goto error_out;
	}

	/* Get the MSI reg base */
	err = of_address_to_resource(dev->dev.of_node, 0, &res);
	if (err) {
		dev_err(&dev->dev, "%s resource error!\n",
				dev->dev.of_node->full_name);
		goto error_out;
	}

	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	if (!msi->msi_regs) {
		dev_err(&dev->dev, "ioremap problem failed\n");
		goto error_out;
	}

	msi->feature = features->fsl_pic_ip;

	msi->irqhost->host_data = msi;

	msi->msi_addr_hi = 0x0;
	msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);

	rc = fsl_msi_init_allocator(msi);
	if (rc) {
		dev_err(&dev->dev, "Error allocating MSI bitmap\n");
		goto error_out;
	}

	p = of_get_property(dev->dev.of_node, "interrupts", &count);
	if (!p) {
		dev_err(&dev->dev, "no interrupts property found on %s\n",
				dev->dev.of_node->full_name);
		err = -ENODEV;
		goto error_out;
	}
	if (count % 8 != 0) {
		dev_err(&dev->dev, "Malformed interrupts property on %s\n",
				dev->dev.of_node->full_name);
		err = -EINVAL;
		goto error_out;
	}
	offset = 0;
	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
	if (p)
		offset = *p / IRQS_PER_MSI_REG;

	count /= sizeof(u32);
	for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
		virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
		if (virt_msir != NO_IRQ) {
			cascade_data = kzalloc(
					sizeof(struct fsl_msi_cascade_data),
					GFP_KERNEL);
			if (!cascade_data) {
				dev_err(&dev->dev,
					"No memory for MSI cascade data\n");
				err = -ENOMEM;
				goto error_out;
			}
			msi->msi_virqs[i] = virt_msir;
			cascade_data->index = i + offset;
			cascade_data->msi_data = msi;
			set_irq_data(virt_msir, (void *)cascade_data);
			set_irq_chained_handler(virt_msir, fsl_msi_cascade);
		}
	}

	list_add_tail(&msi->list, &msi_head);

	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	if (!ppc_md.setup_msi_irqs) {
		ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
		ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
		ppc_md.msi_check_device = fsl_msi_check_device;
	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
		dev_err(&dev->dev, "Different MSI driver already installed!\n");
		err = -ENODEV;
		goto error_out;
	}
	return 0;
error_out:
	fsl_of_msi_remove(dev);
	return err;
}

static const struct fsl_msi_feature mpic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	.msiir_offset = 0x140,
};

static const struct fsl_msi_feature ipic_msi_feature = {
	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	.msiir_offset = 0x38,
};

static const struct of_device_id fsl_of_msi_ids[] = {
	{
		.compatible = "fsl,mpic-msi",
		.data = (void *)&mpic_msi_feature,
	},
	{
		.compatible = "fsl,ipic-msi",
		.data = (void *)&ipic_msi_feature,
	},
	{}
};

static struct of_platform_driver fsl_of_msi_driver = {
	.driver = {
		.name = "fsl-msi",
		.owner = THIS_MODULE,
		.of_match_table = fsl_of_msi_ids,
	},
	.probe = fsl_of_msi_probe,
	.remove = fsl_of_msi_remove,
};

static __init int fsl_of_msi_init(void)
{
	return of_register_platform_driver(&fsl_of_msi_driver);
}

subsys_initcall(fsl_of_msi_init);
Commit	Line	Data
34e36c15	1	/*
80818813	2	* Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
34e36c15 JJ	3	*
	4	* Author: Tony Li <tony.li@freescale.com>
	5	* Jason Jin <Jason.jin@freescale.com>
	6	*
	7	* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; version 2 of the
	12	* License.
	13	*
	14	*/
	15	#include <linux/irq.h>
	16	#include <linux/bootmem.h>
34e36c15 JJ	17	#include <linux/msi.h>
34e36c15 JJ	18	#include <linux/pci.h>
5a0e3ad6	19	#include <linux/slab.h>
34e36c15 JJ	20	#include <linux/of_platform.h>
	21	#include <sysdev/fsl_soc.h>
	22	#include <asm/prom.h>
	23	#include <asm/hw_irq.h>
	24	#include <asm/ppc-pci.h>
02adac60	25	#include <asm/mpic.h>
34e36c15 JJ	26	#include "fsl_msi.h"
34e36c15 JJ	27
694a7a36 LY	28	LIST_HEAD(msi_head);
694a7a36 LY	29
34e36c15 JJ	30	struct fsl_msi_feature {
	31	u32 fsl_pic_ip;
	32	u32 msiir_offset;
	33	};
	34
02adac60 LY	35	struct fsl_msi_cascade_data {
	36	struct fsl_msi *msi_data;
	37	int index;
	38	};
34e36c15 JJ	39
	40	static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
	41	{
	42	return in_be32(base + (reg >> 2));
	43	}
	44
34e36c15 JJ	45	/*
	46	* We do not need this actually. The MSIR register has been read once
	47	* in the cascade interrupt. So, this MSI interrupt has been acked
	48	*/
	49	static void fsl_msi_end_irq(unsigned int virq)
	50	{
	51	}
	52
	53	static struct irq_chip fsl_msi_chip = {
	54	.mask = mask_msi_irq,
	55	.unmask = unmask_msi_irq,
	56	.ack = fsl_msi_end_irq,
fc380c0c	57	.name = "FSL-MSI",
34e36c15 JJ	58	};
	59
	60	static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
	61	irq_hw_number_t hw)
	62	{
80818813	63	struct fsl_msi *msi_data = h->host_data;
34e36c15 JJ	64	struct irq_chip *chip = &fsl_msi_chip;
34e36c15 JJ	65
6cff46f4	66	irq_to_desc(virq)->status \|= IRQ_TYPE_EDGE_FALLING;
34e36c15	67
80818813	68	set_irq_chip_data(virq, msi_data);
692d1037	69	set_irq_chip_and_handler(virq, chip, handle_edge_irq);
34e36c15 JJ	70
	71	return 0;
	72	}
	73
	74	static struct irq_host_ops fsl_msi_host_ops = {
	75	.map = fsl_msi_host_map,
	76	};
	77
34e36c15 JJ	78	static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
34e36c15 JJ	79	{
692d1037	80	int rc;
34e36c15	81
7e7ab367 ME	82	rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
	83	msi_data->irqhost->of_node);
	84	if (rc)
	85	return rc;
34e36c15	86
7e7ab367 ME	87	rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
	88	if (rc < 0) {
	89	msi_bitmap_free(&msi_data->bitmap);
	90	return rc;
34e36c15 JJ	91	}
34e36c15 JJ	92
34e36c15	93	return 0;
34e36c15 JJ	94	}
	95
	96	static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
	97	{
	98	if (type == PCI_CAP_ID_MSIX)
	99	pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
	100
	101	return 0;
	102	}
	103
	104	static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
	105	{
	106	struct msi_desc *entry;
80818813	107	struct fsl_msi *msi_data;
34e36c15 JJ	108
	109	list_for_each_entry(entry, &pdev->msi_list, list) {
	110	if (entry->irq == NO_IRQ)
	111	continue;
02adac60	112	msi_data = get_irq_data(entry->irq);
34e36c15	113	set_irq_msi(entry->irq, NULL);
7e7ab367 ME	114	msi_bitmap_free_hwirqs(&msi_data->bitmap,
7e7ab367 ME	115	virq_to_hw(entry->irq), 1);
34e36c15 JJ	116	irq_dispose_mapping(entry->irq);
	117	}
	118
	119	return;
	120	}
	121
	122	static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
80818813 LCB	123	struct msi_msg *msg,
80818813 LCB	124	struct fsl_msi *fsl_msi_data)
34e36c15	125	{
80818813	126	struct fsl_msi *msi_data = fsl_msi_data;
3da34aae KG	127	struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3da34aae KG	128	u32 base = 0;
34e36c15	129
3da34aae KG	130	pci_bus_read_config_dword(hose->bus,
	131	PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
	132
	133	msg->address_lo = msi_data->msi_addr_lo + base;
34e36c15 JJ	134	msg->address_hi = msi_data->msi_addr_hi;
	135	msg->data = hwirq;
	136
	137	pr_debug("%s: allocated srs: %d, ibs: %d\n",
	138	__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
	139	}
	140
	141	static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
	142	{
694a7a36	143	int rc, hwirq = -ENOMEM;
34e36c15 JJ	144	unsigned int virq;
	145	struct msi_desc *entry;
	146	struct msi_msg msg;
80818813	147	struct fsl_msi *msi_data;
34e36c15 JJ	148
34e36c15 JJ	149	list_for_each_entry(entry, &pdev->msi_list, list) {
694a7a36 LY	150	list_for_each_entry(msi_data, &msi_head, list) {
	151	hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
	152	if (hwirq >= 0)
	153	break;
	154	}
80818813	155
34e36c15 JJ	156	if (hwirq < 0) {
	157	rc = hwirq;
	158	pr_debug("%s: fail allocating msi interrupt\n",
	159	__func__);
	160	goto out_free;
	161	}
	162
	163	virq = irq_create_mapping(msi_data->irqhost, hwirq);
	164
	165	if (virq == NO_IRQ) {
7e7ab367	166	pr_debug("%s: fail mapping hwirq 0x%x\n",
34e36c15	167	__func__, hwirq);
7e7ab367	168	msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
34e36c15 JJ	169	rc = -ENOSPC;
	170	goto out_free;
	171	}
02adac60	172	set_irq_data(virq, msi_data);
34e36c15 JJ	173	set_irq_msi(virq, entry);
34e36c15 JJ	174
80818813	175	fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
34e36c15 JJ	176	write_msi_msg(virq, &msg);
	177	}
	178	return 0;
	179
	180	out_free:
694a7a36	181	/* free by the caller of this function */
34e36c15 JJ	182	return rc;
	183	}
	184
692d1037	185	static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
34e36c15 JJ	186	{
34e36c15 JJ	187	unsigned int cascade_irq;
02adac60	188	struct fsl_msi *msi_data;
34e36c15 JJ	189	int msir_index = -1;
	190	u32 msir_value = 0;
	191	u32 intr_index;
	192	u32 have_shift = 0;
02adac60 LY	193	struct fsl_msi_cascade_data *cascade_data;
	194
	195	cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
	196	msi_data = cascade_data->msi_data;
34e36c15	197
239007b8	198	raw_spin_lock(&desc->lock);
34e36c15 JJ	199	if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
	200	if (desc->chip->mask_ack)
	201	desc->chip->mask_ack(irq);
	202	else {
	203	desc->chip->mask(irq);
	204	desc->chip->ack(irq);
	205	}
	206	}
	207
	208	if (unlikely(desc->status & IRQ_INPROGRESS))
	209	goto unlock;
	210
02adac60	211	msir_index = cascade_data->index;
34e36c15 JJ	212
	213	if (msir_index >= NR_MSI_REG)
	214	cascade_irq = NO_IRQ;
	215
	216	desc->status \|= IRQ_INPROGRESS;
80818813	217	switch (msi_data->feature & FSL_PIC_IP_MASK) {
34e36c15 JJ	218	case FSL_PIC_IP_MPIC:
	219	msir_value = fsl_msi_read(msi_data->msi_regs,
	220	msir_index * 0x10);
	221	break;
	222	case FSL_PIC_IP_IPIC:
	223	msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
	224	break;
	225	}
	226
	227	while (msir_value) {
	228	intr_index = ffs(msir_value) - 1;
	229
	230	cascade_irq = irq_linear_revmap(msi_data->irqhost,
692d1037 AV	231	msir_index * IRQS_PER_MSI_REG +
692d1037 AV	232	intr_index + have_shift);
34e36c15 JJ	233	if (cascade_irq != NO_IRQ)
34e36c15 JJ	234	generic_handle_irq(cascade_irq);
692d1037 AV	235	have_shift += intr_index + 1;
692d1037 AV	236	msir_value = msir_value >> (intr_index + 1);
34e36c15 JJ	237	}
	238	desc->status &= ~IRQ_INPROGRESS;
	239
	240	switch (msi_data->feature & FSL_PIC_IP_MASK) {
	241	case FSL_PIC_IP_MPIC:
	242	desc->chip->eoi(irq);
	243	break;
	244	case FSL_PIC_IP_IPIC:
	245	if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
	246	desc->chip->unmask(irq);
	247	break;
	248	}
	249	unlock:
239007b8	250	raw_spin_unlock(&desc->lock);
34e36c15 JJ	251	}
34e36c15 JJ	252
48059993 LY	253	static int fsl_of_msi_remove(struct of_device *ofdev)
	254	{
	255	struct fsl_msi *msi = ofdev->dev.platform_data;
	256	int virq, i;
	257	struct fsl_msi_cascade_data *cascade_data;
	258
	259	if (msi->list.prev != NULL)
	260	list_del(&msi->list);
	261	for (i = 0; i < NR_MSI_REG; i++) {
	262	virq = msi->msi_virqs[i];
	263	if (virq != NO_IRQ) {
	264	cascade_data = get_irq_data(virq);
	265	kfree(cascade_data);
	266	irq_dispose_mapping(virq);
	267	}
	268	}
	269	if (msi->bitmap.bitmap)
	270	msi_bitmap_free(&msi->bitmap);
	271	iounmap(msi->msi_regs);
	272	kfree(msi);
	273
	274	return 0;
	275	}
	276
34e36c15 JJ	277	static int __devinit fsl_of_msi_probe(struct of_device *dev,
	278	const struct of_device_id *match)
	279	{
	280	struct fsl_msi *msi;
	281	struct resource res;
	282	int err, i, count;
	283	int rc;
	284	int virt_msir;
	285	const u32 *p;
692d1037	286	struct fsl_msi_feature *features = match->data;
02adac60	287	struct fsl_msi_cascade_data *cascade_data = NULL;
061ca4ad LY	288	int len;
061ca4ad LY	289	u32 offset;
34e36c15 JJ	290
	291	printk(KERN_DEBUG "Setting up Freescale MSI support\n");
	292
	293	msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
	294	if (!msi) {
	295	dev_err(&dev->dev, "No memory for MSI structure\n");
48059993	296	return -ENOMEM;
34e36c15	297	}
48059993	298	dev->dev.platform_data = msi;
34e36c15	299
61c7a080	300	msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
611cd90c	301	NR_MSI_IRQS, &fsl_msi_host_ops, 0);
34e36c15	302
34e36c15 JJ	303	if (msi->irqhost == NULL) {
34e36c15 JJ	304	dev_err(&dev->dev, "No memory for MSI irqhost\n");
34e36c15 JJ	305	err = -ENOMEM;
	306	goto error_out;
	307	}
	308
	309	/* Get the MSI reg base */
61c7a080	310	err = of_address_to_resource(dev->dev.of_node, 0, &res);
34e36c15 JJ	311	if (err) {
34e36c15 JJ	312	dev_err(&dev->dev, "%s resource error!\n",
61c7a080	313	dev->dev.of_node->full_name);
34e36c15 JJ	314	goto error_out;
	315	}
	316
	317	msi->msi_regs = ioremap(res.start, res.end - res.start + 1);
	318	if (!msi->msi_regs) {
	319	dev_err(&dev->dev, "ioremap problem failed\n");
	320	goto error_out;
	321	}
	322
692d1037	323	msi->feature = features->fsl_pic_ip;
34e36c15 JJ	324
	325	msi->irqhost->host_data = msi;
	326
	327	msi->msi_addr_hi = 0x0;
3da34aae	328	msi->msi_addr_lo = features->msiir_offset + (res.start & 0xfffff);
34e36c15 JJ	329
	330	rc = fsl_msi_init_allocator(msi);
	331	if (rc) {
	332	dev_err(&dev->dev, "Error allocating MSI bitmap\n");
	333	goto error_out;
	334	}
	335
61c7a080	336	p = of_get_property(dev->dev.of_node, "interrupts", &count);
34e36c15 JJ	337	if (!p) {
34e36c15 JJ	338	dev_err(&dev->dev, "no interrupts property found on %s\n",
61c7a080	339	dev->dev.of_node->full_name);
34e36c15 JJ	340	err = -ENODEV;
	341	goto error_out;
	342	}
	343	if (count % 8 != 0) {
	344	dev_err(&dev->dev, "Malformed interrupts property on %s\n",
61c7a080	345	dev->dev.of_node->full_name);
34e36c15 JJ	346	err = -EINVAL;
	347	goto error_out;
	348	}
061ca4ad	349	offset = 0;
ee227c57	350	p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
061ca4ad LY	351	if (p)
061ca4ad LY	352	offset = *p / IRQS_PER_MSI_REG;
34e36c15 JJ	353
34e36c15 JJ	354	count /= sizeof(u32);
48059993	355	for (i = 0; i < min(count / 2, NR_MSI_REG); i++) {
61c7a080	356	virt_msir = irq_of_parse_and_map(dev->dev.of_node, i);
34e36c15	357	if (virt_msir != NO_IRQ) {
02adac60 LY	358	cascade_data = kzalloc(
	359	sizeof(struct fsl_msi_cascade_data),
	360	GFP_KERNEL);
	361	if (!cascade_data) {
	362	dev_err(&dev->dev,
	363	"No memory for MSI cascade data\n");
	364	err = -ENOMEM;
	365	goto error_out;
	366	}
48059993	367	msi->msi_virqs[i] = virt_msir;
061ca4ad	368	cascade_data->index = i + offset;
02adac60 LY	369	cascade_data->msi_data = msi;
02adac60 LY	370	set_irq_data(virt_msir, (void *)cascade_data);
34e36c15 JJ	371	set_irq_chained_handler(virt_msir, fsl_msi_cascade);
	372	}
	373	}
	374
694a7a36	375	list_add_tail(&msi->list, &msi_head);
34e36c15	376
80818813 LCB	377	/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
	378	if (!ppc_md.setup_msi_irqs) {
	379	ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
	380	ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
	381	ppc_md.msi_check_device = fsl_msi_check_device;
	382	} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
	383	dev_err(&dev->dev, "Different MSI driver already installed!\n");
	384	err = -ENODEV;
	385	goto error_out;
	386	}
34e36c15 JJ	387	return 0;
34e36c15 JJ	388	error_out:
48059993	389	fsl_of_msi_remove(dev);
34e36c15 JJ	390	return err;
	391	}
	392
	393	static const struct fsl_msi_feature mpic_msi_feature = {
	394	.fsl_pic_ip = FSL_PIC_IP_MPIC,
	395	.msiir_offset = 0x140,
	396	};
	397
	398	static const struct fsl_msi_feature ipic_msi_feature = {
	399	.fsl_pic_ip = FSL_PIC_IP_IPIC,
	400	.msiir_offset = 0x38,
	401	};
	402
	403	static const struct of_device_id fsl_of_msi_ids[] = {
	404	{
	405	.compatible = "fsl,mpic-msi",
	406	.data = (void *)&mpic_msi_feature,
	407	},
	408	{
	409	.compatible = "fsl,ipic-msi",
	410	.data = (void *)&ipic_msi_feature,
	411	},
	412	{}
	413	};
	414
	415	static struct of_platform_driver fsl_of_msi_driver = {
4018294b GL	416	.driver = {
	417	.name = "fsl-msi",
	418	.owner = THIS_MODULE,
	419	.of_match_table = fsl_of_msi_ids,
	420	},
34e36c15	421	.probe = fsl_of_msi_probe,
48059993	422	.remove = fsl_of_msi_remove,
34e36c15 JJ	423	};
	424
	425	static __init int fsl_of_msi_init(void)
	426	{
	427	return of_register_platform_driver(&fsl_of_msi_driver);
	428	}
	429
	430	subsys_initcall(fsl_of_msi_init);