[net-next-2.6.git] / arch / powerpc / kvm / emulate.c

/*
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, version 2, as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 * Copyright IBM Corp. 2007
 *
 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
 */

#include <linux/jiffies.h>
#include <linux/hrtimer.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/kvm_host.h>

#include <asm/reg.h>
#include <asm/time.h>
#include <asm/byteorder.h>
#include <asm/kvm_ppc.h>
#include <asm/disassemble.h>
#include "timing.h"
#include "trace.h"

#define OP_TRAP 3
#define OP_TRAP_64 2

#define OP_31_XOP_LWZX      23
#define OP_31_XOP_LBZX      87
#define OP_31_XOP_STWX      151
#define OP_31_XOP_STBX      215
#define OP_31_XOP_LBZUX     119
#define OP_31_XOP_STBUX     247
#define OP_31_XOP_LHZX      279
#define OP_31_XOP_LHZUX     311
#define OP_31_XOP_MFSPR     339
#define OP_31_XOP_LHAX      343
#define OP_31_XOP_STHX      407
#define OP_31_XOP_STHUX     439
#define OP_31_XOP_MTSPR     467
#define OP_31_XOP_DCBI      470
#define OP_31_XOP_LWBRX     534
#define OP_31_XOP_TLBSYNC   566
#define OP_31_XOP_STWBRX    662
#define OP_31_XOP_LHBRX     790
#define OP_31_XOP_STHBRX    918

#define OP_LWZ  32
#define OP_LWZU 33
#define OP_LBZ  34
#define OP_LBZU 35
#define OP_STW  36
#define OP_STWU 37
#define OP_STB  38
#define OP_STBU 39
#define OP_LHZ  40
#define OP_LHZU 41
#define OP_LHA  42
#define OP_LHAU 43
#define OP_STH  44
#define OP_STHU 45

#ifdef CONFIG_PPC_BOOK3S
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return 1;
}
#else
static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
{
	return vcpu->arch.tcr & TCR_DIE;
}
#endif

void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
{
	unsigned long dec_nsec;

	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
#ifdef CONFIG_PPC_BOOK3S
	/* mtdec lowers the interrupt line when positive. */
	kvmppc_core_dequeue_dec(vcpu);

	/* POWER4+ triggers a dec interrupt if the value is < 0 */
	if (vcpu->arch.dec & 0x80000000) {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		kvmppc_core_queue_dec(vcpu);
		return;
	}
#endif
	if (kvmppc_dec_enabled(vcpu)) {
		/* The decrementer ticks at the same rate as the timebase, so
		 * that's how we convert the guest DEC value to the number of
		 * host ticks. */

		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
		dec_nsec = vcpu->arch.dec;
		dec_nsec *= 1000;
		dec_nsec /= tb_ticks_per_usec;
		hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
			      HRTIMER_MODE_REL);
		vcpu->arch.dec_jiffies = get_tb();
	} else {
		hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	}
}

/* XXX to do:
 * lhax
 * lhaux
 * lswx
 * lswi
 * stswx
 * stswi
 * lha
 * lhau
 * lmw
 * stmw
 *
 * XXX is_bigendian should depend on MMU mapping or MSR[LE]
 */
/* XXX Should probably auto-generate instruction decoding for a particular core
 * from opcode tables in the future. */
int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
{
	u32 inst = kvmppc_get_last_inst(vcpu);
	u32 ea;
	int ra;
	int rb;
	int rs;
	int rt;
	int sprn;
	enum emulation_result emulated = EMULATE_DONE;
	int advance = 1;

	/* this default type might be overwritten by subcategories */
	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);

	pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));

	switch (get_op(inst)) {
	case OP_TRAP:
#ifdef CONFIG_PPC_BOOK3S
	case OP_TRAP_64:
		kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
#else
		kvmppc_core_queue_program(vcpu, vcpu->arch.esr | ESR_PTR);
#endif
		advance = 0;
		break;

	case 31:
		switch (get_xop(inst)) {

		case OP_31_XOP_LWZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
			break;

		case OP_31_XOP_LBZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
			break;

		case OP_31_XOP_LBZUX:
			rt = get_rt(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_STWX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 1);
			break;

		case OP_31_XOP_STBX:
			rs = get_rs(inst);
			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			break;

		case OP_31_XOP_STBUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               1, 1);
			kvmppc_set_gpr(vcpu, rs, ea);
			break;

		case OP_31_XOP_LHAX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
			break;

		case OP_31_XOP_LHZX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			break;

		case OP_31_XOP_LHZUX:
			rt = get_rt(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MFSPR:
			sprn = get_sprn(inst);
			rt = get_rt(inst);

			switch (sprn) {
			case SPRN_SRR0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr0); break;
			case SPRN_SRR1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr1); break;
			case SPRN_PVR:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
			case SPRN_PIR:
				kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
			case SPRN_MSSSR0:
				kvmppc_set_gpr(vcpu, rt, 0); break;

			/* Note: mftb and TBRL/TBWL are user-accessible, so
			 * the guest can always access the real TB anyways.
			 * In fact, we probably will never see these traps. */
			case SPRN_TBWL:
				kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
			case SPRN_TBWU:
				kvmppc_set_gpr(vcpu, rt, get_tb()); break;

			case SPRN_SPRG0:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg0); break;
			case SPRN_SPRG1:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg1); break;
			case SPRN_SPRG2:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg2); break;
			case SPRN_SPRG3:
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg3); break;
			/* Note: SPRG4-7 are user-readable, so we don't get
			 * a trap. */

			case SPRN_DEC:
			{
				u64 jd = get_tb() - vcpu->arch.dec_jiffies;
				kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd);
				pr_debug("mfDEC: %x - %llx = %lx\n",
					 vcpu->arch.dec, jd,
					 kvmppc_get_gpr(vcpu, rt));
				break;
			}
			default:
				emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
				if (emulated == EMULATE_FAIL) {
					printk("mfspr: unknown spr %x\n", sprn);
					kvmppc_set_gpr(vcpu, rt, 0);
				}
				break;
			}
			break;

		case OP_31_XOP_STHX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			break;

		case OP_31_XOP_STHUX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			ea = kvmppc_get_gpr(vcpu, rb);
			if (ra)
				ea += kvmppc_get_gpr(vcpu, ra);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 1);
			kvmppc_set_gpr(vcpu, ra, ea);
			break;

		case OP_31_XOP_MTSPR:
			sprn = get_sprn(inst);
			rs = get_rs(inst);
			switch (sprn) {
			case SPRN_SRR0:
				vcpu->arch.srr0 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SRR1:
				vcpu->arch.srr1 = kvmppc_get_gpr(vcpu, rs); break;

			/* XXX We need to context-switch the timebase for
			 * watchdog and FIT. */
			case SPRN_TBWL: break;
			case SPRN_TBWU: break;

			case SPRN_MSSSR0: break;

			case SPRN_DEC:
				vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
				kvmppc_emulate_dec(vcpu);
				break;

			case SPRN_SPRG0:
				vcpu->arch.sprg0 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG1:
				vcpu->arch.sprg1 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG2:
				vcpu->arch.sprg2 = kvmppc_get_gpr(vcpu, rs); break;
			case SPRN_SPRG3:
				vcpu->arch.sprg3 = kvmppc_get_gpr(vcpu, rs); break;

			default:
				emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
				if (emulated == EMULATE_FAIL)
					printk("mtspr: unknown spr %x\n", sprn);
				break;
			}
			break;

		case OP_31_XOP_DCBI:
			/* Do nothing. The guest is performing dcbi because
			 * hardware DMA is not snooped by the dcache, but
			 * emulated DMA either goes through the dcache as
			 * normal writes, or the host kernel has handled dcache
			 * coherence. */
			break;

		case OP_31_XOP_LWBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
			break;

		case OP_31_XOP_TLBSYNC:
			break;

		case OP_31_XOP_STWBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               4, 0);
			break;

		case OP_31_XOP_LHBRX:
			rt = get_rt(inst);
			emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
			break;

		case OP_31_XOP_STHBRX:
			rs = get_rs(inst);
			ra = get_ra(inst);
			rb = get_rb(inst);

			emulated = kvmppc_handle_store(run, vcpu,
						       kvmppc_get_gpr(vcpu, rs),
			                               2, 0);
			break;

		default:
			/* Attempt core-specific emulation below. */
			emulated = EMULATE_FAIL;
		}
		break;

	case OP_LWZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		break;

	case OP_LWZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LBZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		break;

	case OP_LBZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STW:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		break;

	case OP_STWU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               4, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STB:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		break;

	case OP_STBU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               1, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LHZ:
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		break;

	case OP_LHZU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_LHA:
		rt = get_rt(inst);
		emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
		break;

	case OP_LHAU:
		ra = get_ra(inst);
		rt = get_rt(inst);
		emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	case OP_STH:
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		break;

	case OP_STHU:
		ra = get_ra(inst);
		rs = get_rs(inst);
		emulated = kvmppc_handle_store(run, vcpu,
					       kvmppc_get_gpr(vcpu, rs),
		                               2, 1);
		kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
		break;

	default:
		emulated = EMULATE_FAIL;
	}

	if (emulated == EMULATE_FAIL) {
		emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
		if (emulated == EMULATE_AGAIN) {
			advance = 0;
		} else if (emulated == EMULATE_FAIL) {
			advance = 0;
			printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
			       "(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
			kvmppc_core_queue_program(vcpu, 0);
		}
	}

	trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);

	/* Advance past emulated instruction. */
	if (advance)
		kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);

	return emulated;
}
Commit	Line	Data
bbf45ba5 HB	1	/*
	2	* This program is free software; you can redistribute it and/or modify
	3	* it under the terms of the GNU General Public License, version 2, as
	4	* published by the Free Software Foundation.
	5	*
	6	* This program is distributed in the hope that it will be useful,
	7	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	8	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	9	* GNU General Public License for more details.
	10	*
	11	* You should have received a copy of the GNU General Public License
	12	* along with this program; if not, write to the Free Software
	13	* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
	14	*
	15	* Copyright IBM Corp. 2007
	16	*
	17	* Authors: Hollis Blanchard <hollisb@us.ibm.com>
	18	*/
	19
	20	#include <linux/jiffies.h>
544c6761	21	#include <linux/hrtimer.h>
bbf45ba5 HB	22	#include <linux/types.h>
	23	#include <linux/string.h>
	24	#include <linux/kvm_host.h>
	25
75f74f0d	26	#include <asm/reg.h>
bbf45ba5 HB	27	#include <asm/time.h>
	28	#include <asm/byteorder.h>
	29	#include <asm/kvm_ppc.h>
c381a043	30	#include <asm/disassemble.h>
73e75b41	31	#include "timing.h"
46f43c6e	32	#include "trace.h"
bbf45ba5	33
cea5d8c9	34	#define OP_TRAP 3
513579e3	35	#define OP_TRAP_64 2
cea5d8c9 HB	36
	37	#define OP_31_XOP_LWZX 23
	38	#define OP_31_XOP_LBZX 87
	39	#define OP_31_XOP_STWX 151
	40	#define OP_31_XOP_STBX 215
1c85e733	41	#define OP_31_XOP_LBZUX 119
cea5d8c9 HB	42	#define OP_31_XOP_STBUX 247
	43	#define OP_31_XOP_LHZX 279
	44	#define OP_31_XOP_LHZUX 311
	45	#define OP_31_XOP_MFSPR 339
1c85e733	46	#define OP_31_XOP_LHAX 343
cea5d8c9 HB	47	#define OP_31_XOP_STHX 407
	48	#define OP_31_XOP_STHUX 439
	49	#define OP_31_XOP_MTSPR 467
	50	#define OP_31_XOP_DCBI 470
	51	#define OP_31_XOP_LWBRX 534
	52	#define OP_31_XOP_TLBSYNC 566
	53	#define OP_31_XOP_STWBRX 662
	54	#define OP_31_XOP_LHBRX 790
	55	#define OP_31_XOP_STHBRX 918
	56
	57	#define OP_LWZ 32
	58	#define OP_LWZU 33
	59	#define OP_LBZ 34
	60	#define OP_LBZU 35
	61	#define OP_STW 36
	62	#define OP_STWU 37
	63	#define OP_STB 38
	64	#define OP_STBU 39
	65	#define OP_LHZ 40
	66	#define OP_LHZU 41
3587d534 AG	67	#define OP_LHA 42
3587d534 AG	68	#define OP_LHAU 43
cea5d8c9 HB	69	#define OP_STH 44
	70	#define OP_STHU 45
	71
00c3a37c	72	#ifdef CONFIG_PPC_BOOK3S
513579e3 AG	73	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	74	{
	75	return 1;
	76	}
	77	#else
	78	static int kvmppc_dec_enabled(struct kvm_vcpu *vcpu)
	79	{
	80	return vcpu->arch.tcr & TCR_DIE;
	81	}
	82	#endif
	83
75f74f0d	84	void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
bbf45ba5	85	{
544c6761	86	unsigned long dec_nsec;
9a7a9b09	87
544c6761	88	pr_debug("mtDEC: %x\n", vcpu->arch.dec);
00c3a37c	89	#ifdef CONFIG_PPC_BOOK3S
7706664d AG	90	/* mtdec lowers the interrupt line when positive. */
	91	kvmppc_core_dequeue_dec(vcpu);
	92
513579e3 AG	93	/* POWER4+ triggers a dec interrupt if the value is < 0 */
513579e3 AG	94	if (vcpu->arch.dec & 0x80000000) {
544c6761	95	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
513579e3 AG	96	kvmppc_core_queue_dec(vcpu);
	97	return;
	98	}
	99	#endif
	100	if (kvmppc_dec_enabled(vcpu)) {
bbf45ba5 HB	101	/* The decrementer ticks at the same rate as the timebase, so
	102	* that's how we convert the guest DEC value to the number of
	103	* host ticks. */
bbf45ba5	104
544c6761 AG	105	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
	106	dec_nsec = vcpu->arch.dec;
	107	dec_nsec *= 1000;
	108	dec_nsec /= tb_ticks_per_usec;
	109	hrtimer_start(&vcpu->arch.dec_timer, ktime_set(0, dec_nsec),
	110	HRTIMER_MODE_REL);
513579e3	111	vcpu->arch.dec_jiffies = get_tb();
bbf45ba5	112	} else {
544c6761	113	hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
bbf45ba5 HB	114	}
	115	}
	116
bbf45ba5 HB	117	/* XXX to do:
	118	* lhax
	119	* lhaux
	120	* lswx
	121	* lswi
	122	* stswx
	123	* stswi
	124	* lha
	125	* lhau
	126	* lmw
	127	* stmw
	128	*
	129	* XXX is_bigendian should depend on MMU mapping or MSR[LE]
	130	*/
75f74f0d HB	131	/* XXX Should probably auto-generate instruction decoding for a particular core
75f74f0d HB	132	* from opcode tables in the future. */
bbf45ba5 HB	133	int kvmppc_emulate_instruction(struct kvm_run run, struct kvm_vcpu vcpu)
bbf45ba5 HB	134	{
c7f38f46	135	u32 inst = kvmppc_get_last_inst(vcpu);
bbf45ba5 HB	136	u32 ea;
	137	int ra;
	138	int rb;
bbf45ba5 HB	139	int rs;
	140	int rt;
	141	int sprn;
bbf45ba5 HB	142	enum emulation_result emulated = EMULATE_DONE;
	143	int advance = 1;
	144
73e75b41 HB	145	/* this default type might be overwritten by subcategories */
	146	kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
	147
689fd14a	148	pr_debug("Emulating opcode %d / %d\n", get_op(inst), get_xop(inst));
513579e3	149
bbf45ba5	150	switch (get_op(inst)) {
cea5d8c9	151	case OP_TRAP:
00c3a37c	152	#ifdef CONFIG_PPC_BOOK3S
513579e3	153	case OP_TRAP_64:
daf5e271	154	kvmppc_core_queue_program(vcpu, SRR1_PROGTRAP);
513579e3	155	#else
daf5e271	156	kvmppc_core_queue_program(vcpu, vcpu->arch.esr \| ESR_PTR);
513579e3	157	#endif
bbf45ba5 HB	158	advance = 0;
	159	break;
	160
bbf45ba5 HB	161	case 31:
	162	switch (get_xop(inst)) {
	163
cea5d8c9	164	case OP_31_XOP_LWZX:
ac3cd34e HB	165	rt = get_rt(inst);
	166	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	167	break;
	168
cea5d8c9	169	case OP_31_XOP_LBZX:
bbf45ba5 HB	170	rt = get_rt(inst);
	171	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	172	break;
	173
1c85e733 AG	174	case OP_31_XOP_LBZUX:
	175	rt = get_rt(inst);
	176	ra = get_ra(inst);
	177	rb = get_rb(inst);
	178
	179	ea = kvmppc_get_gpr(vcpu, rb);
	180	if (ra)
	181	ea += kvmppc_get_gpr(vcpu, ra);
	182
	183	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	184	kvmppc_set_gpr(vcpu, ra, ea);
	185	break;
	186
cea5d8c9	187	case OP_31_XOP_STWX:
ac3cd34e HB	188	rs = get_rs(inst);
ac3cd34e HB	189	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	190	kvmppc_get_gpr(vcpu, rs),
ac3cd34e HB	191	4, 1);
	192	break;
	193
cea5d8c9	194	case OP_31_XOP_STBX:
bbf45ba5 HB	195	rs = get_rs(inst);
bbf45ba5 HB	196	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	197	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	198	1, 1);
	199	break;
	200
cea5d8c9	201	case OP_31_XOP_STBUX:
bbf45ba5 HB	202	rs = get_rs(inst);
	203	ra = get_ra(inst);
	204	rb = get_rb(inst);
	205
8e5b26b5	206	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	207	if (ra)
8e5b26b5	208	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	209
bbf45ba5 HB	210	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	211	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	212	1, 1);
8e5b26b5	213	kvmppc_set_gpr(vcpu, rs, ea);
bbf45ba5 HB	214	break;
bbf45ba5 HB	215
1c85e733 AG	216	case OP_31_XOP_LHAX:
	217	rt = get_rt(inst);
	218	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	219	break;
	220
cea5d8c9	221	case OP_31_XOP_LHZX:
bbf45ba5 HB	222	rt = get_rt(inst);
	223	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	224	break;
	225
cea5d8c9	226	case OP_31_XOP_LHZUX:
bbf45ba5 HB	227	rt = get_rt(inst);
	228	ra = get_ra(inst);
	229	rb = get_rb(inst);
	230
8e5b26b5	231	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	232	if (ra)
8e5b26b5	233	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	234
bbf45ba5 HB	235	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	236	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	237	break;
bbf45ba5 HB	238
cea5d8c9	239	case OP_31_XOP_MFSPR:
bbf45ba5 HB	240	sprn = get_sprn(inst);
	241	rt = get_rt(inst);
	242
	243	switch (sprn) {
	244	case SPRN_SRR0:
8e5b26b5	245	kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr0); break;
bbf45ba5	246	case SPRN_SRR1:
8e5b26b5	247	kvmppc_set_gpr(vcpu, rt, vcpu->arch.srr1); break;
bbf45ba5	248	case SPRN_PVR:
8e5b26b5	249	kvmppc_set_gpr(vcpu, rt, vcpu->arch.pvr); break;
06579dd9	250	case SPRN_PIR:
8e5b26b5	251	kvmppc_set_gpr(vcpu, rt, vcpu->vcpu_id); break;
513579e3	252	case SPRN_MSSSR0:
8e5b26b5	253	kvmppc_set_gpr(vcpu, rt, 0); break;
bbf45ba5 HB	254
	255	/* Note: mftb and TBRL/TBWL are user-accessible, so
	256	* the guest can always access the real TB anyways.
	257	* In fact, we probably will never see these traps. */
	258	case SPRN_TBWL:
8e5b26b5	259	kvmppc_set_gpr(vcpu, rt, get_tb() >> 32); break;
bbf45ba5	260	case SPRN_TBWU:
8e5b26b5	261	kvmppc_set_gpr(vcpu, rt, get_tb()); break;
bbf45ba5 HB	262
bbf45ba5 HB	263	case SPRN_SPRG0:
8e5b26b5	264	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg0); break;
bbf45ba5	265	case SPRN_SPRG1:
8e5b26b5	266	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg1); break;
bbf45ba5	267	case SPRN_SPRG2:
8e5b26b5	268	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg2); break;
bbf45ba5	269	case SPRN_SPRG3:
8e5b26b5	270	kvmppc_set_gpr(vcpu, rt, vcpu->arch.sprg3); break;
bbf45ba5 HB	271	/* Note: SPRG4-7 are user-readable, so we don't get
	272	* a trap. */
	273
9a7a9b09 AG	274	case SPRN_DEC:
9a7a9b09 AG	275	{
513579e3	276	u64 jd = get_tb() - vcpu->arch.dec_jiffies;
8e5b26b5	277	kvmppc_set_gpr(vcpu, rt, vcpu->arch.dec - jd);
689fd14a	278	pr_debug("mfDEC: %x - %llx = %lx\n",
8e5b26b5 AG	279	vcpu->arch.dec, jd,
8e5b26b5 AG	280	kvmppc_get_gpr(vcpu, rt));
9a7a9b09 AG	281	break;
9a7a9b09 AG	282	}
bbf45ba5	283	default:
75f74f0d HB	284	emulated = kvmppc_core_emulate_mfspr(vcpu, sprn, rt);
	285	if (emulated == EMULATE_FAIL) {
	286	printk("mfspr: unknown spr %x\n", sprn);
8e5b26b5	287	kvmppc_set_gpr(vcpu, rt, 0);
75f74f0d	288	}
bbf45ba5 HB	289	break;
	290	}
	291	break;
	292
cea5d8c9	293	case OP_31_XOP_STHX:
bbf45ba5 HB	294	rs = get_rs(inst);
	295	ra = get_ra(inst);
	296	rb = get_rb(inst);
	297
	298	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	299	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	300	2, 1);
	301	break;
	302
cea5d8c9	303	case OP_31_XOP_STHUX:
bbf45ba5 HB	304	rs = get_rs(inst);
	305	ra = get_ra(inst);
	306	rb = get_rb(inst);
	307
8e5b26b5	308	ea = kvmppc_get_gpr(vcpu, rb);
bbf45ba5	309	if (ra)
8e5b26b5	310	ea += kvmppc_get_gpr(vcpu, ra);
bbf45ba5 HB	311
bbf45ba5 HB	312	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	313	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	314	2, 1);
8e5b26b5	315	kvmppc_set_gpr(vcpu, ra, ea);
bbf45ba5 HB	316	break;
bbf45ba5 HB	317
cea5d8c9	318	case OP_31_XOP_MTSPR:
bbf45ba5 HB	319	sprn = get_sprn(inst);
	320	rs = get_rs(inst);
	321	switch (sprn) {
	322	case SPRN_SRR0:
8e5b26b5	323	vcpu->arch.srr0 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	324	case SPRN_SRR1:
8e5b26b5	325	vcpu->arch.srr1 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5 HB	326
	327	/* XXX We need to context-switch the timebase for
	328	* watchdog and FIT. */
	329	case SPRN_TBWL: break;
	330	case SPRN_TBWU: break;
	331
513579e3 AG	332	case SPRN_MSSSR0: break;
513579e3 AG	333
bbf45ba5	334	case SPRN_DEC:
8e5b26b5	335	vcpu->arch.dec = kvmppc_get_gpr(vcpu, rs);
bbf45ba5 HB	336	kvmppc_emulate_dec(vcpu);
	337	break;
	338
bbf45ba5	339	case SPRN_SPRG0:
8e5b26b5	340	vcpu->arch.sprg0 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	341	case SPRN_SPRG1:
8e5b26b5	342	vcpu->arch.sprg1 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	343	case SPRN_SPRG2:
8e5b26b5	344	vcpu->arch.sprg2 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	345	case SPRN_SPRG3:
8e5b26b5	346	vcpu->arch.sprg3 = kvmppc_get_gpr(vcpu, rs); break;
bbf45ba5	347
bbf45ba5	348	default:
75f74f0d HB	349	emulated = kvmppc_core_emulate_mtspr(vcpu, sprn, rs);
	350	if (emulated == EMULATE_FAIL)
	351	printk("mtspr: unknown spr %x\n", sprn);
bbf45ba5 HB	352	break;
	353	}
	354	break;
	355
cea5d8c9	356	case OP_31_XOP_DCBI:
bbf45ba5 HB	357	/* Do nothing. The guest is performing dcbi because
	358	* hardware DMA is not snooped by the dcache, but
	359	* emulated DMA either goes through the dcache as
	360	* normal writes, or the host kernel has handled dcache
	361	* coherence. */
	362	break;
	363
cea5d8c9	364	case OP_31_XOP_LWBRX:
bbf45ba5 HB	365	rt = get_rt(inst);
	366	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
	367	break;
	368
cea5d8c9	369	case OP_31_XOP_TLBSYNC:
bbf45ba5 HB	370	break;
bbf45ba5 HB	371
cea5d8c9	372	case OP_31_XOP_STWBRX:
bbf45ba5 HB	373	rs = get_rs(inst);
	374	ra = get_ra(inst);
	375	rb = get_rb(inst);
	376
	377	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	378	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	379	4, 0);
	380	break;
	381
cea5d8c9	382	case OP_31_XOP_LHBRX:
bbf45ba5 HB	383	rt = get_rt(inst);
	384	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
	385	break;
	386
cea5d8c9	387	case OP_31_XOP_STHBRX:
bbf45ba5 HB	388	rs = get_rs(inst);
	389	ra = get_ra(inst);
	390	rb = get_rb(inst);
	391
	392	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5	393	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	394	2, 0);
	395	break;
	396
bbf45ba5	397	default:
75f74f0d	398	/* Attempt core-specific emulation below. */
bbf45ba5	399	emulated = EMULATE_FAIL;
bbf45ba5 HB	400	}
	401	break;
	402
cea5d8c9	403	case OP_LWZ:
bbf45ba5 HB	404	rt = get_rt(inst);
	405	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
	406	break;
	407
cea5d8c9	408	case OP_LWZU:
bbf45ba5 HB	409	ra = get_ra(inst);
	410	rt = get_rt(inst);
	411	emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
8e5b26b5	412	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	413	break;
bbf45ba5 HB	414
cea5d8c9	415	case OP_LBZ:
bbf45ba5 HB	416	rt = get_rt(inst);
	417	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
	418	break;
	419
cea5d8c9	420	case OP_LBZU:
bbf45ba5 HB	421	ra = get_ra(inst);
	422	rt = get_rt(inst);
	423	emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
8e5b26b5	424	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	425	break;
bbf45ba5 HB	426
cea5d8c9	427	case OP_STW:
bbf45ba5	428	rs = get_rs(inst);
8e5b26b5 AG	429	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	430	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	431	4, 1);
	432	break;
	433
cea5d8c9	434	case OP_STWU:
bbf45ba5 HB	435	ra = get_ra(inst);
bbf45ba5 HB	436	rs = get_rs(inst);
8e5b26b5 AG	437	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	438	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	439	4, 1);
8e5b26b5	440	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	441	break;
bbf45ba5 HB	442
cea5d8c9	443	case OP_STB:
bbf45ba5	444	rs = get_rs(inst);
8e5b26b5 AG	445	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	446	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	447	1, 1);
	448	break;
	449
cea5d8c9	450	case OP_STBU:
bbf45ba5 HB	451	ra = get_ra(inst);
bbf45ba5 HB	452	rs = get_rs(inst);
8e5b26b5 AG	453	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	454	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	455	1, 1);
8e5b26b5	456	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	457	break;
bbf45ba5 HB	458
cea5d8c9	459	case OP_LHZ:
bbf45ba5 HB	460	rt = get_rt(inst);
	461	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
	462	break;
	463
cea5d8c9	464	case OP_LHZU:
bbf45ba5 HB	465	ra = get_ra(inst);
	466	rt = get_rt(inst);
	467	emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
8e5b26b5	468	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	469	break;
bbf45ba5 HB	470
3587d534 AG	471	case OP_LHA:
	472	rt = get_rt(inst);
	473	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	474	break;
	475
	476	case OP_LHAU:
	477	ra = get_ra(inst);
	478	rt = get_rt(inst);
	479	emulated = kvmppc_handle_loads(run, vcpu, rt, 2, 1);
	480	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
	481	break;
	482
cea5d8c9	483	case OP_STH:
bbf45ba5	484	rs = get_rs(inst);
8e5b26b5 AG	485	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	486	kvmppc_get_gpr(vcpu, rs),
bbf45ba5 HB	487	2, 1);
	488	break;
	489
cea5d8c9	490	case OP_STHU:
bbf45ba5 HB	491	ra = get_ra(inst);
bbf45ba5 HB	492	rs = get_rs(inst);
8e5b26b5 AG	493	emulated = kvmppc_handle_store(run, vcpu,
8e5b26b5 AG	494	kvmppc_get_gpr(vcpu, rs),
bbf45ba5	495	2, 1);
8e5b26b5	496	kvmppc_set_gpr(vcpu, ra, vcpu->arch.paddr_accessed);
bbf45ba5 HB	497	break;
	498
	499	default:
bbf45ba5	500	emulated = EMULATE_FAIL;
75f74f0d HB	501	}
	502
	503	if (emulated == EMULATE_FAIL) {
	504	emulated = kvmppc_core_emulate_op(run, vcpu, inst, &advance);
37f5bca6 AG	505	if (emulated == EMULATE_AGAIN) {
	506	advance = 0;
	507	} else if (emulated == EMULATE_FAIL) {
75f74f0d HB	508	advance = 0;
	509	printk(KERN_ERR "Couldn't emulate instruction 0x%08x "
	510	"(op %d xop %d)\n", inst, get_op(inst), get_xop(inst));
5f2b105a	511	kvmppc_core_queue_program(vcpu, 0);
75f74f0d	512	}
bbf45ba5 HB	513	}
bbf45ba5 HB	514
c7f38f46	515	trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
3b4bd796	516
c7f38f46	517	/* Advance past emulated instruction. */
bbf45ba5	518	if (advance)
c7f38f46	519	kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
bbf45ba5 HB	520
	521	return emulated;
	522	}