[net-next-2.6.git] / arch / mips / alchemy / common / sleeper.S

/*
 * Copyright 2002 Embedded Edge, LLC
 * Author: dan@embeddededge.com
 *
 * Sleep helper for Au1xxx sleep mode.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>

	.extern __flush_cache_all

	.text
	.set noreorder
	.set noat
	.align	5


/* preparatory stuff */
.macro	SETUP_SLEEP
	subu	sp, PT_SIZE
	sw	$1, PT_R1(sp)
	sw	$2, PT_R2(sp)
	sw	$3, PT_R3(sp)
	sw	$4, PT_R4(sp)
	sw	$5, PT_R5(sp)
	sw	$6, PT_R6(sp)
	sw	$7, PT_R7(sp)
	sw	$16, PT_R16(sp)
	sw	$17, PT_R17(sp)
	sw	$18, PT_R18(sp)
	sw	$19, PT_R19(sp)
	sw	$20, PT_R20(sp)
	sw	$21, PT_R21(sp)
	sw	$22, PT_R22(sp)
	sw	$23, PT_R23(sp)
	sw	$26, PT_R26(sp)
	sw	$27, PT_R27(sp)
	sw	$28, PT_R28(sp)
	sw	$30, PT_R30(sp)
	sw	$31, PT_R31(sp)
	mfc0	k0, CP0_STATUS
	sw	k0, 0x20(sp)
	mfc0	k0, CP0_CONTEXT
	sw	k0, 0x1c(sp)
	mfc0	k0, CP0_PAGEMASK
	sw	k0, 0x18(sp)
	mfc0	k0, CP0_CONFIG
	sw	k0, 0x14(sp)

	/* flush caches to make sure context is in memory */
	la	t1, __flush_cache_all
	lw	t0, 0(t1)
	jalr	t0
	 nop

	/* Now set up the scratch registers so the boot rom will
	 * return to this point upon wakeup.
	 * sys_scratch0 : SP
	 * sys_scratch1 : RA
	 */
	lui	t3, 0xb190		/* sys_xxx */
	sw	sp, 0x0018(t3)
	la	k0, alchemy_sleep_wakeup	/* resume path */
	sw	k0, 0x001c(t3)
.endm

.macro	DO_SLEEP
	/* put power supply and processor to sleep */
	sw	zero, 0x0078(t3)	/* sys_slppwr */
	sync
	sw	zero, 0x007c(t3)	/* sys_sleep */
	sync
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
.endm

/* sleep code for Au1000/Au1100/Au1500 memory controller type */
LEAF(alchemy_sleep_au1000)

	SETUP_SLEEP

	/* cache following instructions, as memory gets put to sleep */
	la	t0, 1f
	.set	mips3
	cache	0x14, 0(t0)
	cache	0x14, 32(t0)
	cache	0x14, 64(t0)
	cache	0x14, 96(t0)
	.set	mips0

1:	lui 	a0, 0xb400		/* mem_xxx */
	sw	zero, 0x001c(a0) 	/* Precharge */
	sync
	sw	zero, 0x0020(a0)	/* Auto Refresh */
	sync
	sw	zero, 0x0030(a0)  	/* Sleep */
	sync

	DO_SLEEP

END(alchemy_sleep_au1000)

/* sleep code for Au1550/Au1200 memory controller type */
LEAF(alchemy_sleep_au1550)

	SETUP_SLEEP

	/* cache following instructions, as memory gets put to sleep */
	la	t0, 1f
	.set	mips3
	cache	0x14, 0(t0)
	cache	0x14, 32(t0)
	cache	0x14, 64(t0)
	cache	0x14, 96(t0)
	.set	mips0

1:	lui 	a0, 0xb400		/* mem_xxx */
	sw	zero, 0x08c0(a0) 	/* Precharge */
	sync
	sw	zero, 0x08d0(a0)	/* Self Refresh */
	sync

	/* wait for sdram to enter self-refresh mode */
	lui 	t0, 0x0100
2:	lw 	t1, 0x0850(a0)		/* mem_sdstat */
	and	t2, t1, t0
	beq	t2, zero, 2b
	 nop

	/* disable SDRAM clocks */
	lui	t0, 0xcfff
	ori	t0, t0, 0xffff
	lw 	t1, 0x0840(a0)		/* mem_sdconfiga */
	and 	t1, t0, t1		/* clear CE[1:0] */
	sw 	t1, 0x0840(a0)		/* mem_sdconfiga */
	sync

	DO_SLEEP

END(alchemy_sleep_au1550)


	/* This is where we return upon wakeup.
	 * Reload all of the registers and return.
	 */
LEAF(alchemy_sleep_wakeup)
	lw	k0, 0x20(sp)
	mtc0	k0, CP0_STATUS
	lw	k0, 0x1c(sp)
	mtc0	k0, CP0_CONTEXT
	lw	k0, 0x18(sp)
	mtc0	k0, CP0_PAGEMASK
	lw	k0, 0x14(sp)
	mtc0	k0, CP0_CONFIG

	/* We need to catch the early Alchemy SOCs with
	 * the write-only Config[OD] bit and set it back to one...
	 */
	jal	au1x00_fixup_config_od
	 nop
	lw	$1, PT_R1(sp)
	lw	$2, PT_R2(sp)
	lw	$3, PT_R3(sp)
	lw	$4, PT_R4(sp)
	lw	$5, PT_R5(sp)
	lw	$6, PT_R6(sp)
	lw	$7, PT_R7(sp)
	lw	$16, PT_R16(sp)
	lw	$17, PT_R17(sp)
	lw	$18, PT_R18(sp)
	lw	$19, PT_R19(sp)
	lw	$20, PT_R20(sp)
	lw	$21, PT_R21(sp)
	lw	$22, PT_R22(sp)
	lw	$23, PT_R23(sp)
	lw	$26, PT_R26(sp)
	lw	$27, PT_R27(sp)
	lw	$28, PT_R28(sp)
	lw	$30, PT_R30(sp)
	lw	$31, PT_R31(sp)
	jr	ra
	 addiu	sp, PT_SIZE
END(alchemy_sleep_wakeup)
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright 2002 Embedded Edge, LLC
	3	* Author: dan@embeddededge.com
	4	*
	5	* Sleep helper for Au1xxx sleep mode.
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or (at your
	10	* option) any later version.
	11	*/
ce28f94c	12
1da177e4 LT	13	#include <asm/asm.h>
1da177e4 LT	14	#include <asm/mipsregs.h>
1da177e4 LT	15	#include <asm/regdef.h>
	16	#include <asm/stackframe.h>
	17
564365b0 ML	18	.extern __flush_cache_all
564365b0 ML	19
1da177e4	20	.text
564365b0 ML	21	.set noreorder
564365b0 ML	22	.set noat
1da177e4 LT	23	.align 5
1da177e4 LT	24
2e93d1ec ML	25
	26	/* preparatory stuff */
	27	.macro SETUP_SLEEP
1da177e4 LT	28	subu sp, PT_SIZE
	29	sw $1, PT_R1(sp)
	30	sw $2, PT_R2(sp)
	31	sw $3, PT_R3(sp)
	32	sw $4, PT_R4(sp)
	33	sw $5, PT_R5(sp)
	34	sw $6, PT_R6(sp)
	35	sw $7, PT_R7(sp)
1da177e4 LT	36	sw $16, PT_R16(sp)
	37	sw $17, PT_R17(sp)
	38	sw $18, PT_R18(sp)
	39	sw $19, PT_R19(sp)
	40	sw $20, PT_R20(sp)
	41	sw $21, PT_R21(sp)
	42	sw $22, PT_R22(sp)
	43	sw $23, PT_R23(sp)
1da177e4 LT	44	sw $26, PT_R26(sp)
	45	sw $27, PT_R27(sp)
	46	sw $28, PT_R28(sp)
1da177e4 LT	47	sw $30, PT_R30(sp)
	48	sw $31, PT_R31(sp)
	49	mfc0 k0, CP0_STATUS
	50	sw k0, 0x20(sp)
	51	mfc0 k0, CP0_CONTEXT
	52	sw k0, 0x1c(sp)
	53	mfc0 k0, CP0_PAGEMASK
	54	sw k0, 0x18(sp)
	55	mfc0 k0, CP0_CONFIG
	56	sw k0, 0x14(sp)
	57
564365b0 ML	58	/* flush caches to make sure context is in memory */
	59	la t1, __flush_cache_all
	60	lw t0, 0(t1)
	61	jalr t0
	62	nop
	63
1da177e4 LT	64	/* Now set up the scratch registers so the boot rom will
1da177e4 LT	65	* return to this point upon wakeup.
564365b0 ML	66	* sys_scratch0 : SP
564365b0 ML	67	* sys_scratch1 : RA
1da177e4	68	*/
564365b0 ML	69	lui t3, 0xb190 /* sys_xxx */
564365b0 ML	70	sw sp, 0x0018(t3)
2e93d1ec	71	la k0, alchemy_sleep_wakeup /* resume path */
564365b0	72	sw k0, 0x001c(t3)
2e93d1ec	73	.endm
1da177e4	74
2e93d1ec ML	75	.macro DO_SLEEP
	76	/* put power supply and processor to sleep */
	77	sw zero, 0x0078(t3) /* sys_slppwr */
	78	sync
	79	sw zero, 0x007c(t3) /* sys_sleep */
	80	sync
	81	nop
	82	nop
	83	nop
	84	nop
	85	nop
	86	nop
	87	nop
	88	nop
	89	.endm
	90
	91	/* sleep code for Au1000/Au1100/Au1500 memory controller type */
	92	LEAF(alchemy_sleep_au1000)
	93
	94	SETUP_SLEEP
	95
	96	/* cache following instructions, as memory gets put to sleep */
564365b0	97	la t0, 1f
1da177e4	98	.set mips3
e8c7c482 RB	99	cache 0x14, 0(t0)
	100	cache 0x14, 32(t0)
	101	cache 0x14, 64(t0)
	102	cache 0x14, 96(t0)
1da177e4 LT	103	.set mips0
1da177e4 LT	104
564365b0	105	1: lui a0, 0xb400 /* mem_xxx */
564365b0 ML	106	sw zero, 0x001c(a0) /* Precharge */
	107	sync
	108	sw zero, 0x0020(a0) /* Auto Refresh */
	109	sync
	110	sw zero, 0x0030(a0) /* Sleep */
	111	sync
564365b0	112
2e93d1ec ML	113	DO_SLEEP
	114
	115	END(alchemy_sleep_au1000)
	116
	117	/* sleep code for Au1550/Au1200 memory controller type */
	118	LEAF(alchemy_sleep_au1550)
	119
	120	SETUP_SLEEP
	121
	122	/* cache following instructions, as memory gets put to sleep */
	123	la t0, 1f
	124	.set mips3
	125	cache 0x14, 0(t0)
	126	cache 0x14, 32(t0)
	127	cache 0x14, 64(t0)
	128	cache 0x14, 96(t0)
	129	.set mips0
	130
	131	1: lui a0, 0xb400 /* mem_xxx */
564365b0	132	sw zero, 0x08c0(a0) /* Precharge */
1da177e4	133	sync
564365b0 ML	134	sw zero, 0x08d0(a0) /* Self Refresh */
	135	sync
	136
	137	/* wait for sdram to enter self-refresh mode */
	138	lui t0, 0x0100
	139	2: lw t1, 0x0850(a0) /* mem_sdstat */
	140	and t2, t1, t0
	141	beq t2, zero, 2b
	142	nop
1da177e4	143
564365b0 ML	144	/* disable SDRAM clocks */
	145	lui t0, 0xcfff
	146	ori t0, t0, 0xffff
	147	lw t1, 0x0840(a0) /* mem_sdconfiga */
	148	and t1, t0, t1 /* clear CE[1:0] */
	149	sw t1, 0x0840(a0) /* mem_sdconfiga */
1da177e4	150	sync
564365b0	151
2e93d1ec ML	152	DO_SLEEP
	153
	154	END(alchemy_sleep_au1550)
	155
1da177e4 LT	156
	157	/* This is where we return upon wakeup.
	158	* Reload all of the registers and return.
	159	*/
2e93d1ec ML	160	LEAF(alchemy_sleep_wakeup)
2e93d1ec ML	161	lw k0, 0x20(sp)
1da177e4 LT	162	mtc0 k0, CP0_STATUS
	163	lw k0, 0x1c(sp)
	164	mtc0 k0, CP0_CONTEXT
	165	lw k0, 0x18(sp)
	166	mtc0 k0, CP0_PAGEMASK
	167	lw k0, 0x14(sp)
	168	mtc0 k0, CP0_CONFIG
9370b351	169
564365b0	170	/* We need to catch the early Alchemy SOCs with
9370b351 SS	171	* the write-only Config[OD] bit and set it back to one...
	172	*/
	173	jal au1x00_fixup_config_od
564365b0	174	nop
1da177e4 LT	175	lw $1, PT_R1(sp)
	176	lw $2, PT_R2(sp)
	177	lw $3, PT_R3(sp)
	178	lw $4, PT_R4(sp)
	179	lw $5, PT_R5(sp)
	180	lw $6, PT_R6(sp)
	181	lw $7, PT_R7(sp)
1da177e4 LT	182	lw $16, PT_R16(sp)
	183	lw $17, PT_R17(sp)
	184	lw $18, PT_R18(sp)
	185	lw $19, PT_R19(sp)
	186	lw $20, PT_R20(sp)
	187	lw $21, PT_R21(sp)
	188	lw $22, PT_R22(sp)
	189	lw $23, PT_R23(sp)
1da177e4 LT	190	lw $26, PT_R26(sp)
	191	lw $27, PT_R27(sp)
	192	lw $28, PT_R28(sp)
1da177e4 LT	193	lw $30, PT_R30(sp)
1da177e4 LT	194	lw $31, PT_R31(sp)
1da177e4	195	jr ra
564365b0	196	addiu sp, PT_SIZE
2e93d1ec	197	END(alchemy_sleep_wakeup)