[net-next-2.6.git] / arch / microblaze / kernel / timer.c

/*
 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
 * Copyright (C) 2007-2009 PetaLogix
 * Copyright (C) 2006 Atmark Techno, Inc.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/irq.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/bug.h>
#include <asm/cpuinfo.h>
#include <asm/setup.h>
#include <asm/prom.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <linux/cnt32_to_63.h>

#ifdef CONFIG_SELFMOD_TIMER
#include <asm/selfmod.h>
#define TIMER_BASE	BARRIER_BASE_ADDR
#else
static unsigned int timer_baseaddr;
#define TIMER_BASE	timer_baseaddr
#endif

#define TCSR0	(0x00)
#define TLR0	(0x04)
#define TCR0	(0x08)
#define TCSR1	(0x10)
#define TLR1	(0x14)
#define TCR1	(0x18)

#define TCSR_MDT	(1<<0)
#define TCSR_UDT	(1<<1)
#define TCSR_GENT	(1<<2)
#define TCSR_CAPT	(1<<3)
#define TCSR_ARHT	(1<<4)
#define TCSR_LOAD	(1<<5)
#define TCSR_ENIT	(1<<6)
#define TCSR_ENT	(1<<7)
#define TCSR_TINT	(1<<8)
#define TCSR_PWMA	(1<<9)
#define TCSR_ENALL	(1<<10)

static inline void microblaze_timer0_stop(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
}

static inline void microblaze_timer0_start_periodic(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	/* see timer data sheet for detail
	 * !ENALL - don't enable 'em all
	 * !PWMA - disable pwm
	 * TINT - clear interrupt status
	 * ENT- enable timer itself
	 * EINT - enable interrupt
	 * !LOAD - clear the bit to let go
	 * ARHT - auto reload
	 * !CAPT - no external trigger
	 * !GENT - no external signal
	 * UDT - set the timer as down counter
	 * !MDT0 - generate mode
	 */
	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
{
	if (!load_val)
		load_val = 1;
	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */

	/* load the initial value */
	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);

	out_be32(TIMER_BASE + TCSR0,
			TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT);
}

static int microblaze_timer_set_next_event(unsigned long delta,
					struct clock_event_device *dev)
{
	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
	microblaze_timer0_start_oneshot(delta);
	return 0;
}

static void microblaze_timer_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_INFO "%s: periodic\n", __func__);
		microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		printk(KERN_INFO "%s: oneshot\n", __func__);
		break;
	case CLOCK_EVT_MODE_UNUSED:
		printk(KERN_INFO "%s: unused\n", __func__);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
		printk(KERN_INFO "%s: shutdown\n", __func__);
		microblaze_timer0_stop();
		break;
	case CLOCK_EVT_MODE_RESUME:
		printk(KERN_INFO "%s: resume\n", __func__);
		break;
	}
}

static struct clock_event_device clockevent_microblaze_timer = {
	.name		= "microblaze_clockevent",
	.features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.shift		= 8,
	.rating		= 300,
	.set_next_event	= microblaze_timer_set_next_event,
	.set_mode	= microblaze_timer_set_mode,
};

static inline void timer_ack(void)
{
	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
}

static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_microblaze_timer;
#ifdef CONFIG_HEART_BEAT
	heartbeat();
#endif
	timer_ack();
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction timer_irqaction = {
	.handler = timer_interrupt,
	.flags = IRQF_DISABLED | IRQF_TIMER,
	.name = "timer",
	.dev_id = &clockevent_microblaze_timer,
};

static __init void microblaze_clockevent_init(void)
{
	clockevent_microblaze_timer.mult =
		div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
				clockevent_microblaze_timer.shift);
	clockevent_microblaze_timer.max_delta_ns =
		clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.min_delta_ns =
		clockevent_delta2ns(1, &clockevent_microblaze_timer);
	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_microblaze_timer);
}

static cycle_t microblaze_read(struct clocksource *cs)
{
	/* reading actual value of timer 1 */
	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
}

static struct timecounter microblaze_tc = {
	.cc = NULL,
};

static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
{
	return microblaze_read(NULL);
}

static struct cyclecounter microblaze_cc = {
	.read = microblaze_cc_read,
	.mask = CLOCKSOURCE_MASK(32),
	.shift = 8,
};

int __init init_microblaze_timecounter(void)
{
	microblaze_cc.mult = div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
				microblaze_cc.shift);

	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());

	return 0;
}

static struct clocksource clocksource_microblaze = {
	.name		= "microblaze_clocksource",
	.rating		= 300,
	.read		= microblaze_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.shift		= 8, /* I can shift it */
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static int __init microblaze_clocksource_init(void)
{
	clocksource_microblaze.mult =
			clocksource_hz2mult(cpuinfo.cpu_clock_freq,
						clocksource_microblaze.shift);
	if (clocksource_register(&clocksource_microblaze))
		panic("failed to register clocksource");

	/* stop timer1 */
	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	/* start timer1 - up counting without interrupt */
	out_be32(TIMER_BASE + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT);

	/* register timecounter - for ftrace support */
	init_microblaze_timecounter();
	return 0;
}

/*
 * We have to protect accesses before timer initialization
 * and return 0 for sched_clock function below.
 */
static int timer_initialized;

void __init time_init(void)
{
	u32 irq, i = 0;
	u32 timer_num = 1;
	struct device_node *timer = NULL;
#ifdef CONFIG_SELFMOD_TIMER
	unsigned int timer_baseaddr = 0;
	int arr_func[] = {
				(int)&microblaze_read,
				(int)&timer_interrupt,
				(int)&microblaze_clocksource_init,
				(int)&microblaze_timer_set_mode,
				(int)&microblaze_timer_set_next_event,
				0
			};
#endif
	const char * const timer_list[] = {
		"xlnx,xps-timer-1.00.a",
		"xlnx,opb-timer-1.00.b",
		"xlnx,opb-timer-1.00.a",
		NULL
	};

	for (i = 0; timer_list[i] != NULL; i++) {
		timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
		if (timer)
			break;
	}
	BUG_ON(!timer);

	timer_baseaddr = *(int *) of_get_property(timer, "reg", NULL);
	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
	irq = *(int *) of_get_property(timer, "interrupts", NULL);
	timer_num =
		*(int *) of_get_property(timer, "xlnx,one-timer-only", NULL);
	if (timer_num) {
		eprintk(KERN_EMERG "Please enable two timers in HW\n");
		BUG();
	}

#ifdef CONFIG_SELFMOD_TIMER
	selfmod_function((int *) arr_func, timer_baseaddr);
#endif
	printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
		timer_list[i], timer_baseaddr, irq);

	cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;

	setup_irq(irq, &timer_irqaction);
#ifdef CONFIG_HEART_BEAT
	setup_heartbeat();
#endif
	microblaze_clocksource_init();
	microblaze_clockevent_init();
	timer_initialized = 1;
}

unsigned long long notrace sched_clock(void)
{
	if (timer_initialized) {
		struct clocksource *cs = &clocksource_microblaze;
		cycle_t cyc = cnt32_to_63(cs->read(NULL));
		return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	}
	return 0;
}
Commit	Line	Data
eedbdab9 MS	1	/*
	2	* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
	3	* Copyright (C) 2007-2009 PetaLogix
	4	* Copyright (C) 2006 Atmark Techno, Inc.
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/param.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/profile.h>
	16	#include <linux/irq.h>
	17	#include <linux/delay.h>
	18	#include <linux/sched.h>
	19	#include <linux/spinlock.h>
	20	#include <linux/err.h>
	21	#include <linux/clk.h>
	22	#include <linux/clocksource.h>
	23	#include <linux/clockchips.h>
	24	#include <linux/io.h>
892ee92b	25	#include <linux/bug.h>
eedbdab9 MS	26	#include <asm/cpuinfo.h>
	27	#include <asm/setup.h>
	28	#include <asm/prom.h>
	29	#include <asm/irq.h>
	30	#include <asm/system.h>
c8f77436	31	#include <linux/cnt32_to_63.h>
eedbdab9 MS	32
	33	#ifdef CONFIG_SELFMOD_TIMER
	34	#include <asm/selfmod.h>
	35	#define TIMER_BASE BARRIER_BASE_ADDR
	36	#else
	37	static unsigned int timer_baseaddr;
	38	#define TIMER_BASE timer_baseaddr
	39	#endif
	40
	41	#define TCSR0 (0x00)
	42	#define TLR0 (0x04)
	43	#define TCR0 (0x08)
	44	#define TCSR1 (0x10)
	45	#define TLR1 (0x14)
	46	#define TCR1 (0x18)
	47
	48	#define TCSR_MDT (1<<0)
	49	#define TCSR_UDT (1<<1)
	50	#define TCSR_GENT (1<<2)
	51	#define TCSR_CAPT (1<<3)
	52	#define TCSR_ARHT (1<<4)
	53	#define TCSR_LOAD (1<<5)
	54	#define TCSR_ENIT (1<<6)
	55	#define TCSR_ENT (1<<7)
	56	#define TCSR_TINT (1<<8)
	57	#define TCSR_PWMA (1<<9)
	58	#define TCSR_ENALL (1<<10)
	59
	60	static inline void microblaze_timer0_stop(void)
	61	{
	62	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0) & ~TCSR_ENT);
	63	}
	64
	65	static inline void microblaze_timer0_start_periodic(unsigned long load_val)
	66	{
	67	if (!load_val)
	68	load_val = 1;
	69	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
	70
	71	/* load the initial value */
	72	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
	73
	74	/* see timer data sheet for detail
	75	* !ENALL - don't enable 'em all
	76	* !PWMA - disable pwm
	77	* TINT - clear interrupt status
	78	* ENT- enable timer itself
	79	* EINT - enable interrupt
	80	* !LOAD - clear the bit to let go
	81	* ARHT - auto reload
	82	* !CAPT - no external trigger
	83	* !GENT - no external signal
	84	* UDT - set the timer as down counter
	85	* !MDT0 - generate mode
	86	*/
	87	out_be32(TIMER_BASE + TCSR0,
	88	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
	89	}
	90
	91	static inline void microblaze_timer0_start_oneshot(unsigned long load_val)
	92	{
	93	if (!load_val)
	94	load_val = 1;
	95	out_be32(TIMER_BASE + TLR0, load_val); /* loading value to timer reg */
96
97	/* load the initial value */
98	out_be32(TIMER_BASE + TCSR0, TCSR_LOAD);
99
100	out_be32(TIMER_BASE + TCSR0,
101	TCSR_TINT\|TCSR_ENIT\|TCSR_ENT\|TCSR_ARHT\|TCSR_UDT);
102	}
103
104	static int microblaze_timer_set_next_event(unsigned long delta,
105	struct clock_event_device *dev)
106	{
107	pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
108	microblaze_timer0_start_oneshot(delta);
109	return 0;
110	}
111
112	static void microblaze_timer_set_mode(enum clock_event_mode mode,
113	struct clock_event_device *evt)
114	{
115	switch (mode) {
116	case CLOCK_EVT_MODE_PERIODIC:
117	printk(KERN_INFO "%s: periodic\n", __func__);
118	microblaze_timer0_start_periodic(cpuinfo.freq_div_hz);
119	break;
120	case CLOCK_EVT_MODE_ONESHOT:
121	printk(KERN_INFO "%s: oneshot\n", __func__);
122	break;
123	case CLOCK_EVT_MODE_UNUSED:
124	printk(KERN_INFO "%s: unused\n", __func__);
125	break;
126	case CLOCK_EVT_MODE_SHUTDOWN:
127	printk(KERN_INFO "%s: shutdown\n", __func__);
128	microblaze_timer0_stop();
129	break;
130	case CLOCK_EVT_MODE_RESUME:
131	printk(KERN_INFO "%s: resume\n", __func__);
132	break;
133	}
134	}
135
136	static struct clock_event_device clockevent_microblaze_timer = {
137	.name = "microblaze_clockevent",
138	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
c8f77436	139	.shift = 8,
eedbdab9 MS	140	.rating = 300,
	141	.set_next_event = microblaze_timer_set_next_event,
	142	.set_mode = microblaze_timer_set_mode,
	143	};
	144
	145	static inline void timer_ack(void)
	146	{
	147	out_be32(TIMER_BASE + TCSR0, in_be32(TIMER_BASE + TCSR0));
	148	}
	149
	150	static irqreturn_t timer_interrupt(int irq, void *dev_id)
	151	{
	152	struct clock_event_device *evt = &clockevent_microblaze_timer;
	153	#ifdef CONFIG_HEART_BEAT
	154	heartbeat();
	155	#endif
	156	timer_ack();
	157	evt->event_handler(evt);
	158	return IRQ_HANDLED;
	159	}
	160
	161	static struct irqaction timer_irqaction = {
	162	.handler = timer_interrupt,
	163	.flags = IRQF_DISABLED \| IRQF_TIMER,
	164	.name = "timer",
	165	.dev_id = &clockevent_microblaze_timer,
	166	};
	167
	168	static __init void microblaze_clockevent_init(void)
	169	{
	170	clockevent_microblaze_timer.mult =
	171	div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
	172	clockevent_microblaze_timer.shift);
	173	clockevent_microblaze_timer.max_delta_ns =
	174	clockevent_delta2ns((u32)~0, &clockevent_microblaze_timer);
	175	clockevent_microblaze_timer.min_delta_ns =
	176	clockevent_delta2ns(1, &clockevent_microblaze_timer);
	177	clockevent_microblaze_timer.cpumask = cpumask_of(0);
	178	clockevents_register_device(&clockevent_microblaze_timer);
	179	}
	180
f57f2fe2	181	static cycle_t microblaze_read(struct clocksource *cs)
eedbdab9 MS	182	{
	183	/* reading actual value of timer 1 */
	184	return (cycle_t) (in_be32(TIMER_BASE + TCR1));
	185	}
	186
519e9f41 MS	187	static struct timecounter microblaze_tc = {
	188	.cc = NULL,
	189	};
	190
	191	static cycle_t microblaze_cc_read(const struct cyclecounter *cc)
	192	{
	193	return microblaze_read(NULL);
	194	}
	195
	196	static struct cyclecounter microblaze_cc = {
	197	.read = microblaze_cc_read,
	198	.mask = CLOCKSOURCE_MASK(32),
c8f77436	199	.shift = 8,
519e9f41 MS	200	};
	201
	202	int __init init_microblaze_timecounter(void)
	203	{
	204	microblaze_cc.mult = div_sc(cpuinfo.cpu_clock_freq, NSEC_PER_SEC,
	205	microblaze_cc.shift);
	206
	207	timecounter_init(&microblaze_tc, &microblaze_cc, sched_clock());
	208
	209	return 0;
	210	}
	211
eedbdab9 MS	212	static struct clocksource clocksource_microblaze = {
	213	.name = "microblaze_clocksource",
	214	.rating = 300,
	215	.read = microblaze_read,
	216	.mask = CLOCKSOURCE_MASK(32),
c8f77436	217	.shift = 8, /* I can shift it */
eedbdab9 MS	218	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	219	};
	220
	221	static int __init microblaze_clocksource_init(void)
	222	{
	223	clocksource_microblaze.mult =
	224	clocksource_hz2mult(cpuinfo.cpu_clock_freq,
	225	clocksource_microblaze.shift);
	226	if (clocksource_register(&clocksource_microblaze))
	227	panic("failed to register clocksource");
	228
	229	/* stop timer1 */
	230	out_be32(TIMER_BASE + TCSR1, in_be32(TIMER_BASE + TCSR1) & ~TCSR_ENT);
	231	/* start timer1 - up counting without interrupt */
	232	out_be32(TIMER_BASE + TCSR1, TCSR_TINT\|TCSR_ENT\|TCSR_ARHT);
519e9f41 MS	233
	234	/* register timecounter - for ftrace support */
	235	init_microblaze_timecounter();
eedbdab9 MS	236	return 0;
	237	}
	238
6f34b08f MS	239	/*
	240	* We have to protect accesses before timer initialization
	241	* and return 0 for sched_clock function below.
	242	*/
	243	static int timer_initialized;
	244
eedbdab9 MS	245	void __init time_init(void)
	246	{
	247	u32 irq, i = 0;
	248	u32 timer_num = 1;
	249	struct device_node *timer = NULL;
	250	#ifdef CONFIG_SELFMOD_TIMER
	251	unsigned int timer_baseaddr = 0;
	252	int arr_func[] = {
	253	(int)&microblaze_read,
	254	(int)&timer_interrupt,
	255	(int)&microblaze_clocksource_init,
	256	(int)&microblaze_timer_set_mode,
	257	(int)&microblaze_timer_set_next_event,
	258	0
	259	};
	260	#endif
92ee8bd4 JP	261	const char * const timer_list[] = {
	262	"xlnx,xps-timer-1.00.a",
	263	"xlnx,opb-timer-1.00.b",
	264	"xlnx,opb-timer-1.00.a",
	265	NULL
	266	};
eedbdab9 MS	267
	268	for (i = 0; timer_list[i] != NULL; i++) {
	269	timer = of_find_compatible_node(NULL, NULL, timer_list[i]);
	270	if (timer)
	271	break;
	272	}
892ee92b	273	BUG_ON(!timer);
eedbdab9 MS	274
	275	timer_baseaddr = (int ) of_get_property(timer, "reg", NULL);
	276	timer_baseaddr = (unsigned long) ioremap(timer_baseaddr, PAGE_SIZE);
	277	irq = (int ) of_get_property(timer, "interrupts", NULL);
	278	timer_num =
	279	(int ) of_get_property(timer, "xlnx,one-timer-only", NULL);
	280	if (timer_num) {
69717607	281	eprintk(KERN_EMERG "Please enable two timers in HW\n");
eedbdab9 MS	282	BUG();
	283	}
	284
	285	#ifdef CONFIG_SELFMOD_TIMER
	286	selfmod_function((int *) arr_func, timer_baseaddr);
	287	#endif
	288	printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n",
	289	timer_list[i], timer_baseaddr, irq);
	290
	291	cpuinfo.freq_div_hz = cpuinfo.cpu_clock_freq / HZ;
	292
	293	setup_irq(irq, &timer_irqaction);
	294	#ifdef CONFIG_HEART_BEAT
	295	setup_heartbeat();
	296	#endif
	297	microblaze_clocksource_init();
	298	microblaze_clockevent_init();
6f34b08f MS	299	timer_initialized = 1;
	300	}
	301
	302	unsigned long long notrace sched_clock(void)
	303	{
	304	if (timer_initialized) {
	305	struct clocksource *cs = &clocksource_microblaze;
c8f77436	306	cycle_t cyc = cnt32_to_63(cs->read(NULL));
6f34b08f MS	307	return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	308	}
	309	return 0;
eedbdab9	310	}