[net-next-2.6.git] / arch / ia64 / mm / tlb.c

/*
 * TLB support routines.
 *
 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
 *		Modified RID allocation for SMP
 *          Goutham Rao <goutham.rao@intel.com>
 *              IPI based ptc implementation and A-step IPI implementation.
 * Rohit Seth <rohit.seth@intel.com>
 * Ken Chen <kenneth.w.chen@intel.com>
 * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
 * Copyright (C) 2007 Intel Corp
 *	Fenghua Yu <fenghua.yu@intel.com>
 *	Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <linux/slab.h>

#include <asm/delay.h>
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
#include <asm/pal.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
#include <asm/processor.h>
#include <asm/sal.h>
#include <asm/tlb.h>

static struct {
	u64 mask;		/* mask of supported purge page-sizes */
	unsigned long max_bits;	/* log2 of largest supported purge page-size */
} purge;

struct ia64_ctx ia64_ctx = {
	.lock =	__SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
	.next =	1,
	.max_ctx = ~0U
};

DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/

struct ia64_tr_entry *ia64_idtrs[NR_CPUS];

/*
 * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
 * Called after cpu_init() has setup ia64_ctx.max_ctx based on
 * maximum RID that is supported by boot CPU.
 */
void __init
mmu_context_init (void)
{
	ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
}

/*
 * Acquire the ia64_ctx.lock before calling this function!
 */
void
wrap_mmu_context (struct mm_struct *mm)
{
	int i, cpu;
	unsigned long flush_bit;

	for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
		flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
		ia64_ctx.bitmap[i] ^= flush_bit;
	}
 
	/* use offset at 300 to skip daemons */
	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
				ia64_ctx.max_ctx, 300);
	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
				ia64_ctx.max_ctx, ia64_ctx.next);

	/*
	 * can't call flush_tlb_all() here because of race condition
	 * with O(1) scheduler [EF]
	 */
	cpu = get_cpu(); /* prevent preemption/migration */
	for_each_online_cpu(i)
		if (i != cpu)
			per_cpu(ia64_need_tlb_flush, i) = 1;
	put_cpu();
	local_flush_tlb_all();
}

/*
 * Implement "spinaphores" ... like counting semaphores, but they
 * spin instead of sleeping.  If there are ever any other users for
 * this primitive it can be moved up to a spinaphore.h header.
 */
struct spinaphore {
	unsigned long	ticket;
	unsigned long	serve;
};

static inline void spinaphore_init(struct spinaphore *ss, int val)
{
	ss->ticket = 0;
	ss->serve = val;
}

static inline void down_spin(struct spinaphore *ss)
{
	unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;

	if (time_before(t, ss->serve))
		return;

	ia64_invala();

	for (;;) {
		asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
		if (time_before(t, serve))
			return;
		cpu_relax();
	}
}

static inline void up_spin(struct spinaphore *ss)
{
	ia64_fetchadd(1, &ss->serve, rel);
}

static struct spinaphore ptcg_sem;
static u16 nptcg = 1;
static int need_ptcg_sem = 1;
static int toolatetochangeptcgsem = 0;

/*
 * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
 * purges which is reported from either PAL or SAL PALO.
 *
 * We don't have sanity checking for nptcg value. It's the user's responsibility
 * for valid nptcg value on the platform. Otherwise, kernel may hang in some
 * cases.
 */
static int __init
set_nptcg(char *str)
{
	int value = 0;

	get_option(&str, &value);
	setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);

	return 1;
}

__setup("nptcg=", set_nptcg);

/*
 * Maximum number of simultaneous ptc.g purges in the system can
 * be defined by PAL_VM_SUMMARY (in which case we should take
 * the smallest value for any cpu in the system) or by the PAL
 * override table (in which case we should ignore the value from
 * PAL_VM_SUMMARY).
 *
 * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
 * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
 * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
 *
 * Complicating the logic here is the fact that num_possible_cpus()
 * isn't fully setup until we start bringing cpus online.
 */
void
setup_ptcg_sem(int max_purges, int nptcg_from)
{
	static int kp_override;
	static int palo_override;
	static int firstcpu = 1;

	if (toolatetochangeptcgsem) {
		if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
			BUG_ON(1 < nptcg);
		else
			BUG_ON(max_purges < nptcg);
		return;
	}

	if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
		kp_override = 1;
		nptcg = max_purges;
		goto resetsema;
	}
	if (kp_override) {
		need_ptcg_sem = num_possible_cpus() > nptcg;
		return;
	}

	if (nptcg_from == NPTCG_FROM_PALO) {
		palo_override = 1;

		/* In PALO max_purges == 0 really means it! */
		if (max_purges == 0)
			panic("Whoa! Platform does not support global TLB purges.\n");
		nptcg = max_purges;
		if (nptcg == PALO_MAX_TLB_PURGES) {
			need_ptcg_sem = 0;
			return;
		}
		goto resetsema;
	}
	if (palo_override) {
		if (nptcg != PALO_MAX_TLB_PURGES)
			need_ptcg_sem = (num_possible_cpus() > nptcg);
		return;
	}

	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
	if (max_purges == 0) max_purges = 1;

	if (firstcpu) {
		nptcg = max_purges;
		firstcpu = 0;
	}
	if (max_purges < nptcg)
		nptcg = max_purges;
	if (nptcg == PAL_MAX_PURGES) {
		need_ptcg_sem = 0;
		return;
	} else
		need_ptcg_sem = (num_possible_cpus() > nptcg);

resetsema:
	spinaphore_init(&ptcg_sem, max_purges);
}

void
ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
		       unsigned long end, unsigned long nbits)
{
	struct mm_struct *active_mm = current->active_mm;

	toolatetochangeptcgsem = 1;

	if (mm != active_mm) {
		/* Restore region IDs for mm */
		if (mm && active_mm) {
			activate_context(mm);
		} else {
			flush_tlb_all();
			return;
		}
	}

	if (need_ptcg_sem)
		down_spin(&ptcg_sem);

	do {
		/*
		 * Flush ALAT entries also.
		 */
		ia64_ptcga(start, (nbits << 2));
		ia64_srlz_i();
		start += (1UL << nbits);
	} while (start < end);

	if (need_ptcg_sem)
		up_spin(&ptcg_sem);

        if (mm != active_mm) {
                activate_context(active_mm);
        }
}

void
local_flush_tlb_all (void)
{
	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;

	addr    = local_cpu_data->ptce_base;
	count0  = local_cpu_data->ptce_count[0];
	count1  = local_cpu_data->ptce_count[1];
	stride0 = local_cpu_data->ptce_stride[0];
	stride1 = local_cpu_data->ptce_stride[1];

	local_irq_save(flags);
	for (i = 0; i < count0; ++i) {
		for (j = 0; j < count1; ++j) {
			ia64_ptce(addr);
			addr += stride1;
		}
		addr += stride0;
	}
	local_irq_restore(flags);
	ia64_srlz_i();			/* srlz.i implies srlz.d */
}

void
flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
		 unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	unsigned long size = end - start;
	unsigned long nbits;

#ifndef CONFIG_SMP
	if (mm != current->active_mm) {
		mm->context = 0;
		return;
	}
#endif

	nbits = ia64_fls(size + 0xfff);
	while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
			(nbits < purge.max_bits))
		++nbits;
	if (nbits > purge.max_bits)
		nbits = purge.max_bits;
	start &= ~((1UL << nbits) - 1);

	preempt_disable();
#ifdef CONFIG_SMP
	if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
		platform_global_tlb_purge(mm, start, end, nbits);
		preempt_enable();
		return;
	}
#endif
	do {
		ia64_ptcl(start, (nbits<<2));
		start += (1UL << nbits);
	} while (start < end);
	preempt_enable();
	ia64_srlz_i();			/* srlz.i implies srlz.d */
}
EXPORT_SYMBOL(flush_tlb_range);

void __devinit
ia64_tlb_init (void)
{
	ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
	u64 tr_pgbits;
	long status;
	pal_vm_info_1_u_t vm_info_1;
	pal_vm_info_2_u_t vm_info_2;
	int cpu = smp_processor_id();

	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
		       "defaulting to architected purge page-sizes.\n", status);
		purge.mask = 0x115557000UL;
	}
	purge.max_bits = ia64_fls(purge.mask);

	ia64_get_ptce(&ptce_info);
	local_cpu_data->ptce_base = ptce_info.base;
	local_cpu_data->ptce_count[0] = ptce_info.count[0];
	local_cpu_data->ptce_count[1] = ptce_info.count[1];
	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];

	local_flush_tlb_all();	/* nuke left overs from bootstrapping... */
	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);

	if (status) {
		printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
		per_cpu(ia64_tr_num, cpu) = 8;
		return;
	}
	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
	if (per_cpu(ia64_tr_num, cpu) >
				(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
		per_cpu(ia64_tr_num, cpu) =
				vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
	if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
		static int justonce = 1;
		per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
		if (justonce) {
			justonce = 0;
			printk(KERN_DEBUG "TR register number exceeds "
			       "IA64_TR_ALLOC_MAX!\n");
		}
	}
}

/*
 * is_tr_overlap
 *
 * Check overlap with inserted TRs.
 */
static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
{
	u64 tr_log_size;
	u64 tr_end;
	u64 va_rr = ia64_get_rr(va);
	u64 va_rid = RR_TO_RID(va_rr);
	u64 va_end = va + (1<<log_size) - 1;

	if (va_rid != RR_TO_RID(p->rr))
		return 0;
	tr_log_size = (p->itir & 0xff) >> 2;
	tr_end = p->ifa + (1<<tr_log_size) - 1;

	if (va > tr_end || p->ifa > va_end)
		return 0;
	return 1;

}

/*
 * ia64_insert_tr in virtual mode. Allocate a TR slot
 *
 * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
 *
 * va 	: virtual address.
 * pte 	: pte entries inserted.
 * log_size: range to be covered.
 *
 * Return value:  <0 :  error No.
 *
 *		  >=0 : slot number allocated for TR.
 * Must be called with preemption disabled.
 */
int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
{
	int i, r;
	unsigned long psr;
	struct ia64_tr_entry *p;
	int cpu = smp_processor_id();

	if (!ia64_idtrs[cpu]) {
		ia64_idtrs[cpu] = kmalloc(2 * IA64_TR_ALLOC_MAX *
				sizeof (struct ia64_tr_entry), GFP_KERNEL);
		if (!ia64_idtrs[cpu])
			return -ENOMEM;
	}
	r = -EINVAL;
	/*Check overlap with existing TR entries*/
	if (target_mask & 0x1) {
		p = ia64_idtrs[cpu];
		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
								i++, p++) {
			if (p->pte & 0x1)
				if (is_tr_overlap(p, va, log_size)) {
					printk(KERN_DEBUG "Overlapped Entry"
						"Inserted for TR Reigster!!\n");
					goto out;
			}
		}
	}
	if (target_mask & 0x2) {
		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
								i++, p++) {
			if (p->pte & 0x1)
				if (is_tr_overlap(p, va, log_size)) {
					printk(KERN_DEBUG "Overlapped Entry"
						"Inserted for TR Reigster!!\n");
					goto out;
				}
		}
	}

	for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
		switch (target_mask & 0x3) {
		case 1:
			if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
				goto found;
			continue;
		case 2:
			if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
				goto found;
			continue;
		case 3:
			if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
			    !((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
				goto found;
			continue;
		default:
			r = -EINVAL;
			goto out;
		}
	}
found:
	if (i >= per_cpu(ia64_tr_num, cpu))
		return -EBUSY;

	/*Record tr info for mca hander use!*/
	if (i > per_cpu(ia64_tr_used, cpu))
		per_cpu(ia64_tr_used, cpu) = i;

	psr = ia64_clear_ic();
	if (target_mask & 0x1) {
		ia64_itr(0x1, i, va, pte, log_size);
		ia64_srlz_i();
		p = ia64_idtrs[cpu] + i;
		p->ifa = va;
		p->pte = pte;
		p->itir = log_size << 2;
		p->rr = ia64_get_rr(va);
	}
	if (target_mask & 0x2) {
		ia64_itr(0x2, i, va, pte, log_size);
		ia64_srlz_i();
		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
		p->ifa = va;
		p->pte = pte;
		p->itir = log_size << 2;
		p->rr = ia64_get_rr(va);
	}
	ia64_set_psr(psr);
	r = i;
out:
	return r;
}
EXPORT_SYMBOL_GPL(ia64_itr_entry);

/*
 * ia64_purge_tr
 *
 * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
 * slot: slot number to be freed.
 *
 * Must be called with preemption disabled.
 */
void ia64_ptr_entry(u64 target_mask, int slot)
{
	int cpu = smp_processor_id();
	int i;
	struct ia64_tr_entry *p;

	if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
		return;

	if (target_mask & 0x1) {
		p = ia64_idtrs[cpu] + slot;
		if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
			p->pte = 0;
			ia64_ptr(0x1, p->ifa, p->itir>>2);
			ia64_srlz_i();
		}
	}

	if (target_mask & 0x2) {
		p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
		if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
			p->pte = 0;
			ia64_ptr(0x2, p->ifa, p->itir>>2);
			ia64_srlz_i();
		}
	}

	for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
		if (((ia64_idtrs[cpu] + i)->pte & 0x1) ||
		    ((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
			break;
	}
	per_cpu(ia64_tr_used, cpu) = i;
}
EXPORT_SYMBOL_GPL(ia64_ptr_entry);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* TLB support routines.
	3	*
	4	* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
	5	* David Mosberger-Tang <davidm@hpl.hp.com>
	6	*
	7	* 08/02/00 A. Mallick <asit.k.mallick@intel.com>
	8	* Modified RID allocation for SMP
	9	* Goutham Rao <goutham.rao@intel.com>
	10	* IPI based ptc implementation and A-step IPI implementation.
dcc17d1b PK	11	* Rohit Seth <rohit.seth@intel.com>
dcc17d1b PK	12	* Ken Chen <kenneth.w.chen@intel.com>
aec103bf	13	* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
2046b94e FY	14	* Copyright (C) 2007 Intel Corp
	15	* Fenghua Yu <fenghua.yu@intel.com>
	16	* Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
1da177e4	17	*/
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/smp.h>
	23	#include <linux/mm.h>
dcc17d1b	24	#include <linux/bootmem.h>
5a0e3ad6	25	#include <linux/slab.h>
1da177e4 LT	26
	27	#include <asm/delay.h>
	28	#include <asm/mmu_context.h>
	29	#include <asm/pgalloc.h>
	30	#include <asm/pal.h>
	31	#include <asm/tlbflush.h>
dcc17d1b	32	#include <asm/dma.h>
96651896	33	#include <asm/processor.h>
2046b94e	34	#include <asm/sal.h>
96651896	35	#include <asm/tlb.h>
1da177e4 LT	36
1da177e4 LT	37	static struct {
e088a4ad	38	u64 mask; /* mask of supported purge page-sizes */
58cd9082	39	unsigned long max_bits; /* log2 of largest supported purge page-size */
1da177e4 LT	40	} purge;
	41
	42	struct ia64_ctx ia64_ctx = {
8737d595 MAC	43	.lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
	44	.next = 1,
	45	.max_ctx = ~0U
1da177e4 LT	46	};
	47
	48	DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
96651896 XZ	49	DEFINE_PER_CPU(u8, ia64_tr_num); /Number of TR slots in current processor/
	50	DEFINE_PER_CPU(u8, ia64_tr_used); /Max Slot number used by kernel/
	51
6c57a332	52	struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
1da177e4	53
dcc17d1b PK	54	/*
	55	* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
	56	* Called after cpu_init() has setup ia64_ctx.max_ctx based on
	57	* maximum RID that is supported by boot CPU.
	58	*/
	59	void __init
	60	mmu_context_init (void)
	61	{
	62	ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	63	ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	64	}
	65
1da177e4 LT	66	/*
	67	* Acquire the ia64_ctx.lock before calling this function!
	68	*/
	69	void
	70	wrap_mmu_context (struct mm_struct *mm)
	71	{
58cd9082	72	int i, cpu;
dcc17d1b	73	unsigned long flush_bit;
1da177e4	74
dcc17d1b PK	75	for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
	76	flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
	77	ia64_ctx.bitmap[i] ^= flush_bit;
1da177e4	78	}
dcc17d1b PK	79
	80	/* use offset at 300 to skip daemons */
	81	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
	82	ia64_ctx.max_ctx, 300);
	83	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
	84	ia64_ctx.max_ctx, ia64_ctx.next);
	85
58cd9082 KC	86	/*
	87	* can't call flush_tlb_all() here because of race condition
	88	* with O(1) scheduler [EF]
	89	*/
	90	cpu = get_cpu(); /* prevent preemption/migration */
	91	for_each_online_cpu(i)
	92	if (i != cpu)
	93	per_cpu(ia64_need_tlb_flush, i) = 1;
	94	put_cpu();
1da177e4 LT	95	local_flush_tlb_all();
	96	}
	97
2046b94e FY	98	/*
	99	* Implement "spinaphores" ... like counting semaphores, but they
	100	* spin instead of sleeping. If there are ever any other users for
	101	* this primitive it can be moved up to a spinaphore.h header.
	102	*/
	103	struct spinaphore {
883a3acf TL	104	unsigned long ticket;
883a3acf TL	105	unsigned long serve;
2046b94e FY	106	};
	107
	108	static inline void spinaphore_init(struct spinaphore *ss, int val)
	109	{
883a3acf TL	110	ss->ticket = 0;
883a3acf TL	111	ss->serve = val;
2046b94e FY	112	}
	113
	114	static inline void down_spin(struct spinaphore *ss)
	115	{
883a3acf TL	116	unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
	117
	118	if (time_before(t, ss->serve))
	119	return;
	120
	121	ia64_invala();
	122
	123	for (;;) {
b70f4e85	124	asm volatile ("ld8.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
883a3acf TL	125	if (time_before(t, serve))
	126	return;
	127	cpu_relax();
	128	}
2046b94e FY	129	}
	130
	131	static inline void up_spin(struct spinaphore *ss)
	132	{
883a3acf	133	ia64_fetchadd(1, &ss->serve, rel);
2046b94e FY	134	}
	135
	136	static struct spinaphore ptcg_sem;
	137	static u16 nptcg = 1;
	138	static int need_ptcg_sem = 1;
	139	static int toolatetochangeptcgsem = 0;
	140
a6c75b86 FY	141	/*
	142	* Kernel parameter "nptcg=" overrides max number of concurrent global TLB
	143	* purges which is reported from either PAL or SAL PALO.
	144	*
	145	* We don't have sanity checking for nptcg value. It's the user's responsibility
	146	* for valid nptcg value on the platform. Otherwise, kernel may hang in some
	147	* cases.
	148	*/
	149	static int __init
	150	set_nptcg(char *str)
	151	{
	152	int value = 0;
	153
	154	get_option(&str, &value);
	155	setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
	156
	157	return 1;
	158	}
	159
	160	__setup("nptcg=", set_nptcg);
	161
2046b94e FY	162	/*
	163	* Maximum number of simultaneous ptc.g purges in the system can
	164	* be defined by PAL_VM_SUMMARY (in which case we should take
	165	* the smallest value for any cpu in the system) or by the PAL
	166	* override table (in which case we should ignore the value from
	167	* PAL_VM_SUMMARY).
	168	*
a6c75b86 FY	169	* Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
	170	* purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
	171	* we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
	172	*
2046b94e FY	173	* Complicating the logic here is the fact that num_possible_cpus()
	174	* isn't fully setup until we start bringing cpus online.
	175	*/
	176	void
a6c75b86	177	setup_ptcg_sem(int max_purges, int nptcg_from)
2046b94e	178	{
a6c75b86 FY	179	static int kp_override;
a6c75b86 FY	180	static int palo_override;
2046b94e FY	181	static int firstcpu = 1;
	182
	183	if (toolatetochangeptcgsem) {
e617fce6 HS	184	if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
	185	BUG_ON(1 < nptcg);
	186	else
	187	BUG_ON(max_purges < nptcg);
2046b94e FY	188	return;
	189	}
	190
a6c75b86 FY	191	if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
	192	kp_override = 1;
	193	nptcg = max_purges;
	194	goto resetsema;
	195	}
	196	if (kp_override) {
	197	need_ptcg_sem = num_possible_cpus() > nptcg;
	198	return;
	199	}
	200
	201	if (nptcg_from == NPTCG_FROM_PALO) {
	202	palo_override = 1;
2046b94e FY	203
	204	/* In PALO max_purges == 0 really means it! */
	205	if (max_purges == 0)
	206	panic("Whoa! Platform does not support global TLB purges.\n");
	207	nptcg = max_purges;
	208	if (nptcg == PALO_MAX_TLB_PURGES) {
	209	need_ptcg_sem = 0;
	210	return;
	211	}
	212	goto resetsema;
	213	}
a6c75b86	214	if (palo_override) {
2046b94e FY	215	if (nptcg != PALO_MAX_TLB_PURGES)
	216	need_ptcg_sem = (num_possible_cpus() > nptcg);
	217	return;
	218	}
	219
	220	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
	221	if (max_purges == 0) max_purges = 1;
	222
	223	if (firstcpu) {
	224	nptcg = max_purges;
	225	firstcpu = 0;
	226	}
	227	if (max_purges < nptcg)
	228	nptcg = max_purges;
	229	if (nptcg == PAL_MAX_PURGES) {
	230	need_ptcg_sem = 0;
	231	return;
	232	} else
	233	need_ptcg_sem = (num_possible_cpus() > nptcg);
	234
	235	resetsema:
	236	spinaphore_init(&ptcg_sem, max_purges);
	237	}
	238
1da177e4	239	void
58cd9082 KC	240	ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
58cd9082 KC	241	unsigned long end, unsigned long nbits)
1da177e4	242	{
aec103bf DCIV	243	struct mm_struct *active_mm = current->active_mm;
aec103bf DCIV	244
2046b94e FY	245	toolatetochangeptcgsem = 1;
2046b94e FY	246
aec103bf DCIV	247	if (mm != active_mm) {
	248	/* Restore region IDs for mm */
	249	if (mm && active_mm) {
	250	activate_context(mm);
	251	} else {
	252	flush_tlb_all();
	253	return;
	254	}
c1902aae DR	255	}
c1902aae DR	256
2046b94e FY	257	if (need_ptcg_sem)
	258	down_spin(&ptcg_sem);
	259
	260	do {
	261	/*
	262	* Flush ALAT entries also.
	263	*/
	264	ia64_ptcga(start, (nbits << 2));
	265	ia64_srlz_i();
	266	start += (1UL << nbits);
	267	} while (start < end);
	268
	269	if (need_ptcg_sem)
	270	up_spin(&ptcg_sem);
aec103bf DCIV	271
	272	if (mm != active_mm) {
	273	activate_context(active_mm);
	274	}
1da177e4 LT	275	}
	276
	277	void
	278	local_flush_tlb_all (void)
	279	{
	280	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
	281
	282	addr = local_cpu_data->ptce_base;
	283	count0 = local_cpu_data->ptce_count[0];
	284	count1 = local_cpu_data->ptce_count[1];
	285	stride0 = local_cpu_data->ptce_stride[0];
	286	stride1 = local_cpu_data->ptce_stride[1];
	287
	288	local_irq_save(flags);
	289	for (i = 0; i < count0; ++i) {
	290	for (j = 0; j < count1; ++j) {
	291	ia64_ptce(addr);
	292	addr += stride1;
	293	}
	294	addr += stride0;
	295	}
	296	local_irq_restore(flags);
	297	ia64_srlz_i(); /* srlz.i implies srlz.d */
	298	}
	299
	300	void
58cd9082 KC	301	flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
58cd9082 KC	302	unsigned long end)
1da177e4 LT	303	{
	304	struct mm_struct *mm = vma->vm_mm;
	305	unsigned long size = end - start;
	306	unsigned long nbits;
	307
c1902aae	308	#ifndef CONFIG_SMP
1da177e4	309	if (mm != current->active_mm) {
1da177e4	310	mm->context = 0;
1da177e4 LT	311	return;
1da177e4 LT	312	}
c1902aae	313	#endif
1da177e4 LT	314
1da177e4 LT	315	nbits = ia64_fls(size + 0xfff);
58cd9082 KC	316	while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
58cd9082 KC	317	(nbits < purge.max_bits))
1da177e4 LT	318	++nbits;
	319	if (nbits > purge.max_bits)
	320	nbits = purge.max_bits;
	321	start &= ~((1UL << nbits) - 1);
	322
663b97f7	323	preempt_disable();
ce9eed5a	324	#ifdef CONFIG_SMP
5d8c39f6	325	if (mm != current->active_mm \|\| cpumask_weight(mm_cpumask(mm)) != 1) {
ce9eed5a KC	326	platform_global_tlb_purge(mm, start, end, nbits);
	327	preempt_enable();
	328	return;
	329	}
	330	#endif
1da177e4 LT	331	do {
	332	ia64_ptcl(start, (nbits<<2));
	333	start += (1UL << nbits);
	334	} while (start < end);
663b97f7	335	preempt_enable();
1da177e4 LT	336	ia64_srlz_i(); /* srlz.i implies srlz.d */
	337	}
	338	EXPORT_SYMBOL(flush_tlb_range);
	339
	340	void __devinit
	341	ia64_tlb_init (void)
	342	{
256a7e09	343	ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
e088a4ad	344	u64 tr_pgbits;
1da177e4	345	long status;
96651896 XZ	346	pal_vm_info_1_u_t vm_info_1;
	347	pal_vm_info_2_u_t vm_info_2;
	348	int cpu = smp_processor_id();
1da177e4 LT	349
1da177e4 LT	350	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
c2eeb321	351	printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
1da177e4 LT	352	"defaulting to architected purge page-sizes.\n", status);
	353	purge.mask = 0x115557000UL;
	354	}
	355	purge.max_bits = ia64_fls(purge.mask);
	356
	357	ia64_get_ptce(&ptce_info);
	358	local_cpu_data->ptce_base = ptce_info.base;
	359	local_cpu_data->ptce_count[0] = ptce_info.count[0];
	360	local_cpu_data->ptce_count[1] = ptce_info.count[1];
	361	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
	362	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
	363
58cd9082	364	local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
96651896 XZ	365	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
	366
	367	if (status) {
	368	printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
	369	per_cpu(ia64_tr_num, cpu) = 8;
	370	return;
	371	}
	372	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
	373	if (per_cpu(ia64_tr_num, cpu) >
	374	(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
	375	per_cpu(ia64_tr_num, cpu) =
	376	vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
	377	if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
a9894a4a	378	static int justonce = 1;
96651896	379	per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
a9894a4a TL	380	if (justonce) {
	381	justonce = 0;
	382	printk(KERN_DEBUG "TR register number exceeds "
	383	"IA64_TR_ALLOC_MAX!\n");
	384	}
96651896 XZ	385	}
	386	}
	387
	388	/*
	389	* is_tr_overlap
	390	*
	391	* Check overlap with inserted TRs.
	392	*/
	393	static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
	394	{
	395	u64 tr_log_size;
	396	u64 tr_end;
	397	u64 va_rr = ia64_get_rr(va);
	398	u64 va_rid = RR_TO_RID(va_rr);
	399	u64 va_end = va + (1<<log_size) - 1;
	400
	401	if (va_rid != RR_TO_RID(p->rr))
	402	return 0;
	403	tr_log_size = (p->itir & 0xff) >> 2;
	404	tr_end = p->ifa + (1<<tr_log_size) - 1;
	405
	406	if (va > tr_end \|\| p->ifa > va_end)
	407	return 0;
	408	return 1;
	409
	410	}
	411
	412	/*
	413	* ia64_insert_tr in virtual mode. Allocate a TR slot
	414	*
	415	* target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
	416	*
	417	* va : virtual address.
	418	* pte : pte entries inserted.
	419	* log_size: range to be covered.
	420	*
	421	* Return value: <0 : error No.
	422	*
	423	* >=0 : slot number allocated for TR.
	424	* Must be called with preemption disabled.
	425	*/
	426	int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
	427	{
	428	int i, r;
	429	unsigned long psr;
	430	struct ia64_tr_entry *p;
	431	int cpu = smp_processor_id();
	432
6c57a332 TL	433	if (!ia64_idtrs[cpu]) {
	434	ia64_idtrs[cpu] = kmalloc(2 * IA64_TR_ALLOC_MAX *
	435	sizeof (struct ia64_tr_entry), GFP_KERNEL);
	436	if (!ia64_idtrs[cpu])
	437	return -ENOMEM;
	438	}
96651896 XZ	439	r = -EINVAL;
	440	/Check overlap with existing TR entries/
	441	if (target_mask & 0x1) {
6c57a332	442	p = ia64_idtrs[cpu];
96651896 XZ	443	for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
	444	i++, p++) {
	445	if (p->pte & 0x1)
	446	if (is_tr_overlap(p, va, log_size)) {
	447	printk(KERN_DEBUG "Overlapped Entry"
	448	"Inserted for TR Reigster!!\n");
	449	goto out;
	450	}
	451	}
	452	}
	453	if (target_mask & 0x2) {
6c57a332	454	p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX;
96651896 XZ	455	for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
	456	i++, p++) {
	457	if (p->pte & 0x1)
	458	if (is_tr_overlap(p, va, log_size)) {
	459	printk(KERN_DEBUG "Overlapped Entry"
	460	"Inserted for TR Reigster!!\n");
	461	goto out;
	462	}
	463	}
	464	}
	465
	466	for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
	467	switch (target_mask & 0x3) {
	468	case 1:
6c57a332	469	if (!((ia64_idtrs[cpu] + i)->pte & 0x1))
96651896 XZ	470	goto found;
	471	continue;
	472	case 2:
6c57a332	473	if (!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
96651896 XZ	474	goto found;
	475	continue;
	476	case 3:
6c57a332 TL	477	if (!((ia64_idtrs[cpu] + i)->pte & 0x1) &&
6c57a332 TL	478	!((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
96651896 XZ	479	goto found;
	480	continue;
	481	default:
	482	r = -EINVAL;
	483	goto out;
	484	}
	485	}
	486	found:
	487	if (i >= per_cpu(ia64_tr_num, cpu))
	488	return -EBUSY;
	489
	490	/Record tr info for mca hander use!/
	491	if (i > per_cpu(ia64_tr_used, cpu))
	492	per_cpu(ia64_tr_used, cpu) = i;
	493
	494	psr = ia64_clear_ic();
	495	if (target_mask & 0x1) {
	496	ia64_itr(0x1, i, va, pte, log_size);
	497	ia64_srlz_i();
6c57a332	498	p = ia64_idtrs[cpu] + i;
96651896 XZ	499	p->ifa = va;
	500	p->pte = pte;
	501	p->itir = log_size << 2;
	502	p->rr = ia64_get_rr(va);
	503	}
	504	if (target_mask & 0x2) {
	505	ia64_itr(0x2, i, va, pte, log_size);
	506	ia64_srlz_i();
6c57a332	507	p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i;
96651896 XZ	508	p->ifa = va;
	509	p->pte = pte;
	510	p->itir = log_size << 2;
	511	p->rr = ia64_get_rr(va);
	512	}
	513	ia64_set_psr(psr);
	514	r = i;
	515	out:
	516	return r;
	517	}
	518	EXPORT_SYMBOL_GPL(ia64_itr_entry);
	519
	520	/*
	521	* ia64_purge_tr
	522	*
	523	* target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
	524	* slot: slot number to be freed.
	525	*
	526	* Must be called with preemption disabled.
	527	*/
	528	void ia64_ptr_entry(u64 target_mask, int slot)
	529	{
	530	int cpu = smp_processor_id();
	531	int i;
	532	struct ia64_tr_entry *p;
	533
	534	if (slot < IA64_TR_ALLOC_BASE \|\| slot >= per_cpu(ia64_tr_num, cpu))
	535	return;
	536
	537	if (target_mask & 0x1) {
6c57a332	538	p = ia64_idtrs[cpu] + slot;
96651896 XZ	539	if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
	540	p->pte = 0;
	541	ia64_ptr(0x1, p->ifa, p->itir>>2);
	542	ia64_srlz_i();
	543	}
	544	}
	545
	546	if (target_mask & 0x2) {
6c57a332	547	p = ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + slot;
96651896 XZ	548	if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
	549	p->pte = 0;
	550	ia64_ptr(0x2, p->ifa, p->itir>>2);
	551	ia64_srlz_i();
	552	}
	553	}
	554
	555	for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
6c57a332 TL	556	if (((ia64_idtrs[cpu] + i)->pte & 0x1) \|\|
6c57a332 TL	557	((ia64_idtrs[cpu] + IA64_TR_ALLOC_MAX + i)->pte & 0x1))
96651896 XZ	558	break;
	559	}
	560	per_cpu(ia64_tr_used, cpu) = i;
1da177e4	561	}
96651896	562	EXPORT_SYMBOL_GPL(ia64_ptr_entry);