[net-next-2.6.git] / arch / ia64 / mm / tlb.c

/*
 * TLB support routines.
 *
 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
 *	David Mosberger-Tang <davidm@hpl.hp.com>
 *
 * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
 *		Modified RID allocation for SMP
 *          Goutham Rao <goutham.rao@intel.com>
 *              IPI based ptc implementation and A-step IPI implementation.
 * Rohit Seth <rohit.seth@intel.com>
 * Ken Chen <kenneth.w.chen@intel.com>
 * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
 * Copyright (C) 2007 Intel Corp
 *	Fenghua Yu <fenghua.yu@intel.com>
 *	Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
#include <linux/bootmem.h>

#include <asm/delay.h>
#include <asm/mmu_context.h>
#include <asm/pgalloc.h>
#include <asm/pal.h>
#include <asm/tlbflush.h>
#include <asm/dma.h>
#include <asm/processor.h>
#include <asm/sal.h>
#include <asm/tlb.h>

static struct {
	u64 mask;		/* mask of supported purge page-sizes */
	unsigned long max_bits;	/* log2 of largest supported purge page-size */
} purge;

struct ia64_ctx ia64_ctx = {
	.lock =	__SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
	.next =	1,
	.max_ctx = ~0U
};

DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/

struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];

/*
 * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
 * Called after cpu_init() has setup ia64_ctx.max_ctx based on
 * maximum RID that is supported by boot CPU.
 */
void __init
mmu_context_init (void)
{
	ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
}

/*
 * Acquire the ia64_ctx.lock before calling this function!
 */
void
wrap_mmu_context (struct mm_struct *mm)
{
	int i, cpu;
	unsigned long flush_bit;

	for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
		flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
		ia64_ctx.bitmap[i] ^= flush_bit;
	}
 
	/* use offset at 300 to skip daemons */
	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
				ia64_ctx.max_ctx, 300);
	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
				ia64_ctx.max_ctx, ia64_ctx.next);

	/*
	 * can't call flush_tlb_all() here because of race condition
	 * with O(1) scheduler [EF]
	 */
	cpu = get_cpu(); /* prevent preemption/migration */
	for_each_online_cpu(i)
		if (i != cpu)
			per_cpu(ia64_need_tlb_flush, i) = 1;
	put_cpu();
	local_flush_tlb_all();
}

/*
 * Implement "spinaphores" ... like counting semaphores, but they
 * spin instead of sleeping.  If there are ever any other users for
 * this primitive it can be moved up to a spinaphore.h header.
 */
struct spinaphore {
	unsigned long	ticket;
	unsigned long	serve;
};

static inline void spinaphore_init(struct spinaphore *ss, int val)
{
	ss->ticket = 0;
	ss->serve = val;
}

static inline void down_spin(struct spinaphore *ss)
{
	unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;

	if (time_before(t, ss->serve))
		return;

	ia64_invala();

	for (;;) {
		asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
		if (time_before(t, serve))
			return;
		cpu_relax();
	}
}

static inline void up_spin(struct spinaphore *ss)
{
	ia64_fetchadd(1, &ss->serve, rel);
}

static struct spinaphore ptcg_sem;
static u16 nptcg = 1;
static int need_ptcg_sem = 1;
static int toolatetochangeptcgsem = 0;

/*
 * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
 * purges which is reported from either PAL or SAL PALO.
 *
 * We don't have sanity checking for nptcg value. It's the user's responsibility
 * for valid nptcg value on the platform. Otherwise, kernel may hang in some
 * cases.
 */
static int __init
set_nptcg(char *str)
{
	int value = 0;

	get_option(&str, &value);
	setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);

	return 1;
}

__setup("nptcg=", set_nptcg);

/*
 * Maximum number of simultaneous ptc.g purges in the system can
 * be defined by PAL_VM_SUMMARY (in which case we should take
 * the smallest value for any cpu in the system) or by the PAL
 * override table (in which case we should ignore the value from
 * PAL_VM_SUMMARY).
 *
 * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
 * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
 * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
 *
 * Complicating the logic here is the fact that num_possible_cpus()
 * isn't fully setup until we start bringing cpus online.
 */
void
setup_ptcg_sem(int max_purges, int nptcg_from)
{
	static int kp_override;
	static int palo_override;
	static int firstcpu = 1;

	if (toolatetochangeptcgsem) {
		if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
			BUG_ON(1 < nptcg);
		else
			BUG_ON(max_purges < nptcg);
		return;
	}

	if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
		kp_override = 1;
		nptcg = max_purges;
		goto resetsema;
	}
	if (kp_override) {
		need_ptcg_sem = num_possible_cpus() > nptcg;
		return;
	}

	if (nptcg_from == NPTCG_FROM_PALO) {
		palo_override = 1;

		/* In PALO max_purges == 0 really means it! */
		if (max_purges == 0)
			panic("Whoa! Platform does not support global TLB purges.\n");
		nptcg = max_purges;
		if (nptcg == PALO_MAX_TLB_PURGES) {
			need_ptcg_sem = 0;
			return;
		}
		goto resetsema;
	}
	if (palo_override) {
		if (nptcg != PALO_MAX_TLB_PURGES)
			need_ptcg_sem = (num_possible_cpus() > nptcg);
		return;
	}

	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
	if (max_purges == 0) max_purges = 1;

	if (firstcpu) {
		nptcg = max_purges;
		firstcpu = 0;
	}
	if (max_purges < nptcg)
		nptcg = max_purges;
	if (nptcg == PAL_MAX_PURGES) {
		need_ptcg_sem = 0;
		return;
	} else
		need_ptcg_sem = (num_possible_cpus() > nptcg);

resetsema:
	spinaphore_init(&ptcg_sem, max_purges);
}

void
ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
		       unsigned long end, unsigned long nbits)
{
	struct mm_struct *active_mm = current->active_mm;

	toolatetochangeptcgsem = 1;

	if (mm != active_mm) {
		/* Restore region IDs for mm */
		if (mm && active_mm) {
			activate_context(mm);
		} else {
			flush_tlb_all();
			return;
		}
	}

	if (need_ptcg_sem)
		down_spin(&ptcg_sem);

	do {
		/*
		 * Flush ALAT entries also.
		 */
		ia64_ptcga(start, (nbits << 2));
		ia64_srlz_i();
		start += (1UL << nbits);
	} while (start < end);

	if (need_ptcg_sem)
		up_spin(&ptcg_sem);

        if (mm != active_mm) {
                activate_context(active_mm);
        }
}

void
local_flush_tlb_all (void)
{
	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;

	addr    = local_cpu_data->ptce_base;
	count0  = local_cpu_data->ptce_count[0];
	count1  = local_cpu_data->ptce_count[1];
	stride0 = local_cpu_data->ptce_stride[0];
	stride1 = local_cpu_data->ptce_stride[1];

	local_irq_save(flags);
	for (i = 0; i < count0; ++i) {
		for (j = 0; j < count1; ++j) {
			ia64_ptce(addr);
			addr += stride1;
		}
		addr += stride0;
	}
	local_irq_restore(flags);
	ia64_srlz_i();			/* srlz.i implies srlz.d */
}

void
flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
		 unsigned long end)
{
	struct mm_struct *mm = vma->vm_mm;
	unsigned long size = end - start;
	unsigned long nbits;

#ifndef CONFIG_SMP
	if (mm != current->active_mm) {
		mm->context = 0;
		return;
	}
#endif

	nbits = ia64_fls(size + 0xfff);
	while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
			(nbits < purge.max_bits))
		++nbits;
	if (nbits > purge.max_bits)
		nbits = purge.max_bits;
	start &= ~((1UL << nbits) - 1);

	preempt_disable();
#ifdef CONFIG_SMP
	if (mm != current->active_mm || cpumask_weight(mm_cpumask(mm)) != 1) {
		platform_global_tlb_purge(mm, start, end, nbits);
		preempt_enable();
		return;
	}
#endif
	do {
		ia64_ptcl(start, (nbits<<2));
		start += (1UL << nbits);
	} while (start < end);
	preempt_enable();
	ia64_srlz_i();			/* srlz.i implies srlz.d */
}
EXPORT_SYMBOL(flush_tlb_range);

void __devinit
ia64_tlb_init (void)
{
	ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
	u64 tr_pgbits;
	long status;
	pal_vm_info_1_u_t vm_info_1;
	pal_vm_info_2_u_t vm_info_2;
	int cpu = smp_processor_id();

	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
		       "defaulting to architected purge page-sizes.\n", status);
		purge.mask = 0x115557000UL;
	}
	purge.max_bits = ia64_fls(purge.mask);

	ia64_get_ptce(&ptce_info);
	local_cpu_data->ptce_base = ptce_info.base;
	local_cpu_data->ptce_count[0] = ptce_info.count[0];
	local_cpu_data->ptce_count[1] = ptce_info.count[1];
	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];

	local_flush_tlb_all();	/* nuke left overs from bootstrapping... */
	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);

	if (status) {
		printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
		per_cpu(ia64_tr_num, cpu) = 8;
		return;
	}
	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
	if (per_cpu(ia64_tr_num, cpu) >
				(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
		per_cpu(ia64_tr_num, cpu) =
				vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
	if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
		static int justonce = 1;
		per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
		if (justonce) {
			justonce = 0;
			printk(KERN_DEBUG "TR register number exceeds "
			       "IA64_TR_ALLOC_MAX!\n");
		}
	}
}

/*
 * is_tr_overlap
 *
 * Check overlap with inserted TRs.
 */
static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
{
	u64 tr_log_size;
	u64 tr_end;
	u64 va_rr = ia64_get_rr(va);
	u64 va_rid = RR_TO_RID(va_rr);
	u64 va_end = va + (1<<log_size) - 1;

	if (va_rid != RR_TO_RID(p->rr))
		return 0;
	tr_log_size = (p->itir & 0xff) >> 2;
	tr_end = p->ifa + (1<<tr_log_size) - 1;

	if (va > tr_end || p->ifa > va_end)
		return 0;
	return 1;

}

/*
 * ia64_insert_tr in virtual mode. Allocate a TR slot
 *
 * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
 *
 * va 	: virtual address.
 * pte 	: pte entries inserted.
 * log_size: range to be covered.
 *
 * Return value:  <0 :  error No.
 *
 *		  >=0 : slot number allocated for TR.
 * Must be called with preemption disabled.
 */
int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
{
	int i, r;
	unsigned long psr;
	struct ia64_tr_entry *p;
	int cpu = smp_processor_id();

	r = -EINVAL;
	/*Check overlap with existing TR entries*/
	if (target_mask & 0x1) {
		p = &__per_cpu_idtrs[cpu][0][0];
		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
								i++, p++) {
			if (p->pte & 0x1)
				if (is_tr_overlap(p, va, log_size)) {
					printk(KERN_DEBUG "Overlapped Entry"
						"Inserted for TR Reigster!!\n");
					goto out;
			}
		}
	}
	if (target_mask & 0x2) {
		p = &__per_cpu_idtrs[cpu][1][0];
		for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
								i++, p++) {
			if (p->pte & 0x1)
				if (is_tr_overlap(p, va, log_size)) {
					printk(KERN_DEBUG "Overlapped Entry"
						"Inserted for TR Reigster!!\n");
					goto out;
				}
		}
	}

	for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
		switch (target_mask & 0x3) {
		case 1:
			if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1))
				goto found;
			continue;
		case 2:
			if (!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
				goto found;
			continue;
		case 3:
			if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1) &&
				!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
				goto found;
			continue;
		default:
			r = -EINVAL;
			goto out;
		}
	}
found:
	if (i >= per_cpu(ia64_tr_num, cpu))
		return -EBUSY;

	/*Record tr info for mca hander use!*/
	if (i > per_cpu(ia64_tr_used, cpu))
		per_cpu(ia64_tr_used, cpu) = i;

	psr = ia64_clear_ic();
	if (target_mask & 0x1) {
		ia64_itr(0x1, i, va, pte, log_size);
		ia64_srlz_i();
		p = &__per_cpu_idtrs[cpu][0][i];
		p->ifa = va;
		p->pte = pte;
		p->itir = log_size << 2;
		p->rr = ia64_get_rr(va);
	}
	if (target_mask & 0x2) {
		ia64_itr(0x2, i, va, pte, log_size);
		ia64_srlz_i();
		p = &__per_cpu_idtrs[cpu][1][i];
		p->ifa = va;
		p->pte = pte;
		p->itir = log_size << 2;
		p->rr = ia64_get_rr(va);
	}
	ia64_set_psr(psr);
	r = i;
out:
	return r;
}
EXPORT_SYMBOL_GPL(ia64_itr_entry);

/*
 * ia64_purge_tr
 *
 * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
 * slot: slot number to be freed.
 *
 * Must be called with preemption disabled.
 */
void ia64_ptr_entry(u64 target_mask, int slot)
{
	int cpu = smp_processor_id();
	int i;
	struct ia64_tr_entry *p;

	if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
		return;

	if (target_mask & 0x1) {
		p = &__per_cpu_idtrs[cpu][0][slot];
		if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
			p->pte = 0;
			ia64_ptr(0x1, p->ifa, p->itir>>2);
			ia64_srlz_i();
		}
	}

	if (target_mask & 0x2) {
		p = &__per_cpu_idtrs[cpu][1][slot];
		if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
			p->pte = 0;
			ia64_ptr(0x2, p->ifa, p->itir>>2);
			ia64_srlz_i();
		}
	}

	for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
		if ((__per_cpu_idtrs[cpu][0][i].pte & 0x1) ||
				(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
			break;
	}
	per_cpu(ia64_tr_used, cpu) = i;
}
EXPORT_SYMBOL_GPL(ia64_ptr_entry);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* TLB support routines.
	3	*
	4	* Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
	5	* David Mosberger-Tang <davidm@hpl.hp.com>
	6	*
	7	* 08/02/00 A. Mallick <asit.k.mallick@intel.com>
	8	* Modified RID allocation for SMP
	9	* Goutham Rao <goutham.rao@intel.com>
	10	* IPI based ptc implementation and A-step IPI implementation.
dcc17d1b PK	11	* Rohit Seth <rohit.seth@intel.com>
dcc17d1b PK	12	* Ken Chen <kenneth.w.chen@intel.com>
aec103bf	13	* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
2046b94e FY	14	* Copyright (C) 2007 Intel Corp
	15	* Fenghua Yu <fenghua.yu@intel.com>
	16	* Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
1da177e4	17	*/
1da177e4 LT	18	#include <linux/module.h>
	19	#include <linux/init.h>
	20	#include <linux/kernel.h>
	21	#include <linux/sched.h>
	22	#include <linux/smp.h>
	23	#include <linux/mm.h>
dcc17d1b	24	#include <linux/bootmem.h>
1da177e4 LT	25
	26	#include <asm/delay.h>
	27	#include <asm/mmu_context.h>
	28	#include <asm/pgalloc.h>
	29	#include <asm/pal.h>
	30	#include <asm/tlbflush.h>
dcc17d1b	31	#include <asm/dma.h>
96651896	32	#include <asm/processor.h>
2046b94e	33	#include <asm/sal.h>
96651896	34	#include <asm/tlb.h>
1da177e4 LT	35
1da177e4 LT	36	static struct {
e088a4ad	37	u64 mask; /* mask of supported purge page-sizes */
58cd9082	38	unsigned long max_bits; /* log2 of largest supported purge page-size */
1da177e4 LT	39	} purge;
	40
	41	struct ia64_ctx ia64_ctx = {
8737d595 MAC	42	.lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
	43	.next = 1,
	44	.max_ctx = ~0U
1da177e4 LT	45	};
	46
	47	DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
96651896 XZ	48	DEFINE_PER_CPU(u8, ia64_tr_num); /Number of TR slots in current processor/
	49	DEFINE_PER_CPU(u8, ia64_tr_used); /Max Slot number used by kernel/
	50
	51	struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
1da177e4	52
dcc17d1b PK	53	/*
	54	* Initializes the ia64_ctx.bitmap array based on max_ctx+1.
	55	* Called after cpu_init() has setup ia64_ctx.max_ctx based on
	56	* maximum RID that is supported by boot CPU.
	57	*/
	58	void __init
	59	mmu_context_init (void)
	60	{
	61	ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	62	ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
	63	}
	64
1da177e4 LT	65	/*
	66	* Acquire the ia64_ctx.lock before calling this function!
	67	*/
	68	void
	69	wrap_mmu_context (struct mm_struct *mm)
	70	{
58cd9082	71	int i, cpu;
dcc17d1b	72	unsigned long flush_bit;
1da177e4	73
dcc17d1b PK	74	for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
	75	flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
	76	ia64_ctx.bitmap[i] ^= flush_bit;
1da177e4	77	}
dcc17d1b PK	78
	79	/* use offset at 300 to skip daemons */
	80	ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
	81	ia64_ctx.max_ctx, 300);
	82	ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
	83	ia64_ctx.max_ctx, ia64_ctx.next);
	84
58cd9082 KC	85	/*
	86	* can't call flush_tlb_all() here because of race condition
	87	* with O(1) scheduler [EF]
	88	*/
	89	cpu = get_cpu(); /* prevent preemption/migration */
	90	for_each_online_cpu(i)
	91	if (i != cpu)
	92	per_cpu(ia64_need_tlb_flush, i) = 1;
	93	put_cpu();
1da177e4 LT	94	local_flush_tlb_all();
	95	}
	96
2046b94e FY	97	/*
	98	* Implement "spinaphores" ... like counting semaphores, but they
	99	* spin instead of sleeping. If there are ever any other users for
	100	* this primitive it can be moved up to a spinaphore.h header.
	101	*/
	102	struct spinaphore {
883a3acf TL	103	unsigned long ticket;
883a3acf TL	104	unsigned long serve;
2046b94e FY	105	};
	106
	107	static inline void spinaphore_init(struct spinaphore *ss, int val)
	108	{
883a3acf TL	109	ss->ticket = 0;
883a3acf TL	110	ss->serve = val;
2046b94e FY	111	}
	112
	113	static inline void down_spin(struct spinaphore *ss)
	114	{
883a3acf TL	115	unsigned long t = ia64_fetchadd(1, &ss->ticket, acq), serve;
	116
	117	if (time_before(t, ss->serve))
	118	return;
	119
	120	ia64_invala();
	121
	122	for (;;) {
	123	asm volatile ("ld4.c.nc %0=[%1]" : "=r"(serve) : "r"(&ss->serve) : "memory");
	124	if (time_before(t, serve))
	125	return;
	126	cpu_relax();
	127	}
2046b94e FY	128	}
	129
	130	static inline void up_spin(struct spinaphore *ss)
	131	{
883a3acf	132	ia64_fetchadd(1, &ss->serve, rel);
2046b94e FY	133	}
	134
	135	static struct spinaphore ptcg_sem;
	136	static u16 nptcg = 1;
	137	static int need_ptcg_sem = 1;
	138	static int toolatetochangeptcgsem = 0;
	139
a6c75b86 FY	140	/*
	141	* Kernel parameter "nptcg=" overrides max number of concurrent global TLB
	142	* purges which is reported from either PAL or SAL PALO.
	143	*
	144	* We don't have sanity checking for nptcg value. It's the user's responsibility
	145	* for valid nptcg value on the platform. Otherwise, kernel may hang in some
	146	* cases.
	147	*/
	148	static int __init
	149	set_nptcg(char *str)
	150	{
	151	int value = 0;
	152
	153	get_option(&str, &value);
	154	setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
	155
	156	return 1;
	157	}
	158
	159	__setup("nptcg=", set_nptcg);
	160
2046b94e FY	161	/*
	162	* Maximum number of simultaneous ptc.g purges in the system can
	163	* be defined by PAL_VM_SUMMARY (in which case we should take
	164	* the smallest value for any cpu in the system) or by the PAL
	165	* override table (in which case we should ignore the value from
	166	* PAL_VM_SUMMARY).
	167	*
a6c75b86 FY	168	* Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
	169	* purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
	170	* we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
	171	*
2046b94e FY	172	* Complicating the logic here is the fact that num_possible_cpus()
	173	* isn't fully setup until we start bringing cpus online.
	174	*/
	175	void
a6c75b86	176	setup_ptcg_sem(int max_purges, int nptcg_from)
2046b94e	177	{
a6c75b86 FY	178	static int kp_override;
a6c75b86 FY	179	static int palo_override;
2046b94e FY	180	static int firstcpu = 1;
	181
	182	if (toolatetochangeptcgsem) {
e617fce6 HS	183	if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
	184	BUG_ON(1 < nptcg);
	185	else
	186	BUG_ON(max_purges < nptcg);
2046b94e FY	187	return;
	188	}
	189
a6c75b86 FY	190	if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
	191	kp_override = 1;
	192	nptcg = max_purges;
	193	goto resetsema;
	194	}
	195	if (kp_override) {
	196	need_ptcg_sem = num_possible_cpus() > nptcg;
	197	return;
	198	}
	199
	200	if (nptcg_from == NPTCG_FROM_PALO) {
	201	palo_override = 1;
2046b94e FY	202
	203	/* In PALO max_purges == 0 really means it! */
	204	if (max_purges == 0)
	205	panic("Whoa! Platform does not support global TLB purges.\n");
	206	nptcg = max_purges;
	207	if (nptcg == PALO_MAX_TLB_PURGES) {
	208	need_ptcg_sem = 0;
	209	return;
	210	}
	211	goto resetsema;
	212	}
a6c75b86	213	if (palo_override) {
2046b94e FY	214	if (nptcg != PALO_MAX_TLB_PURGES)
	215	need_ptcg_sem = (num_possible_cpus() > nptcg);
	216	return;
	217	}
	218
	219	/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
	220	if (max_purges == 0) max_purges = 1;
	221
	222	if (firstcpu) {
	223	nptcg = max_purges;
	224	firstcpu = 0;
	225	}
	226	if (max_purges < nptcg)
	227	nptcg = max_purges;
	228	if (nptcg == PAL_MAX_PURGES) {
	229	need_ptcg_sem = 0;
	230	return;
	231	} else
	232	need_ptcg_sem = (num_possible_cpus() > nptcg);
	233
	234	resetsema:
	235	spinaphore_init(&ptcg_sem, max_purges);
	236	}
	237
1da177e4	238	void
58cd9082 KC	239	ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
58cd9082 KC	240	unsigned long end, unsigned long nbits)
1da177e4	241	{
aec103bf DCIV	242	struct mm_struct *active_mm = current->active_mm;
aec103bf DCIV	243
2046b94e FY	244	toolatetochangeptcgsem = 1;
2046b94e FY	245
aec103bf DCIV	246	if (mm != active_mm) {
	247	/* Restore region IDs for mm */
	248	if (mm && active_mm) {
	249	activate_context(mm);
	250	} else {
	251	flush_tlb_all();
	252	return;
	253	}
c1902aae DR	254	}
c1902aae DR	255
2046b94e FY	256	if (need_ptcg_sem)
	257	down_spin(&ptcg_sem);
	258
	259	do {
	260	/*
	261	* Flush ALAT entries also.
	262	*/
	263	ia64_ptcga(start, (nbits << 2));
	264	ia64_srlz_i();
	265	start += (1UL << nbits);
	266	} while (start < end);
	267
	268	if (need_ptcg_sem)
	269	up_spin(&ptcg_sem);
aec103bf DCIV	270
	271	if (mm != active_mm) {
	272	activate_context(active_mm);
	273	}
1da177e4 LT	274	}
	275
	276	void
	277	local_flush_tlb_all (void)
	278	{
	279	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
	280
	281	addr = local_cpu_data->ptce_base;
	282	count0 = local_cpu_data->ptce_count[0];
	283	count1 = local_cpu_data->ptce_count[1];
	284	stride0 = local_cpu_data->ptce_stride[0];
	285	stride1 = local_cpu_data->ptce_stride[1];
	286
	287	local_irq_save(flags);
	288	for (i = 0; i < count0; ++i) {
	289	for (j = 0; j < count1; ++j) {
	290	ia64_ptce(addr);
	291	addr += stride1;
	292	}
	293	addr += stride0;
	294	}
	295	local_irq_restore(flags);
	296	ia64_srlz_i(); /* srlz.i implies srlz.d */
	297	}
	298
	299	void
58cd9082 KC	300	flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
58cd9082 KC	301	unsigned long end)
1da177e4 LT	302	{
	303	struct mm_struct *mm = vma->vm_mm;
	304	unsigned long size = end - start;
	305	unsigned long nbits;
	306
c1902aae	307	#ifndef CONFIG_SMP
1da177e4	308	if (mm != current->active_mm) {
1da177e4	309	mm->context = 0;
1da177e4 LT	310	return;
1da177e4 LT	311	}
c1902aae	312	#endif
1da177e4 LT	313
1da177e4 LT	314	nbits = ia64_fls(size + 0xfff);
58cd9082 KC	315	while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
58cd9082 KC	316	(nbits < purge.max_bits))
1da177e4 LT	317	++nbits;
	318	if (nbits > purge.max_bits)
	319	nbits = purge.max_bits;
	320	start &= ~((1UL << nbits) - 1);
	321
663b97f7	322	preempt_disable();
ce9eed5a	323	#ifdef CONFIG_SMP
5d8c39f6	324	if (mm != current->active_mm \|\| cpumask_weight(mm_cpumask(mm)) != 1) {
ce9eed5a KC	325	platform_global_tlb_purge(mm, start, end, nbits);
	326	preempt_enable();
	327	return;
	328	}
	329	#endif
1da177e4 LT	330	do {
	331	ia64_ptcl(start, (nbits<<2));
	332	start += (1UL << nbits);
	333	} while (start < end);
663b97f7	334	preempt_enable();
1da177e4 LT	335	ia64_srlz_i(); /* srlz.i implies srlz.d */
	336	}
	337	EXPORT_SYMBOL(flush_tlb_range);
	338
	339	void __devinit
	340	ia64_tlb_init (void)
	341	{
256a7e09	342	ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
e088a4ad	343	u64 tr_pgbits;
1da177e4	344	long status;
96651896 XZ	345	pal_vm_info_1_u_t vm_info_1;
	346	pal_vm_info_2_u_t vm_info_2;
	347	int cpu = smp_processor_id();
1da177e4 LT	348
1da177e4 LT	349	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
c2eeb321	350	printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
1da177e4 LT	351	"defaulting to architected purge page-sizes.\n", status);
	352	purge.mask = 0x115557000UL;
	353	}
	354	purge.max_bits = ia64_fls(purge.mask);
	355
	356	ia64_get_ptce(&ptce_info);
	357	local_cpu_data->ptce_base = ptce_info.base;
	358	local_cpu_data->ptce_count[0] = ptce_info.count[0];
	359	local_cpu_data->ptce_count[1] = ptce_info.count[1];
	360	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
	361	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
	362
58cd9082	363	local_flush_tlb_all(); /* nuke left overs from bootstrapping... */
96651896 XZ	364	status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
	365
	366	if (status) {
	367	printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
	368	per_cpu(ia64_tr_num, cpu) = 8;
	369	return;
	370	}
	371	per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
	372	if (per_cpu(ia64_tr_num, cpu) >
	373	(vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
	374	per_cpu(ia64_tr_num, cpu) =
	375	vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
	376	if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
a9894a4a	377	static int justonce = 1;
96651896	378	per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
a9894a4a TL	379	if (justonce) {
	380	justonce = 0;
	381	printk(KERN_DEBUG "TR register number exceeds "
	382	"IA64_TR_ALLOC_MAX!\n");
	383	}
96651896 XZ	384	}
	385	}
	386
	387	/*
	388	* is_tr_overlap
	389	*
	390	* Check overlap with inserted TRs.
	391	*/
	392	static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
	393	{
	394	u64 tr_log_size;
	395	u64 tr_end;
	396	u64 va_rr = ia64_get_rr(va);
	397	u64 va_rid = RR_TO_RID(va_rr);
	398	u64 va_end = va + (1<<log_size) - 1;
	399
	400	if (va_rid != RR_TO_RID(p->rr))
	401	return 0;
	402	tr_log_size = (p->itir & 0xff) >> 2;
	403	tr_end = p->ifa + (1<<tr_log_size) - 1;
	404
	405	if (va > tr_end \|\| p->ifa > va_end)
	406	return 0;
	407	return 1;
	408
	409	}
	410
	411	/*
	412	* ia64_insert_tr in virtual mode. Allocate a TR slot
	413	*
	414	* target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
	415	*
	416	* va : virtual address.
	417	* pte : pte entries inserted.
	418	* log_size: range to be covered.
	419	*
	420	* Return value: <0 : error No.
	421	*
	422	* >=0 : slot number allocated for TR.
	423	* Must be called with preemption disabled.
	424	*/
	425	int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
	426	{
	427	int i, r;
	428	unsigned long psr;
	429	struct ia64_tr_entry *p;
	430	int cpu = smp_processor_id();
	431
	432	r = -EINVAL;
	433	/Check overlap with existing TR entries/
	434	if (target_mask & 0x1) {
	435	p = &__per_cpu_idtrs[cpu][0][0];
	436	for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
	437	i++, p++) {
	438	if (p->pte & 0x1)
	439	if (is_tr_overlap(p, va, log_size)) {
	440	printk(KERN_DEBUG "Overlapped Entry"
	441	"Inserted for TR Reigster!!\n");
	442	goto out;
	443	}
	444	}
	445	}
	446	if (target_mask & 0x2) {
	447	p = &__per_cpu_idtrs[cpu][1][0];
448	for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
449	i++, p++) {
450	if (p->pte & 0x1)
451	if (is_tr_overlap(p, va, log_size)) {
452	printk(KERN_DEBUG "Overlapped Entry"
453	"Inserted for TR Reigster!!\n");
454	goto out;
455	}
456	}
457	}
458
459	for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
460	switch (target_mask & 0x3) {
461	case 1:
462	if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1))
463	goto found;
464	continue;
465	case 2:
466	if (!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
467	goto found;
468	continue;
469	case 3:
470	if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1) &&
471	!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
472	goto found;
473	continue;
474	default:
475	r = -EINVAL;
476	goto out;
477	}
478	}
479	found:
480	if (i >= per_cpu(ia64_tr_num, cpu))
481	return -EBUSY;
482
483	/Record tr info for mca hander use!/
484	if (i > per_cpu(ia64_tr_used, cpu))
485	per_cpu(ia64_tr_used, cpu) = i;
486
487	psr = ia64_clear_ic();
488	if (target_mask & 0x1) {
489	ia64_itr(0x1, i, va, pte, log_size);
490	ia64_srlz_i();
491	p = &__per_cpu_idtrs[cpu][0][i];
492	p->ifa = va;
493	p->pte = pte;
494	p->itir = log_size << 2;
495	p->rr = ia64_get_rr(va);
496	}
497	if (target_mask & 0x2) {
498	ia64_itr(0x2, i, va, pte, log_size);
499	ia64_srlz_i();
500	p = &__per_cpu_idtrs[cpu][1][i];
501	p->ifa = va;
502	p->pte = pte;
503	p->itir = log_size << 2;
504	p->rr = ia64_get_rr(va);
505	}
506	ia64_set_psr(psr);
507	r = i;
508	out:
509	return r;
510	}
511	EXPORT_SYMBOL_GPL(ia64_itr_entry);
512
513	/*
514	* ia64_purge_tr
515	*
516	* target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
517	* slot: slot number to be freed.
518	*
519	* Must be called with preemption disabled.
520	*/
521	void ia64_ptr_entry(u64 target_mask, int slot)
522	{
523	int cpu = smp_processor_id();
524	int i;
525	struct ia64_tr_entry *p;
526
527	if (slot < IA64_TR_ALLOC_BASE \|\| slot >= per_cpu(ia64_tr_num, cpu))
528	return;
529
530	if (target_mask & 0x1) {
531	p = &__per_cpu_idtrs[cpu][0][slot];
532	if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
533	p->pte = 0;
534	ia64_ptr(0x1, p->ifa, p->itir>>2);
535	ia64_srlz_i();
536	}
537	}
538
539	if (target_mask & 0x2) {
540	p = &__per_cpu_idtrs[cpu][1][slot];
541	if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
542	p->pte = 0;
543	ia64_ptr(0x2, p->ifa, p->itir>>2);
544	ia64_srlz_i();
545	}
546	}
547
548	for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
549	if ((__per_cpu_idtrs[cpu][0][i].pte & 0x1) \|\|
550	(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
551	break;
552	}
553	per_cpu(ia64_tr_used, cpu) = i;
1da177e4	554	}
96651896	555	EXPORT_SYMBOL_GPL(ia64_ptr_entry);