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[IA64] Fix - Section mismatch: reference to .init.data:mvec_name
[net-next-2.6.git] / arch / ia64 / hp / common / hwsw_iommu.c
CommitLineData
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1/*
2 * Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
3 * Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
4 *
5 * This is a pseudo I/O MMU which dispatches to the hardware I/O MMU
6 * whenever possible. We assume that the hardware I/O MMU requires
7 * full 32-bit addressability, as is the case, e.g., for HP zx1-based
8 * systems (there, the I/O MMU window is mapped at 3-4GB). If a
9 * device doesn't provide full 32-bit addressability, we fall back on
10 * the sw I/O TLB. This is good enough to let us support broken
11 * hardware such as soundcards which have a DMA engine that can
12 * address only 28 bits.
13 */
14
15#include <linux/device.h>
16
17#include <asm/machvec.h>
18
19/* swiotlb declarations & definitions: */
0b9afede 20extern int swiotlb_late_init_with_default_size (size_t size);
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21extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent;
22extern ia64_mv_dma_free_coherent swiotlb_free_coherent;
23extern ia64_mv_dma_map_single swiotlb_map_single;
24extern ia64_mv_dma_unmap_single swiotlb_unmap_single;
25extern ia64_mv_dma_map_sg swiotlb_map_sg;
26extern ia64_mv_dma_unmap_sg swiotlb_unmap_sg;
27extern ia64_mv_dma_supported swiotlb_dma_supported;
28extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error;
29
30/* hwiommu declarations & definitions: */
31
32extern ia64_mv_dma_alloc_coherent sba_alloc_coherent;
33extern ia64_mv_dma_free_coherent sba_free_coherent;
34extern ia64_mv_dma_map_single sba_map_single;
35extern ia64_mv_dma_unmap_single sba_unmap_single;
36extern ia64_mv_dma_map_sg sba_map_sg;
37extern ia64_mv_dma_unmap_sg sba_unmap_sg;
38extern ia64_mv_dma_supported sba_dma_supported;
39extern ia64_mv_dma_mapping_error sba_dma_mapping_error;
40
41#define hwiommu_alloc_coherent sba_alloc_coherent
42#define hwiommu_free_coherent sba_free_coherent
43#define hwiommu_map_single sba_map_single
44#define hwiommu_unmap_single sba_unmap_single
45#define hwiommu_map_sg sba_map_sg
46#define hwiommu_unmap_sg sba_unmap_sg
47#define hwiommu_dma_supported sba_dma_supported
48#define hwiommu_dma_mapping_error sba_dma_mapping_error
49#define hwiommu_sync_single_for_cpu machvec_dma_sync_single
50#define hwiommu_sync_sg_for_cpu machvec_dma_sync_sg
51#define hwiommu_sync_single_for_device machvec_dma_sync_single
52#define hwiommu_sync_sg_for_device machvec_dma_sync_sg
53
54
55/*
56 * Note: we need to make the determination of whether or not to use
57 * the sw I/O TLB based purely on the device structure. Anything else
58 * would be unreliable or would be too intrusive.
59 */
60static inline int
61use_swiotlb (struct device *dev)
62{
63 return dev && dev->dma_mask && !hwiommu_dma_supported(dev, *dev->dma_mask);
64}
65
9a86bbb9 66void __init
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67hwsw_init (void)
68{
69 /* default to a smallish 2MB sw I/O TLB */
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70 if (swiotlb_late_init_with_default_size (2 * (1<<20)) != 0) {
71#ifdef CONFIG_IA64_GENERIC
72 /* Better to have normal DMA than panic */
73 printk(KERN_WARNING "%s: Failed to initialize software I/O TLB,"
74 " reverting to hpzx1 platform vector\n", __FUNCTION__);
75 machvec_init("hpzx1");
76#else
77 panic("Unable to initialize software I/O TLB services");
78#endif
79 }
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80}
81
82void *
06a54497 83hwsw_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags)
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84{
85 if (use_swiotlb(dev))
86 return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
87 else
88 return hwiommu_alloc_coherent(dev, size, dma_handle, flags);
89}
90
91void
92hwsw_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
93{
94 if (use_swiotlb(dev))
95 swiotlb_free_coherent(dev, size, vaddr, dma_handle);
96 else
97 hwiommu_free_coherent(dev, size, vaddr, dma_handle);
98}
99
100dma_addr_t
101hwsw_map_single (struct device *dev, void *addr, size_t size, int dir)
102{
103 if (use_swiotlb(dev))
104 return swiotlb_map_single(dev, addr, size, dir);
105 else
106 return hwiommu_map_single(dev, addr, size, dir);
107}
108
109void
110hwsw_unmap_single (struct device *dev, dma_addr_t iova, size_t size, int dir)
111{
112 if (use_swiotlb(dev))
113 return swiotlb_unmap_single(dev, iova, size, dir);
114 else
115 return hwiommu_unmap_single(dev, iova, size, dir);
116}
117
118
119int
120hwsw_map_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
121{
122 if (use_swiotlb(dev))
123 return swiotlb_map_sg(dev, sglist, nents, dir);
124 else
125 return hwiommu_map_sg(dev, sglist, nents, dir);
126}
127
128void
129hwsw_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
130{
131 if (use_swiotlb(dev))
132 return swiotlb_unmap_sg(dev, sglist, nents, dir);
133 else
134 return hwiommu_unmap_sg(dev, sglist, nents, dir);
135}
136
137void
138hwsw_sync_single_for_cpu (struct device *dev, dma_addr_t addr, size_t size, int dir)
139{
140 if (use_swiotlb(dev))
141 swiotlb_sync_single_for_cpu(dev, addr, size, dir);
142 else
143 hwiommu_sync_single_for_cpu(dev, addr, size, dir);
144}
145
146void
147hwsw_sync_sg_for_cpu (struct device *dev, struct scatterlist *sg, int nelems, int dir)
148{
149 if (use_swiotlb(dev))
150 swiotlb_sync_sg_for_cpu(dev, sg, nelems, dir);
151 else
152 hwiommu_sync_sg_for_cpu(dev, sg, nelems, dir);
153}
154
155void
156hwsw_sync_single_for_device (struct device *dev, dma_addr_t addr, size_t size, int dir)
157{
158 if (use_swiotlb(dev))
159 swiotlb_sync_single_for_device(dev, addr, size, dir);
160 else
161 hwiommu_sync_single_for_device(dev, addr, size, dir);
162}
163
164void
165hwsw_sync_sg_for_device (struct device *dev, struct scatterlist *sg, int nelems, int dir)
166{
167 if (use_swiotlb(dev))
168 swiotlb_sync_sg_for_device(dev, sg, nelems, dir);
169 else
170 hwiommu_sync_sg_for_device(dev, sg, nelems, dir);
171}
172
173int
174hwsw_dma_supported (struct device *dev, u64 mask)
175{
176 if (hwiommu_dma_supported(dev, mask))
177 return 1;
178 return swiotlb_dma_supported(dev, mask);
179}
180
181int
182hwsw_dma_mapping_error (dma_addr_t dma_addr)
183{
184 return hwiommu_dma_mapping_error (dma_addr) || swiotlb_dma_mapping_error(dma_addr);
185}
186
187EXPORT_SYMBOL(hwsw_dma_mapping_error);
188EXPORT_SYMBOL(hwsw_map_single);
189EXPORT_SYMBOL(hwsw_unmap_single);
190EXPORT_SYMBOL(hwsw_map_sg);
191EXPORT_SYMBOL(hwsw_unmap_sg);
192EXPORT_SYMBOL(hwsw_dma_supported);
193EXPORT_SYMBOL(hwsw_alloc_coherent);
194EXPORT_SYMBOL(hwsw_free_coherent);
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195EXPORT_SYMBOL(hwsw_sync_single_for_cpu);
196EXPORT_SYMBOL(hwsw_sync_single_for_device);
197EXPORT_SYMBOL(hwsw_sync_sg_for_cpu);
198EXPORT_SYMBOL(hwsw_sync_sg_for_device);