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ab843c79 VY |
1 | /* |
2 | * File: arch/blackfin/mach-bf561/acvilon.c | |
3 | * Based on: arch/blackfin/mach-bf561/ezkit.c | |
4 | * Author: | |
5 | * | |
6 | * Created: | |
7 | * Description: | |
8 | * | |
9 | * Modified: | |
10 | * Copyright 2004-2006 Analog Devices Inc. | |
11 | * Copyright 2009 CJSC "NII STT" | |
12 | * | |
13 | * Bugs: | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation; either version 2 of the License, or | |
18 | * (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, see the file COPYING, or write | |
27 | * to the Free Software Foundation, Inc., | |
28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
29 | * | |
30 | * | |
31 | * For more information about Acvilon BF561 SoM please | |
32 | * go to http://www.niistt.ru/ | |
33 | * | |
34 | */ | |
35 | ||
36 | #include <linux/device.h> | |
37 | #include <linux/platform_device.h> | |
38 | #include <linux/mtd/mtd.h> | |
39 | #include <linux/mtd/partitions.h> | |
40 | #include <linux/mtd/physmap.h> | |
41 | #include <linux/mtd/nand.h> | |
42 | #include <linux/mtd/plat-ram.h> | |
43 | #include <linux/spi/spi.h> | |
44 | #include <linux/spi/flash.h> | |
45 | #include <linux/irq.h> | |
46 | #include <linux/interrupt.h> | |
efc5863e | 47 | #include <linux/jiffies.h> |
ab843c79 VY |
48 | #include <linux/i2c-pca-platform.h> |
49 | #include <linux/delay.h> | |
50 | #include <linux/io.h> | |
51 | #include <asm/dma.h> | |
52 | #include <asm/bfin5xx_spi.h> | |
53 | #include <asm/portmux.h> | |
54 | #include <asm/dpmc.h> | |
55 | #include <asm/cacheflush.h> | |
56 | #include <linux/i2c.h> | |
57 | ||
58 | /* | |
59 | * Name the Board for the /proc/cpuinfo | |
60 | */ | |
61 | const char bfin_board_name[] = "Acvilon board"; | |
62 | ||
63 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | |
64 | #include <linux/usb/isp1760.h> | |
65 | static struct resource bfin_isp1760_resources[] = { | |
66 | [0] = { | |
67 | .start = 0x20000000, | |
68 | .end = 0x20000000 + 0x000fffff, | |
69 | .flags = IORESOURCE_MEM, | |
70 | }, | |
71 | [1] = { | |
72 | .start = IRQ_PF15, | |
73 | .end = IRQ_PF15, | |
74 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
75 | }, | |
76 | }; | |
77 | ||
78 | static struct isp1760_platform_data isp1760_priv = { | |
79 | .is_isp1761 = 0, | |
80 | .port1_disable = 0, | |
81 | .bus_width_16 = 1, | |
82 | .port1_otg = 0, | |
83 | .analog_oc = 0, | |
84 | .dack_polarity_high = 0, | |
85 | .dreq_polarity_high = 0, | |
86 | }; | |
87 | ||
88 | static struct platform_device bfin_isp1760_device = { | |
89 | .name = "isp1760-hcd", | |
90 | .id = 0, | |
91 | .dev = { | |
92 | .platform_data = &isp1760_priv, | |
93 | }, | |
94 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | |
95 | .resource = bfin_isp1760_resources, | |
96 | }; | |
97 | #endif | |
98 | ||
99 | static struct resource bfin_i2c_pca_resources[] = { | |
100 | { | |
101 | .name = "pca9564-regs", | |
102 | .start = 0x2C000000, | |
103 | .end = 0x2C000000 + 16, | |
104 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, | |
105 | }, { | |
106 | ||
107 | .start = IRQ_PF8, | |
108 | .end = IRQ_PF8, | |
109 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
110 | }, | |
111 | }; | |
112 | ||
113 | struct i2c_pca9564_pf_platform_data pca9564_platform_data = { | |
114 | .gpio = -1, | |
115 | .i2c_clock_speed = 330000, | |
efc5863e | 116 | .timeout = HZ, |
ab843c79 VY |
117 | }; |
118 | ||
119 | /* PCA9564 I2C Bus driver */ | |
120 | static struct platform_device bfin_i2c_pca_device = { | |
121 | .name = "i2c-pca-platform", | |
122 | .id = 0, | |
123 | .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources), | |
124 | .resource = bfin_i2c_pca_resources, | |
125 | .dev = { | |
126 | .platform_data = &pca9564_platform_data, | |
127 | } | |
128 | }; | |
129 | ||
130 | /* I2C devices fitted. */ | |
131 | static struct i2c_board_info acvilon_i2c_devs[] __initdata = { | |
132 | { | |
133 | I2C_BOARD_INFO("ds1339", 0x68), | |
134 | }, | |
135 | { | |
136 | I2C_BOARD_INFO("tcn75", 0x49), | |
137 | }, | |
138 | }; | |
139 | ||
140 | #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) | |
141 | static struct platdata_mtd_ram mtd_ram_data = { | |
142 | .mapname = "rootfs(RAM)", | |
143 | .bankwidth = 4, | |
144 | }; | |
145 | ||
146 | static struct resource mtd_ram_resource = { | |
147 | .start = 0x4000000, | |
148 | .end = 0x5ffffff, | |
149 | .flags = IORESOURCE_MEM, | |
150 | }; | |
151 | ||
152 | static struct platform_device mtd_ram_device = { | |
153 | .name = "mtd-ram", | |
154 | .id = 0, | |
155 | .dev = { | |
156 | .platform_data = &mtd_ram_data, | |
157 | }, | |
158 | .num_resources = 1, | |
159 | .resource = &mtd_ram_resource, | |
160 | }; | |
161 | #endif | |
162 | ||
163 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
164 | #include <linux/smsc911x.h> | |
165 | static struct resource smsc911x_resources[] = { | |
166 | { | |
167 | .name = "smsc911x-memory", | |
168 | .start = 0x28000000, | |
169 | .end = 0x28000000 + 0xFF, | |
170 | .flags = IORESOURCE_MEM, | |
171 | }, | |
172 | { | |
173 | .start = IRQ_PF7, | |
174 | .end = IRQ_PF7, | |
175 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static struct smsc911x_platform_config smsc911x_config = { | |
252077cf | 180 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, |
ab843c79 VY |
181 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, |
182 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
183 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
184 | }; | |
185 | ||
186 | static struct platform_device smsc911x_device = { | |
187 | .name = "smsc911x", | |
188 | .id = 0, | |
189 | .num_resources = ARRAY_SIZE(smsc911x_resources), | |
190 | .resource = smsc911x_resources, | |
191 | .dev = { | |
192 | .platform_data = &smsc911x_config, | |
193 | }, | |
194 | }; | |
195 | #endif | |
196 | ||
197 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
198 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
199 | static struct resource bfin_uart0_resources[] = { | |
200 | { | |
201 | .start = BFIN_UART_THR, | |
202 | .end = BFIN_UART_GCTL + 2, | |
203 | .flags = IORESOURCE_MEM, | |
204 | }, | |
205 | { | |
206 | .start = IRQ_UART_RX, | |
207 | .end = IRQ_UART_RX + 1, | |
208 | .flags = IORESOURCE_IRQ, | |
209 | }, | |
210 | { | |
211 | .start = IRQ_UART_ERROR, | |
212 | .end = IRQ_UART_ERROR, | |
213 | .flags = IORESOURCE_IRQ, | |
214 | }, | |
215 | { | |
216 | .start = CH_UART_TX, | |
217 | .end = CH_UART_TX, | |
218 | .flags = IORESOURCE_DMA, | |
219 | }, | |
220 | { | |
221 | .start = CH_UART_RX, | |
222 | .end = CH_UART_RX, | |
223 | .flags = IORESOURCE_DMA, | |
224 | }, | |
225 | }; | |
226 | ||
227 | unsigned short bfin_uart0_peripherals[] = { | |
228 | P_UART0_TX, P_UART0_RX, 0 | |
229 | }; | |
230 | ||
231 | static struct platform_device bfin_uart0_device = { | |
232 | .name = "bfin-uart", | |
233 | .id = 0, | |
234 | .num_resources = ARRAY_SIZE(bfin_uart0_resources), | |
235 | .resource = bfin_uart0_resources, | |
236 | .dev = { | |
237 | /* Passed to driver */ | |
238 | .platform_data = &bfin_uart0_peripherals, | |
239 | }, | |
240 | }; | |
241 | #endif | |
242 | #endif | |
243 | ||
244 | #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
245 | ||
246 | #ifdef CONFIG_MTD_PARTITIONS | |
247 | const char *part_probes[] = { "cmdlinepart", NULL }; | |
248 | ||
249 | static struct mtd_partition bfin_plat_nand_partitions[] = { | |
250 | { | |
251 | .name = "params(nand)", | |
252 | .size = 32 * 1024 * 1024, | |
253 | .offset = 0, | |
254 | }, { | |
255 | .name = "userfs(nand)", | |
256 | .size = MTDPART_SIZ_FULL, | |
257 | .offset = MTDPART_OFS_APPEND, | |
258 | }, | |
259 | }; | |
260 | #endif | |
261 | ||
262 | #define BFIN_NAND_PLAT_CLE 2 | |
263 | #define BFIN_NAND_PLAT_ALE 3 | |
264 | ||
265 | static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | |
266 | unsigned int ctrl) | |
267 | { | |
268 | struct nand_chip *this = mtd->priv; | |
269 | ||
270 | if (cmd == NAND_CMD_NONE) | |
271 | return; | |
272 | ||
273 | if (ctrl & NAND_CLE) | |
274 | writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE)); | |
275 | else | |
276 | writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE)); | |
277 | } | |
278 | ||
279 | #define BFIN_NAND_PLAT_READY GPIO_PF10 | |
280 | static int bfin_plat_nand_dev_ready(struct mtd_info *mtd) | |
281 | { | |
282 | return gpio_get_value(BFIN_NAND_PLAT_READY); | |
283 | } | |
284 | ||
285 | static struct platform_nand_data bfin_plat_nand_data = { | |
286 | .chip = { | |
287 | .chip_delay = 30, | |
288 | #ifdef CONFIG_MTD_PARTITIONS | |
289 | .part_probe_types = part_probes, | |
290 | .partitions = bfin_plat_nand_partitions, | |
291 | .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions), | |
292 | #endif | |
293 | }, | |
294 | .ctrl = { | |
295 | .cmd_ctrl = bfin_plat_nand_cmd_ctrl, | |
296 | .dev_ready = bfin_plat_nand_dev_ready, | |
297 | }, | |
298 | }; | |
299 | ||
300 | #define MAX(x, y) (x > y ? x : y) | |
301 | static struct resource bfin_plat_nand_resources = { | |
302 | .start = 0x24000000, | |
303 | .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)), | |
304 | .flags = IORESOURCE_IO, | |
305 | }; | |
306 | ||
307 | static struct platform_device bfin_async_nand_device = { | |
308 | .name = "gen_nand", | |
309 | .id = -1, | |
310 | .num_resources = 1, | |
311 | .resource = &bfin_plat_nand_resources, | |
312 | .dev = { | |
313 | .platform_data = &bfin_plat_nand_data, | |
314 | }, | |
315 | }; | |
316 | ||
317 | static void bfin_plat_nand_init(void) | |
318 | { | |
319 | gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); | |
320 | } | |
321 | #else | |
322 | static void bfin_plat_nand_init(void) | |
323 | { | |
324 | } | |
325 | #endif | |
326 | ||
327 | #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) | |
328 | static struct mtd_partition bfin_spi_dataflash_partitions[] = { | |
329 | { | |
330 | .name = "bootloader", | |
331 | .size = 0x4200, | |
332 | .offset = 0, | |
333 | .mask_flags = MTD_CAP_ROM}, | |
334 | { | |
335 | .name = "u-boot", | |
336 | .size = 0x42000, | |
337 | .offset = MTDPART_OFS_APPEND, | |
338 | }, | |
339 | { | |
340 | .name = "u-boot(params)", | |
341 | .size = 0x4200, | |
342 | .offset = MTDPART_OFS_APPEND, | |
343 | }, | |
344 | { | |
345 | .name = "kernel", | |
346 | .size = 0x294000, | |
347 | .offset = MTDPART_OFS_APPEND, | |
348 | }, | |
349 | { | |
350 | .name = "params", | |
351 | .size = 0x42000, | |
352 | .offset = MTDPART_OFS_APPEND, | |
353 | }, | |
354 | { | |
355 | .name = "rootfs", | |
356 | .size = MTDPART_SIZ_FULL, | |
357 | .offset = MTDPART_OFS_APPEND, | |
358 | } | |
359 | }; | |
360 | ||
361 | static struct flash_platform_data bfin_spi_dataflash_data = { | |
362 | .name = "SPI Dataflash", | |
363 | .parts = bfin_spi_dataflash_partitions, | |
364 | .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions), | |
365 | }; | |
366 | ||
367 | /* DataFlash chip */ | |
368 | static struct bfin5xx_spi_chip data_flash_chip_info = { | |
369 | .enable_dma = 0, /* use dma transfer with this chip */ | |
370 | .bits_per_word = 8, | |
371 | }; | |
372 | #endif | |
373 | ||
374 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
375 | static struct bfin5xx_spi_chip spidev_chip_info = { | |
376 | .enable_dma = 0, | |
377 | .bits_per_word = 8, | |
378 | }; | |
379 | #endif | |
380 | ||
381 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
382 | /* SPI (0) */ | |
383 | static struct resource bfin_spi0_resource[] = { | |
384 | [0] = { | |
385 | .start = SPI0_REGBASE, | |
386 | .end = SPI0_REGBASE + 0xFF, | |
387 | .flags = IORESOURCE_MEM, | |
388 | }, | |
389 | [1] = { | |
390 | .start = CH_SPI, | |
391 | .end = CH_SPI, | |
392 | .flags = IORESOURCE_DMA, | |
393 | }, | |
394 | [2] = { | |
395 | .start = IRQ_SPI, | |
396 | .end = IRQ_SPI, | |
397 | .flags = IORESOURCE_IRQ, | |
398 | }, | |
399 | }; | |
400 | ||
401 | /* SPI controller data */ | |
402 | static struct bfin5xx_spi_master bfin_spi0_info = { | |
403 | .num_chipselect = 8, | |
404 | .enable_dma = 1, /* master has the ability to do dma transfer */ | |
405 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
406 | }; | |
407 | ||
408 | static struct platform_device bfin_spi0_device = { | |
409 | .name = "bfin-spi", | |
410 | .id = 0, /* Bus number */ | |
411 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | |
412 | .resource = bfin_spi0_resource, | |
413 | .dev = { | |
414 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | |
415 | }, | |
416 | }; | |
417 | #endif | |
418 | ||
419 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | |
420 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | |
421 | { | |
422 | .modalias = "spidev", | |
423 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | |
424 | .bus_num = 0, | |
425 | .chip_select = 3, | |
426 | .controller_data = &spidev_chip_info, | |
427 | }, | |
428 | #endif | |
429 | #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) | |
430 | { /* DataFlash chip */ | |
431 | .modalias = "mtd_dataflash", | |
432 | .max_speed_hz = 33250000, /* max spi clock (SCK) speed in HZ */ | |
433 | .bus_num = 0, /* Framework bus number */ | |
434 | .chip_select = 2, /* Framework chip select */ | |
435 | .platform_data = &bfin_spi_dataflash_data, | |
436 | .controller_data = &data_flash_chip_info, | |
437 | .mode = SPI_MODE_3, | |
438 | }, | |
439 | #endif | |
440 | }; | |
441 | ||
442 | static struct resource bfin_gpios_resources = { | |
443 | .start = 31, | |
444 | /* .end = MAX_BLACKFIN_GPIOS - 1, */ | |
445 | .end = 32, | |
446 | .flags = IORESOURCE_IRQ, | |
447 | }; | |
448 | ||
449 | static struct platform_device bfin_gpios_device = { | |
450 | .name = "simple-gpio", | |
451 | .id = -1, | |
452 | .num_resources = 1, | |
453 | .resource = &bfin_gpios_resources, | |
454 | }; | |
455 | ||
456 | static const unsigned int cclk_vlev_datasheet[] = { | |
457 | VRPAIR(VLEV_085, 250000000), | |
458 | VRPAIR(VLEV_090, 300000000), | |
459 | VRPAIR(VLEV_095, 313000000), | |
460 | VRPAIR(VLEV_100, 350000000), | |
461 | VRPAIR(VLEV_105, 400000000), | |
462 | VRPAIR(VLEV_110, 444000000), | |
463 | VRPAIR(VLEV_115, 450000000), | |
464 | VRPAIR(VLEV_120, 475000000), | |
465 | VRPAIR(VLEV_125, 500000000), | |
466 | VRPAIR(VLEV_130, 600000000), | |
467 | }; | |
468 | ||
469 | static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { | |
470 | .tuple_tab = cclk_vlev_datasheet, | |
471 | .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), | |
472 | .vr_settling_time = 25 /* us */ , | |
473 | }; | |
474 | ||
475 | static struct platform_device bfin_dpmc = { | |
476 | .name = "bfin dpmc", | |
477 | .dev = { | |
478 | .platform_data = &bfin_dmpc_vreg_data, | |
479 | }, | |
480 | }; | |
481 | ||
482 | static struct platform_device *acvilon_devices[] __initdata = { | |
483 | &bfin_dpmc, | |
484 | ||
485 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | |
486 | &bfin_spi0_device, | |
487 | #endif | |
488 | ||
489 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | |
490 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
491 | &bfin_uart0_device, | |
492 | #endif | |
493 | #endif | |
494 | ||
495 | &bfin_gpios_device, | |
496 | ||
497 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
498 | &smsc911x_device, | |
499 | #endif | |
500 | ||
501 | &bfin_i2c_pca_device, | |
502 | ||
503 | #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE) | |
504 | &bfin_async_nand_device, | |
505 | #endif | |
506 | ||
507 | #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE) | |
508 | &mtd_ram_device, | |
509 | #endif | |
510 | ||
511 | }; | |
512 | ||
513 | static int __init acvilon_init(void) | |
514 | { | |
515 | int ret; | |
516 | ||
517 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | |
518 | ||
519 | bfin_plat_nand_init(); | |
520 | ret = | |
521 | platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices)); | |
522 | if (ret < 0) | |
523 | return ret; | |
524 | ||
525 | i2c_register_board_info(0, acvilon_i2c_devs, | |
526 | ARRAY_SIZE(acvilon_i2c_devs)); | |
527 | ||
528 | bfin_write_FIO0_FLAG_C(1 << 14); | |
529 | msleep(5); | |
530 | bfin_write_FIO0_FLAG_S(1 << 14); | |
531 | ||
532 | spi_register_board_info(bfin_spi_board_info, | |
533 | ARRAY_SIZE(bfin_spi_board_info)); | |
534 | return 0; | |
535 | } | |
536 | ||
537 | arch_initcall(acvilon_init); | |
538 | ||
539 | static struct platform_device *acvilon_early_devices[] __initdata = { | |
540 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) | |
541 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
542 | &bfin_uart0_device, | |
543 | #endif | |
544 | #endif | |
545 | }; | |
546 | ||
547 | void __init native_machine_early_platform_add_devices(void) | |
548 | { | |
549 | printk(KERN_INFO "register early platform devices\n"); | |
550 | early_platform_add_devices(acvilon_early_devices, | |
551 | ARRAY_SIZE(acvilon_early_devices)); | |
552 | } |