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Blackfin: bf52x/bf54x boards: drop unused nand page size
[net-next-2.6.git] / arch / blackfin / mach-bf527 / boards / cm_bf527.c
CommitLineData
9db144fe 1/*
96f1050d
RG		 2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2008-2009 Bluetechnix
4 * 2005 National ICT Australia (NICTA)
5 * Aidan Williams <aidan@nicta.com.au>
9db144fe 6 *
96f1050d 7 * Licensed under the GPL-2 or later.
9db144fe
MH		 8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/etherdevice.h>
9db144fe
MH		 18#include <linux/i2c.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
9db144fe 21#include <linux/usb/musb.h>
9db144fe
MH		 22#include <asm/dma.h>
23#include <asm/bfin5xx_spi.h>
24#include <asm/reboot.h>
25#include <asm/nand.h>
26#include <asm/portmux.h>
27#include <asm/dpmc.h>
28#include <linux/spi/ad7877.h>
29
30/*
31 * Name the Board for the /proc/cpuinfo
32 */
33const char bfin_board_name[] = "Bluetechnix CM-BF527";
34
35/*
36 * Driver needs to know address, irq and flag pin.
37 */
38
9db144fe 39#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
3f375690
MH		 40#include <linux/usb/isp1760.h>
41static struct resource bfin_isp1760_resources[] = {
9db144fe 42 [0] = {
3f375690
MH		 43 .start = 0x203C0000,
44 .end = 0x203C0000 + 0x000fffff,
9db144fe
MH		 45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
3f375690
MH		 48 .start = IRQ_PF7,
49 .end = IRQ_PF7,
9db144fe
MH		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
3f375690
MH		 54static struct isp1760_platform_data isp1760_priv = {
55 .is_isp1761 = 0,
3f375690
MH		 56 .bus_width_16 = 1,
57 .port1_otg = 0,
58 .analog_oc = 0,
59 .dack_polarity_high = 0,
60 .dreq_polarity_high = 0,
9db144fe
MH		 61};
62
3f375690 63static struct platform_device bfin_isp1760_device = {
c6feb768 64 .name = "isp1760",
3f375690
MH		 65 .id = 0,
66 .dev = {
67 .platform_data = &isp1760_priv,
68 },
69 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
70 .resource = bfin_isp1760_resources,
9db144fe 71};
9db144fe
MH		 72#endif
73
74#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
75static struct resource musb_resources[] = {
76 [0] = {
77 .start = 0xffc03800,
78 .end = 0xffc03cff,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = { /* general IRQ */
82 .start = IRQ_USB_INT0,
83 .end = IRQ_USB_INT0,
84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
85 },
86 [2] = { /* DMA IRQ */
87 .start = IRQ_USB_DMA,
88 .end = IRQ_USB_DMA,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
90 },
91};
92
50041acb
BW		 93static struct musb_hdrc_config musb_config = {
94 .multipoint = 0,
95 .dyn_fifo = 0,
96 .soft_con = 1,
97 .dma = 1,
fea05dac
BW		 98 .num_eps = 8,
99 .dma_channels = 8,
50041acb 100 .gpio_vrsel = GPIO_PF11,
85eb0e4b
CC		 101 /* Some custom boards need to be active low, just set it to "0"
102 * if it is the case.
103 */
104 .gpio_vrsel_active = 1,
50041acb
BW		 105};
106
9db144fe
MH		 107static struct musb_hdrc_platform_data musb_plat = {
108#if defined(CONFIG_USB_MUSB_OTG)
109 .mode = MUSB_OTG,
110#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
111 .mode = MUSB_HOST,
112#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
113 .mode = MUSB_PERIPHERAL,
114#endif
50041acb 115 .config = &musb_config,
9db144fe
MH		 116};
117
118static u64 musb_dmamask = ~(u32)0;
119
120static struct platform_device musb_device = {
121 .name = "musb_hdrc",
122 .id = 0,
123 .dev = {
124 .dma_mask = &musb_dmamask,
125 .coherent_dma_mask = 0xffffffff,
126 .platform_data = &musb_plat,
127 },
128 .num_resources = ARRAY_SIZE(musb_resources),
129 .resource = musb_resources,
130};
131#endif
132
9db144fe
MH		 133#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
134static struct mtd_partition partition_info[] = {
135 {
aa582977 136 .name = "linux kernel(nand)",
9db144fe 137 .offset = 0,
f4585a08 138 .size = 4 * 1024 * 1024,
9db144fe
MH		 139 },
140 {
aa582977 141 .name = "file system(nand)",
9db144fe
MH		 142 .offset = MTDPART_OFS_APPEND,
143 .size = MTDPART_SIZ_FULL,
144 },
145};
146
147static struct bf5xx_nand_platform bf5xx_nand_platform = {
9db144fe
MH		 148 .data_width = NFC_NWIDTH_8,
149 .partitions = partition_info,
150 .nr_partitions = ARRAY_SIZE(partition_info),
151 .rd_dly = 3,
152 .wr_dly = 3,
153};
154
155static struct resource bf5xx_nand_resources[] = {
156 {
157 .start = NFC_CTL,
158 .end = NFC_DATA_RD + 2,
159 .flags = IORESOURCE_MEM,
160 },
161 {
162 .start = CH_NFC,
163 .end = CH_NFC,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device bf5xx_nand_device = {
169 .name = "bf5xx-nand",
170 .id = 0,
171 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
172 .resource = bf5xx_nand_resources,
173 .dev = {
174 .platform_data = &bf5xx_nand_platform,
175 },
176};
177#endif
178
179#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
180static struct resource bfin_pcmcia_cf_resources[] = {
181 {
182 .start = 0x20310000, /* IO PORT */
183 .end = 0x20312000,
184 .flags = IORESOURCE_MEM,
185 }, {
186 .start = 0x20311000, /* Attribute Memory */
187 .end = 0x20311FFF,
188 .flags = IORESOURCE_MEM,
189 }, {
190 .start = IRQ_PF4,
191 .end = IRQ_PF4,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
193 }, {
194 .start = 6, /* Card Detect PF6 */
195 .end = 6,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device bfin_pcmcia_cf_device = {
201 .name = "bfin_cf_pcmcia",
202 .id = -1,
203 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
204 .resource = bfin_pcmcia_cf_resources,
205};
206#endif
207
208#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
209static struct platform_device rtc_device = {
210 .name = "rtc-bfin",
211 .id = -1,
212};
213#endif
214
215#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
61f09b5a
MH		 216#include <linux/smc91x.h>
217
218static struct smc91x_platdata smc91x_info = {
219 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
220 .leda = RPC_LED_100_10,
221 .ledb = RPC_LED_TX_RX,
222};
223
9db144fe
MH		 224static struct resource smc91x_resources[] = {
225 {
226 .name = "smc91x-regs",
227 .start = 0x20300300,
228 .end = 0x20300300 + 16,
229 .flags = IORESOURCE_MEM,
230 }, {
231
232 .start = IRQ_PF7,
233 .end = IRQ_PF7,
234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
235 },
236};
237static struct platform_device smc91x_device = {
238 .name = "smc91x",
239 .id = 0,
240 .num_resources = ARRAY_SIZE(smc91x_resources),
241 .resource = smc91x_resources,
61f09b5a
MH		 242 .dev = {
243 .platform_data = &smc91x_info,
244 },
9db144fe
MH		 245};
246#endif
247
248#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
249static struct resource dm9000_resources[] = {
250 [0] = {
251 .start = 0x203FB800,
b3dec4a4 252 .end = 0x203FB800 + 1,
9db144fe
MH		 253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
b3dec4a4
BS		 256 .start = 0x203FB804,
257 .end = 0x203FB804 + 1,
258 .flags = IORESOURCE_MEM,
259 },
260 [2] = {
9db144fe
MH		 261 .start = IRQ_PF9,
262 .end = IRQ_PF9,
263 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
264 },
265};
266
267static struct platform_device dm9000_device = {
268 .name = "dm9000",
269 .id = -1,
270 .num_resources = ARRAY_SIZE(dm9000_resources),
271 .resource = dm9000_resources,
272};
273#endif
274
9db144fe 275#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628
GY		 276static struct platform_device bfin_mii_bus = {
277 .name = "bfin_mii_bus",
278};
279
9db144fe
MH		 280static struct platform_device bfin_mac_device = {
281 .name = "bfin_mac",
65319628 282 .dev.platform_data = &bfin_mii_bus,
9db144fe
MH		 283};
284#endif
285
286#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
287static struct resource net2272_bfin_resources[] = {
288 {
289 .start = 0x20300000,
290 .end = 0x20300000 + 0x100,
291 .flags = IORESOURCE_MEM,
292 }, {
293 .start = IRQ_PF7,
294 .end = IRQ_PF7,
295 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
296 },
297};
298
299static struct platform_device net2272_bfin_device = {
300 .name = "net2272",
301 .id = -1,
302 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
303 .resource = net2272_bfin_resources,
304};
305#endif
306
307#if defined(CONFIG_MTD_M25P80) \
308 || defined(CONFIG_MTD_M25P80_MODULE)
309static struct mtd_partition bfin_spi_flash_partitions[] = {
310 {
aa582977 311 .name = "bootloader(spi)",
9db144fe
MH		 312 .size = 0x00040000,
313 .offset = 0,
314 .mask_flags = MTD_CAP_ROM
315 }, {
aa582977 316 .name = "linux kernel(spi)",
9db144fe
MH		 317 .size = MTDPART_SIZ_FULL,
318 .offset = MTDPART_OFS_APPEND,
319 }
320};
321
322static struct flash_platform_data bfin_spi_flash_data = {
323 .name = "m25p80",
324 .parts = bfin_spi_flash_partitions,
325 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
326 .type = "m25p16",
327};
328
329/* SPI flash chip (m25p64) */
330static struct bfin5xx_spi_chip spi_flash_chip_info = {
331 .enable_dma = 0, /* use dma transfer with this chip*/
332 .bits_per_word = 8,
333};
334#endif
335
a261eec0
MF		 336#if defined(CONFIG_BFIN_SPI_ADC) \
337 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 338/* SPI ADC chip */
339static struct bfin5xx_spi_chip spi_adc_chip_info = {
340 .enable_dma = 1, /* use dma transfer with this chip*/
341 .bits_per_word = 16,
342};
343#endif
344
d40bd71f
BS		 345#if defined(CONFIG_SND_BLACKFIN_AD183X) \
346 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
9db144fe
MH		 347static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
348 .enable_dma = 0,
349 .bits_per_word = 16,
350};
351#endif
352
f3f704d3
MH		 353#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
354static struct bfin5xx_spi_chip mmc_spi_chip_info = {
355 .enable_dma = 0,
9db144fe
MH		 356 .bits_per_word = 8,
357};
358#endif
359
9db144fe
MH		 360#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
361static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
362 .enable_dma = 0,
363 .bits_per_word = 16,
364};
365
366static const struct ad7877_platform_data bfin_ad7877_ts_info = {
367 .model = 7877,
368 .vref_delay_usecs = 50, /* internal, no capacitor */
369 .x_plate_ohms = 419,
370 .y_plate_ohms = 486,
371 .pressure_max = 1000,
372 .pressure_min = 0,
373 .stopacq_polarity = 1,
374 .first_conversion_delay = 3,
375 .acquisition_time = 1,
376 .averaging = 1,
377 .pen_down_acc_interval = 1,
378};
379#endif
380
381#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
382 && defined(CONFIG_SND_SOC_WM8731_SPI)
383static struct bfin5xx_spi_chip spi_wm8731_chip_info = {
384 .enable_dma = 0,
385 .bits_per_word = 16,
386};
387#endif
388
389#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
390static struct bfin5xx_spi_chip spidev_chip_info = {
391 .enable_dma = 0,
392 .bits_per_word = 8,
393};
394#endif
395
396static struct spi_board_info bfin_spi_board_info[] __initdata = {
397#if defined(CONFIG_MTD_M25P80) \
398 || defined(CONFIG_MTD_M25P80_MODULE)
399 {
400 /* the modalias must be the same as spi device driver name */
401 .modalias = "m25p80", /* Name of spi_driver for this device */
402 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
403 .bus_num = 0, /* Framework bus number */
404 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
405 .platform_data = &bfin_spi_flash_data,
406 .controller_data = &spi_flash_chip_info,
407 .mode = SPI_MODE_3,
408 },
409#endif
410
a261eec0
MF		 411#if defined(CONFIG_BFIN_SPI_ADC) \
412 || defined(CONFIG_BFIN_SPI_ADC_MODULE)
9db144fe
MH		 413 {
414 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
415 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
416 .bus_num = 0, /* Framework bus number */
417 .chip_select = 1, /* Framework chip select. */
418 .platform_data = NULL, /* No spi_driver specific config */
419 .controller_data = &spi_adc_chip_info,
420 },
421#endif
422
d40bd71f
BS		 423#if defined(CONFIG_SND_BLACKFIN_AD183X) \
424 || defined(CONFIG_SND_BLACKFIN_AD183X_MODULE)
9db144fe 425 {
dac98174 426 .modalias = "ad1836",
9db144fe
MH		 427 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
428 .bus_num = 0,
429 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
430 .controller_data = &ad1836_spi_chip_info,
431 },
432#endif
f3f704d3 433#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
9db144fe 434 {
f3f704d3
MH		 435 .modalias = "mmc_spi",
436 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
9db144fe 437 .bus_num = 0,
f3f704d3
MH		 438 .chip_select = 5,
439 .controller_data = &mmc_spi_chip_info,
9db144fe
MH		 440 .mode = SPI_MODE_3,
441 },
442#endif
9db144fe
MH		 443#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
444 {
445 .modalias = "ad7877",
446 .platform_data = &bfin_ad7877_ts_info,
447 .irq = IRQ_PF8,
448 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
449 .bus_num = 0,
450 .chip_select = 2,
451 .controller_data = &spi_ad7877_chip_info,
452 },
453#endif
454#if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
455 && defined(CONFIG_SND_SOC_WM8731_SPI)
456 {
457 .modalias = "wm8731",
458 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
459 .bus_num = 0,
460 .chip_select = 5,
461 .controller_data = &spi_wm8731_chip_info,
462 .mode = SPI_MODE_0,
463 },
464#endif
465#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
466 {
467 .modalias = "spidev",
468 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
469 .bus_num = 0,
470 .chip_select = 1,
471 .controller_data = &spidev_chip_info,
472 },
473#endif
474};
475
476#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
477/* SPI controller data */
478static struct bfin5xx_spi_master bfin_spi0_info = {
479 .num_chipselect = 8,
480 .enable_dma = 1, /* master has the ability to do dma transfer */
481 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
482};
483
484/* SPI (0) */
485static struct resource bfin_spi0_resource[] = {
486 [0] = {
487 .start = SPI0_REGBASE,
488 .end = SPI0_REGBASE + 0xFF,
489 .flags = IORESOURCE_MEM,
490 },
491 [1] = {
492 .start = CH_SPI,
493 .end = CH_SPI,
53122693
YL		 494 .flags = IORESOURCE_DMA,
495 },
496 [2] = {
497 .start = IRQ_SPI,
498 .end = IRQ_SPI,
9db144fe
MH		 499 .flags = IORESOURCE_IRQ,
500 },
501};
502
503static struct platform_device bfin_spi0_device = {
504 .name = "bfin-spi",
505 .id = 0, /* Bus number */
506 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
507 .resource = bfin_spi0_resource,
508 .dev = {
509 .platform_data = &bfin_spi0_info, /* Passed to driver */
510 },
511};
512#endif /* spi master and devices */
513
9c21453e
HK		 514#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
515static struct mtd_partition cm_partitions[] = {
516 {
517 .name = "bootloader(nor)",
518 .size = 0x40000,
519 .offset = 0,
520 }, {
521 .name = "linux kernel(nor)",
522 .size = 0x100000,
523 .offset = MTDPART_OFS_APPEND,
524 }, {
525 .name = "file system(nor)",
526 .size = MTDPART_SIZ_FULL,
527 .offset = MTDPART_OFS_APPEND,
528 }
529};
530
531static struct physmap_flash_data cm_flash_data = {
532 .width = 2,
533 .parts = cm_partitions,
534 .nr_parts = ARRAY_SIZE(cm_partitions),
535};
536
537static unsigned cm_flash_gpios[] = { GPIO_PH9, GPIO_PG11 };
538
539static struct resource cm_flash_resource[] = {
540 {
541 .name = "cfi_probe",
542 .start = 0x20000000,
543 .end = 0x201fffff,
544 .flags = IORESOURCE_MEM,
545 }, {
546 .start = (unsigned long)cm_flash_gpios,
547 .end = ARRAY_SIZE(cm_flash_gpios),
548 .flags = IORESOURCE_IRQ,
549 }
550};
551
552static struct platform_device cm_flash_device = {
553 .name = "gpio-addr-flash",
554 .id = 0,
555 .dev = {
556 .platform_data = &cm_flash_data,
557 },
558 .num_resources = ARRAY_SIZE(cm_flash_resource),
559 .resource = cm_flash_resource,
560};
561#endif
562
9db144fe 563#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
9db144fe 564#ifdef CONFIG_SERIAL_BFIN_UART0
6bd1fbea 565static struct resource bfin_uart0_resources[] = {
9db144fe 566 {
6bd1fbea
SZ		 567 .start = UART0_THR,
568 .end = UART0_GCTL+2,
9db144fe
MH		 569 .flags = IORESOURCE_MEM,
570 },
6bd1fbea
SZ		 571 {
572 .start = IRQ_UART0_RX,
573 .end = IRQ_UART0_RX+1,
574 .flags = IORESOURCE_IRQ,
575 },
576 {
577 .start = IRQ_UART0_ERROR,
578 .end = IRQ_UART0_ERROR,
579 .flags = IORESOURCE_IRQ,
580 },
581 {
582 .start = CH_UART0_TX,
583 .end = CH_UART0_TX,
584 .flags = IORESOURCE_DMA,
585 },
586 {
587 .start = CH_UART0_RX,
588 .end = CH_UART0_RX,
589 .flags = IORESOURCE_DMA,
590 },
591};
592
593unsigned short bfin_uart0_peripherals[] = {
594 P_UART0_TX, P_UART0_RX, 0
595};
596
597static struct platform_device bfin_uart0_device = {
598 .name = "bfin-uart",
599 .id = 0,
600 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
601 .resource = bfin_uart0_resources,
602 .dev = {
603 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
604 },
605};
9db144fe
MH		 606#endif
607#ifdef CONFIG_SERIAL_BFIN_UART1
6bd1fbea 608static struct resource bfin_uart1_resources[] = {
9db144fe 609 {
6bd1fbea
SZ		 610 .start = UART1_THR,
611 .end = UART1_GCTL+2,
9db144fe
MH		 612 .flags = IORESOURCE_MEM,
613 },
6bd1fbea
SZ		 614 {
615 .start = IRQ_UART1_RX,
616 .end = IRQ_UART1_RX+1,
617 .flags = IORESOURCE_IRQ,
618 },
619 {
620 .start = IRQ_UART1_ERROR,
621 .end = IRQ_UART1_ERROR,
622 .flags = IORESOURCE_IRQ,
623 },
624 {
625 .start = CH_UART1_TX,
626 .end = CH_UART1_TX,
627 .flags = IORESOURCE_DMA,
628 },
629 {
630 .start = CH_UART1_RX,
631 .end = CH_UART1_RX,
632 .flags = IORESOURCE_DMA,
633 },
634#ifdef CONFIG_BFIN_UART1_CTSRTS
635 { /* CTS pin */
636 .start = GPIO_PF9,
637 .end = GPIO_PF9,
638 .flags = IORESOURCE_IO,
639 },
640 { /* RTS pin */
641 .start = GPIO_PF10,
642 .end = GPIO_PF10,
643 .flags = IORESOURCE_IO,
644 },
9db144fe
MH		 645#endif
646};
647
6bd1fbea
SZ		 648unsigned short bfin_uart1_peripherals[] = {
649 P_UART1_TX, P_UART1_RX, 0
650};
651
652static struct platform_device bfin_uart1_device = {
9db144fe
MH		 653 .name = "bfin-uart",
654 .id = 1,
6bd1fbea
SZ		 655 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
656 .resource = bfin_uart1_resources,
657 .dev = {
658 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
659 },
9db144fe
MH		 660};
661#endif
6bd1fbea 662#endif
9db144fe
MH		 663
664#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
9db144fe 665#ifdef CONFIG_BFIN_SIR0
42bd8bcb 666static struct resource bfin_sir0_resources[] = {
9db144fe
MH		 667 {
668 .start = 0xFFC00400,
669 .end = 0xFFC004FF,
670 .flags = IORESOURCE_MEM,
671 },
42bd8bcb
GY		 672 {
673 .start = IRQ_UART0_RX,
674 .end = IRQ_UART0_RX+1,
675 .flags = IORESOURCE_IRQ,
676 },
677 {
678 .start = CH_UART0_RX,
679 .end = CH_UART0_RX+1,
680 .flags = IORESOURCE_DMA,
681 },
682};
683
684static struct platform_device bfin_sir0_device = {
685 .name = "bfin_sir",
686 .id = 0,
687 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
688 .resource = bfin_sir0_resources,
689};
9db144fe
MH		 690#endif
691#ifdef CONFIG_BFIN_SIR1
42bd8bcb 692static struct resource bfin_sir1_resources[] = {
9db144fe
MH		 693 {
694 .start = 0xFFC02000,
695 .end = 0xFFC020FF,
696 .flags = IORESOURCE_MEM,
697 },
42bd8bcb
GY		 698 {
699 .start = IRQ_UART1_RX,
700 .end = IRQ_UART1_RX+1,
701 .flags = IORESOURCE_IRQ,
702 },
703 {
704 .start = CH_UART1_RX,
705 .end = CH_UART1_RX+1,
706 .flags = IORESOURCE_DMA,
707 },
9db144fe
MH		 708};
709
42bd8bcb 710static struct platform_device bfin_sir1_device = {
9db144fe 711 .name = "bfin_sir",
42bd8bcb
GY		 712 .id = 1,
713 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
714 .resource = bfin_sir1_resources,
9db144fe
MH		 715};
716#endif
42bd8bcb 717#endif
9db144fe
MH		 718
719#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
720static struct resource bfin_twi0_resource[] = {
721 [0] = {
722 .start = TWI0_REGBASE,
723 .end = TWI0_REGBASE,
724 .flags = IORESOURCE_MEM,
725 },
726 [1] = {
727 .start = IRQ_TWI,
728 .end = IRQ_TWI,
729 .flags = IORESOURCE_IRQ,
730 },
731};
732
733static struct platform_device i2c_bfin_twi_device = {
734 .name = "i2c-bfin-twi",
735 .id = 0,
736 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
737 .resource = bfin_twi0_resource,
738};
739#endif
740
9db144fe 741static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
ebd58333 742#if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
9db144fe
MH		 743 {
744 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
9db144fe
MH		 745 },
746#endif
204844eb 747#if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
9db144fe
MH		 748 {
749 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
9db144fe
MH		 750 .irq = IRQ_PF8,
751 },
752#endif
50c4c086
MH		 753#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
754 {
755 I2C_BOARD_INFO("bfin-adv7393", 0x2B),
756 },
757#endif
9db144fe 758};
9db144fe
MH		 759
760#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261
SZ		 761#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
762static struct resource bfin_sport0_uart_resources[] = {
763 {
764 .start = SPORT0_TCR1,
765 .end = SPORT0_MRCS3+4,
766 .flags = IORESOURCE_MEM,
767 },
768 {
769 .start = IRQ_SPORT0_RX,
770 .end = IRQ_SPORT0_RX+1,
771 .flags = IORESOURCE_IRQ,
772 },
773 {
774 .start = IRQ_SPORT0_ERROR,
775 .end = IRQ_SPORT0_ERROR,
776 .flags = IORESOURCE_IRQ,
777 },
778};
779
780unsigned short bfin_sport0_peripherals[] = {
781 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
782 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
783};
784
9db144fe
MH		 785static struct platform_device bfin_sport0_uart_device = {
786 .name = "bfin-sport-uart",
787 .id = 0,
df5de261
SZ		 788 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
789 .resource = bfin_sport0_uart_resources,
790 .dev = {
791 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
792 },
793};
794#endif
795#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
796static struct resource bfin_sport1_uart_resources[] = {
797 {
798 .start = SPORT1_TCR1,
799 .end = SPORT1_MRCS3+4,
800 .flags = IORESOURCE_MEM,
801 },
802 {
803 .start = IRQ_SPORT1_RX,
804 .end = IRQ_SPORT1_RX+1,
805 .flags = IORESOURCE_IRQ,
806 },
807 {
808 .start = IRQ_SPORT1_ERROR,
809 .end = IRQ_SPORT1_ERROR,
810 .flags = IORESOURCE_IRQ,
811 },
812};
813
814unsigned short bfin_sport1_peripherals[] = {
815 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
816 P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
9db144fe
MH		 817};
818
819static struct platform_device bfin_sport1_uart_device = {
820 .name = "bfin-sport-uart",
821 .id = 1,
df5de261
SZ		 822 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
823 .resource = bfin_sport1_uart_resources,
824 .dev = {
825 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
826 },
9db144fe
MH		 827};
828#endif
df5de261 829#endif
9db144fe 830
9db144fe
MH		 831#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
832#include <linux/input.h>
833#include <linux/gpio_keys.h>
834
835static struct gpio_keys_button bfin_gpio_keys_table[] = {
836 {BTN_0, GPIO_PF14, 1, "gpio-keys: BTN0"},
837};
838
839static struct gpio_keys_platform_data bfin_gpio_keys_data = {
840 .buttons = bfin_gpio_keys_table,
841 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
842};
843
844static struct platform_device bfin_device_gpiokeys = {
845 .name = "gpio-keys",
846 .dev = {
847 .platform_data = &bfin_gpio_keys_data,
848 },
849};
850#endif
851
9db144fe
MH		 852static const unsigned int cclk_vlev_datasheet[] =
853{
854 VRPAIR(VLEV_100, 400000000),
855 VRPAIR(VLEV_105, 426000000),
856 VRPAIR(VLEV_110, 500000000),
857 VRPAIR(VLEV_115, 533000000),
858 VRPAIR(VLEV_120, 600000000),
859};
860
861static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
862 .tuple_tab = cclk_vlev_datasheet,
863 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
864 .vr_settling_time = 25 /* us */,
865};
866
867static struct platform_device bfin_dpmc = {
868 .name = "bfin dpmc",
869 .dev = {
870 .platform_data = &bfin_dmpc_vreg_data,
871 },
872};
873
9c21453e 874static struct platform_device *cmbf527_devices[] __initdata = {
9db144fe
MH		 875
876 &bfin_dpmc,
877
878#if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
879 &bf5xx_nand_device,
880#endif
881
882#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
883 &bfin_pcmcia_cf_device,
884#endif
885
886#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
887 &rtc_device,
888#endif
889
3f375690
MH		 890#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
891 &bfin_isp1760_device,
892#endif
893
9db144fe
MH		 894#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
895 &musb_device,
896#endif
897
898#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
899 &smc91x_device,
900#endif
901
902#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
903 &dm9000_device,
904#endif
905
906#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
65319628 907 &bfin_mii_bus,
9db144fe
MH		 908 &bfin_mac_device,
909#endif
910
911#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
912 &net2272_bfin_device,
913#endif
914
915#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
916 &bfin_spi0_device,
917#endif
918
9db144fe 919#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
6bd1fbea
SZ		 920#ifdef CONFIG_SERIAL_BFIN_UART0
921 &bfin_uart0_device,
922#endif
923#ifdef CONFIG_SERIAL_BFIN_UART1
924 &bfin_uart1_device,
925#endif
9db144fe
MH		 926#endif
927
928#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
42bd8bcb
GY		 929#ifdef CONFIG_BFIN_SIR0
930 &bfin_sir0_device,
931#endif
932#ifdef CONFIG_BFIN_SIR1
933 &bfin_sir1_device,
934#endif
9db144fe
MH		 935#endif
936
937#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
938 &i2c_bfin_twi_device,
939#endif
940
941#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
df5de261 942#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
9db144fe 943 &bfin_sport0_uart_device,
df5de261
SZ		 944#endif
945#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
9db144fe
MH		 946 &bfin_sport1_uart_device,
947#endif
df5de261 948#endif
9db144fe 949
9db144fe
MH		 950#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
951 &bfin_device_gpiokeys,
952#endif
953
9c21453e
HK		 954#if defined(CONFIG_MTD_GPIO_ADDR) || defined(CONFIG_MTD_GPIO_ADDR_MODULE)
955 &cm_flash_device,
9db144fe 956#endif
9db144fe
MH		 957};
958
7f6678c5 959static int __init cm_init(void)
9db144fe
MH		 960{
961 printk(KERN_INFO "%s(): registering device resources\n", __func__);
9db144fe
MH		 962 i2c_register_board_info(0, bfin_i2c_board_info,
963 ARRAY_SIZE(bfin_i2c_board_info));
9c21453e 964 platform_add_devices(cmbf527_devices, ARRAY_SIZE(cmbf527_devices));
9db144fe 965 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
9db144fe
MH		 966 return 0;
967}
968
7f6678c5 969arch_initcall(cm_init);
9db144fe 970
c13ce9fd
SZ		 971static struct platform_device *cmbf527_early_devices[] __initdata = {
972#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
973#ifdef CONFIG_SERIAL_BFIN_UART0
974 &bfin_uart0_device,
975#endif
976#ifdef CONFIG_SERIAL_BFIN_UART1
977 &bfin_uart1_device,
978#endif
979#endif
980
981#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
982#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
983 &bfin_sport0_uart_device,
984#endif
985#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
986 &bfin_sport1_uart_device,
987#endif
988#endif
989};
990
991void __init native_machine_early_platform_add_devices(void)
992{
993 printk(KERN_INFO "register early platform devices\n");
994 early_platform_add_devices(cmbf527_early_devices,
995 ARRAY_SIZE(cmbf527_early_devices));
996}
997
9db144fe
MH		 998void native_machine_restart(char *cmd)
999{
1000 /* workaround reboot hang when booting from SPI */
1001 if ((bfin_read_SYSCR() & 0x7) == 0x3)
b52dae31 1002 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
9db144fe
MH		 1003}
1004
1005void bfin_get_ether_addr(char *addr)
1006{
1007 random_ether_addr(addr);
1008 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
1009}
1010EXPORT_SYMBOL(bfin_get_ether_addr);
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