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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-pxa/include/mach/hardware.h |
1da177e4 LT |
3 | * |
4 | * Author: Nicolas Pitre | |
5 | * Created: Jun 15, 2001 | |
6 | * Copyright: MontaVista Software Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_HARDWARE_H | |
14 | #define __ASM_ARCH_HARDWARE_H | |
15 | ||
1da177e4 LT |
16 | /* |
17 | * Workarounds for at least 2 errata so far require this. | |
18 | * The mapping is set in mach-pxa/generic.c. | |
19 | */ | |
20 | #define UNCACHED_PHYS_0 0xff000000 | |
21 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | |
22 | ||
23 | /* | |
24 | * Intel PXA2xx internal register mapping: | |
25 | * | |
26 | * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff | |
27 | * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff | |
28 | * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff | |
29 | * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff | |
30 | * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff | |
31 | * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff | |
32 | * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff | |
33 | * | |
34 | * Note that not all PXA2xx chips implement all those addresses, and the | |
35 | * kernel only maps the minimum needed range of this mapping. | |
36 | */ | |
37 | #define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1)) | |
38 | #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1)) | |
39 | ||
40 | #ifndef __ASSEMBLY__ | |
41 | ||
63a4b52c | 42 | # define __REG(x) (*((volatile u32 *)io_p2v(x))) |
1da177e4 LT |
43 | |
44 | /* With indexed regs we don't want to feed the index through io_p2v() | |
45 | especially if it is a variable, otherwise horrible code will result. */ | |
61c8c158 | 46 | # define __REG2(x,y) \ |
63a4b52c | 47 | (*(volatile u32 *)((u32)&__REG(x) + (y))) |
1da177e4 LT |
48 | |
49 | # define __PREG(x) (io_v2p((u32)&(x))) | |
50 | ||
51 | #else | |
52 | ||
53 | # define __REG(x) io_p2v(x) | |
54 | # define __PREG(x) io_v2p(x) | |
55 | ||
56 | #endif | |
57 | ||
58 | #ifndef __ASSEMBLY__ | |
59 | ||
0ba8b9b2 RK |
60 | #include <asm/cputype.h> |
61 | ||
0ffcbfd5 EM |
62 | /* |
63 | * CPU Stepping CPU_ID JTAG_ID | |
64 | * | |
65 | * PXA210 B0 0x69052922 0x2926C013 | |
66 | * PXA210 B1 0x69052923 0x3926C013 | |
67 | * PXA210 B2 0x69052924 0x4926C013 | |
68 | * PXA210 C0 0x69052D25 0x5926C013 | |
69 | * | |
70 | * PXA250 A0 0x69052100 0x09264013 | |
71 | * PXA250 A1 0x69052101 0x19264013 | |
72 | * PXA250 B0 0x69052902 0x29264013 | |
73 | * PXA250 B1 0x69052903 0x39264013 | |
74 | * PXA250 B2 0x69052904 0x49264013 | |
75 | * PXA250 C0 0x69052D05 0x59264013 | |
76 | * | |
77 | * PXA255 A0 0x69052D06 0x69264013 | |
78 | * | |
79 | * PXA26x A0 0x69052903 0x39264013 | |
80 | * PXA26x B0 0x69052D05 0x59264013 | |
81 | * | |
82 | * PXA27x A0 0x69054110 0x09265013 | |
83 | * PXA27x A1 0x69054111 0x19265013 | |
84 | * PXA27x B0 0x69054112 0x29265013 | |
85 | * PXA27x B1 0x69054113 0x39265013 | |
86 | * PXA27x C0 0x69054114 0x49265013 | |
87 | * PXA27x C5 0x69054117 0x79265013 | |
88 | * | |
89 | * PXA30x A0 0x69056880 0x0E648013 | |
90 | * PXA30x A1 0x69056881 0x1E648013 | |
91 | * PXA31x A0 0x69056890 0x0E649013 | |
92 | * PXA31x A1 0x69056891 0x1E649013 | |
93 | * PXA31x A2 0x69056892 0x2E649013 | |
94 | * PXA32x B1 0x69056825 0x5E642013 | |
95 | * PXA32x B2 0x69056826 0x6E642013 | |
96 | * | |
97 | * PXA930 B0 0x69056835 0x5E643013 | |
98 | * PXA930 B1 0x69056837 0x7E643013 | |
99 | * PXA930 B2 0x69056838 0x8E643013 | |
f1c6cd62 EM |
100 | * |
101 | * PXA935 A0 0x56056931 0x1E653013 | |
102 | * PXA935 B0 0x56056936 0x6E653013 | |
61333c63 | 103 | * PXA935 B1 0x56056938 0x8E653013 |
0ffcbfd5 | 104 | */ |
36d8b17b | 105 | #ifdef CONFIG_PXA25x |
0ffcbfd5 | 106 | #define __cpu_is_pxa210(id) \ |
b23170c0 | 107 | ({ \ |
0ffcbfd5 EM |
108 | unsigned int _id = (id) & 0xf3f0; \ |
109 | _id == 0x2120; \ | |
b23170c0 RK |
110 | }) |
111 | ||
0ffcbfd5 EM |
112 | #define __cpu_is_pxa250(id) \ |
113 | ({ \ | |
114 | unsigned int _id = (id) & 0xf3ff; \ | |
115 | _id <= 0x2105; \ | |
116 | }) | |
117 | ||
118 | #define __cpu_is_pxa255(id) \ | |
119 | ({ \ | |
120 | unsigned int _id = (id) & 0xffff; \ | |
121 | _id == 0x2d06; \ | |
122 | }) | |
aa9ae8eb | 123 | |
b23170c0 RK |
124 | #define __cpu_is_pxa25x(id) \ |
125 | ({ \ | |
0ffcbfd5 EM |
126 | unsigned int _id = (id) & 0xf300; \ |
127 | _id == 0x2100; \ | |
b23170c0 | 128 | }) |
36d8b17b | 129 | #else |
0ffcbfd5 EM |
130 | #define __cpu_is_pxa210(id) (0) |
131 | #define __cpu_is_pxa250(id) (0) | |
aa9ae8eb | 132 | #define __cpu_is_pxa255(id) (0) |
36d8b17b RK |
133 | #define __cpu_is_pxa25x(id) (0) |
134 | #endif | |
b23170c0 | 135 | |
36d8b17b | 136 | #ifdef CONFIG_PXA27x |
b23170c0 RK |
137 | #define __cpu_is_pxa27x(id) \ |
138 | ({ \ | |
139 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
140 | _id == 0x411; \ | |
141 | }) | |
36d8b17b RK |
142 | #else |
143 | #define __cpu_is_pxa27x(id) (0) | |
144 | #endif | |
b23170c0 | 145 | |
36d8b17b | 146 | #ifdef CONFIG_CPU_PXA300 |
cd272ab0 | 147 | #define __cpu_is_pxa300(id) \ |
148 | ({ \ | |
149 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
150 | _id == 0x688; \ | |
151 | }) | |
36d8b17b RK |
152 | #else |
153 | #define __cpu_is_pxa300(id) (0) | |
154 | #endif | |
cd272ab0 | 155 | |
36d8b17b | 156 | #ifdef CONFIG_CPU_PXA310 |
cd272ab0 | 157 | #define __cpu_is_pxa310(id) \ |
158 | ({ \ | |
159 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
160 | _id == 0x689; \ | |
161 | }) | |
36d8b17b RK |
162 | #else |
163 | #define __cpu_is_pxa310(id) (0) | |
164 | #endif | |
cd272ab0 | 165 | |
36d8b17b | 166 | #ifdef CONFIG_CPU_PXA320 |
cd272ab0 | 167 | #define __cpu_is_pxa320(id) \ |
168 | ({ \ | |
169 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
170 | _id == 0x603 || _id == 0x682; \ | |
171 | }) | |
36d8b17b RK |
172 | #else |
173 | #define __cpu_is_pxa320(id) (0) | |
174 | #endif | |
cd272ab0 | 175 | |
5d31e435 EM |
176 | #ifdef CONFIG_CPU_PXA930 |
177 | #define __cpu_is_pxa930(id) \ | |
178 | ({ \ | |
179 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
f1c6cd62 | 180 | _id == 0x683; \ |
5d31e435 EM |
181 | }) |
182 | #else | |
183 | #define __cpu_is_pxa930(id) (0) | |
184 | #endif | |
185 | ||
f1c6cd62 EM |
186 | #ifdef CONFIG_CPU_PXA935 |
187 | #define __cpu_is_pxa935(id) \ | |
188 | ({ \ | |
189 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
190 | _id == 0x693; \ | |
191 | }) | |
192 | #else | |
193 | #define __cpu_is_pxa935(id) (0) | |
194 | #endif | |
195 | ||
4646dd27 HZ |
196 | #ifdef CONFIG_CPU_PXA950 |
197 | #define __cpu_is_pxa950(id) \ | |
198 | ({ \ | |
199 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
5d2fec5d | 200 | _id == 0x697; \ |
4646dd27 HZ |
201 | }) |
202 | #else | |
203 | #define __cpu_is_pxa950(id) (0) | |
204 | #endif | |
205 | ||
0ffcbfd5 | 206 | #define cpu_is_pxa210() \ |
b23170c0 | 207 | ({ \ |
0ffcbfd5 EM |
208 | __cpu_is_pxa210(read_cpuid_id()); \ |
209 | }) | |
210 | ||
211 | #define cpu_is_pxa250() \ | |
b23170c0 | 212 | ({ \ |
0ffcbfd5 | 213 | __cpu_is_pxa250(read_cpuid_id()); \ |
b23170c0 RK |
214 | }) |
215 | ||
aa9ae8eb IM |
216 | #define cpu_is_pxa255() \ |
217 | ({ \ | |
218 | __cpu_is_pxa255(read_cpuid_id()); \ | |
219 | }) | |
220 | ||
b23170c0 RK |
221 | #define cpu_is_pxa25x() \ |
222 | ({ \ | |
198a6d5a | 223 | __cpu_is_pxa25x(read_cpuid_id()); \ |
b23170c0 RK |
224 | }) |
225 | ||
226 | #define cpu_is_pxa27x() \ | |
227 | ({ \ | |
198a6d5a | 228 | __cpu_is_pxa27x(read_cpuid_id()); \ |
b23170c0 RK |
229 | }) |
230 | ||
cd272ab0 | 231 | #define cpu_is_pxa300() \ |
232 | ({ \ | |
198a6d5a | 233 | __cpu_is_pxa300(read_cpuid_id()); \ |
cd272ab0 | 234 | }) |
235 | ||
236 | #define cpu_is_pxa310() \ | |
237 | ({ \ | |
198a6d5a | 238 | __cpu_is_pxa310(read_cpuid_id()); \ |
cd272ab0 | 239 | }) |
240 | ||
241 | #define cpu_is_pxa320() \ | |
242 | ({ \ | |
198a6d5a | 243 | __cpu_is_pxa320(read_cpuid_id()); \ |
cd272ab0 | 244 | }) |
245 | ||
5d31e435 EM |
246 | #define cpu_is_pxa930() \ |
247 | ({ \ | |
0dfc84c9 | 248 | __cpu_is_pxa930(read_cpuid_id()); \ |
5d31e435 EM |
249 | }) |
250 | ||
f1c6cd62 EM |
251 | #define cpu_is_pxa935() \ |
252 | ({ \ | |
0dfc84c9 | 253 | __cpu_is_pxa935(read_cpuid_id()); \ |
f1c6cd62 EM |
254 | }) |
255 | ||
4646dd27 HZ |
256 | #define cpu_is_pxa950() \ |
257 | ({ \ | |
0dfc84c9 | 258 | __cpu_is_pxa950(read_cpuid_id()); \ |
4646dd27 HZ |
259 | }) |
260 | ||
261 | ||
cd272ab0 | 262 | /* |
263 | * CPUID Core Generation Bit | |
264 | * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x | |
265 | * == 0x3 for pxa300/pxa310/pxa320 | |
266 | */ | |
cfc6a554 | 267 | #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) |
cd272ab0 | 268 | #define __cpu_is_pxa2xx(id) \ |
269 | ({ \ | |
270 | unsigned int _id = (id) >> 13 & 0x7; \ | |
271 | _id <= 0x2; \ | |
272 | }) | |
cfc6a554 EM |
273 | #else |
274 | #define __cpu_is_pxa2xx(id) (0) | |
275 | #endif | |
cd272ab0 | 276 | |
cfc6a554 | 277 | #ifdef CONFIG_PXA3xx |
cd272ab0 | 278 | #define __cpu_is_pxa3xx(id) \ |
279 | ({ \ | |
280 | unsigned int _id = (id) >> 13 & 0x7; \ | |
281 | _id == 0x3; \ | |
282 | }) | |
cfc6a554 EM |
283 | #else |
284 | #define __cpu_is_pxa3xx(id) (0) | |
285 | #endif | |
cd272ab0 | 286 | |
cfc6a554 | 287 | #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935) |
61333c63 | 288 | #define __cpu_is_pxa93x(id) \ |
f1c6cd62 EM |
289 | ({ \ |
290 | unsigned int _id = (id) >> 4 & 0xfff; \ | |
291 | _id == 0x683 || _id == 0x693; \ | |
292 | }) | |
cfc6a554 EM |
293 | #else |
294 | #define __cpu_is_pxa93x(id) (0) | |
295 | #endif | |
f1c6cd62 | 296 | |
cd272ab0 | 297 | #define cpu_is_pxa2xx() \ |
298 | ({ \ | |
198a6d5a | 299 | __cpu_is_pxa2xx(read_cpuid_id()); \ |
cd272ab0 | 300 | }) |
301 | ||
302 | #define cpu_is_pxa3xx() \ | |
303 | ({ \ | |
198a6d5a | 304 | __cpu_is_pxa3xx(read_cpuid_id()); \ |
cd272ab0 | 305 | }) |
306 | ||
61333c63 | 307 | #define cpu_is_pxa93x() \ |
f1c6cd62 | 308 | ({ \ |
61333c63 | 309 | __cpu_is_pxa93x(read_cpuid_id()); \ |
f1c6cd62 | 310 | }) |
1da177e4 LT |
311 | /* |
312 | * return current memory and LCD clock frequency in units of 10kHz | |
313 | */ | |
314 | extern unsigned int get_memclk_frequency_10khz(void); | |
1da177e4 | 315 | |
6769717d EM |
316 | /* return the clock tick rate of the OS timer */ |
317 | extern unsigned long get_clock_tick_rate(void); | |
1da177e4 LT |
318 | #endif |
319 | ||
3696a8a4 MR |
320 | #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) |
321 | #define PCIBIOS_MIN_IO 0 | |
322 | #define PCIBIOS_MIN_MEM 0 | |
323 | #define pcibios_assign_all_busses() 1 | |
324 | #endif | |
325 | ||
67fbc231 | 326 | |
1da177e4 | 327 | #endif /* _ASM_ARCH_HARDWARE_H */ |