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1dbae815 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/timer-gp.c | |
3 | * | |
4 | * OMAP2 GP timer support. | |
5 | * | |
6 | * Copyright (C) 2005 Nokia Corporation | |
7 | * Author: Paul Mundt <paul.mundt@nokia.com> | |
96de0e25 | 8 | * Juha Yrjölä <juha.yrjola@nokia.com> |
77900a2f | 9 | * OMAP Dual-mode timer framework support by Timo Teras |
1dbae815 TL |
10 | * |
11 | * Some parts based off of TI's 24xx code: | |
12 | * | |
13 | * Copyright (C) 2004 Texas Instruments, Inc. | |
14 | * | |
15 | * Roughly modelled after the OMAP1 MPU timer code. | |
16 | * | |
17 | * This file is subject to the terms and conditions of the GNU General Public | |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details. | |
20 | */ | |
21 | #include <linux/init.h> | |
22 | #include <linux/time.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/err.h> | |
f8ce2547 | 25 | #include <linux/clk.h> |
77900a2f | 26 | #include <linux/delay.h> |
e6687290 | 27 | #include <linux/irq.h> |
f8ce2547 | 28 | |
1dbae815 | 29 | #include <asm/mach/time.h> |
77900a2f | 30 | #include <asm/arch/dmtimer.h> |
1dbae815 | 31 | |
77900a2f | 32 | static struct omap_dm_timer *gptimer; |
1dbae815 | 33 | |
77900a2f | 34 | static inline void omap2_gp_timer_start(unsigned long load_val) |
1dbae815 | 35 | { |
77900a2f TT |
36 | omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val); |
37 | omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); | |
38 | omap_dm_timer_start(gptimer); | |
1dbae815 TL |
39 | } |
40 | ||
0cd61b68 | 41 | static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id) |
1dbae815 TL |
42 | { |
43 | write_seqlock(&xtime_lock); | |
44 | ||
77900a2f | 45 | omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW); |
0cd61b68 | 46 | timer_tick(); |
1dbae815 TL |
47 | |
48 | write_sequnlock(&xtime_lock); | |
49 | ||
50 | return IRQ_HANDLED; | |
51 | } | |
52 | ||
53 | static struct irqaction omap2_gp_timer_irq = { | |
54 | .name = "gp timer", | |
b30fabad | 55 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
1dbae815 TL |
56 | .handler = omap2_gp_timer_interrupt, |
57 | }; | |
58 | ||
59 | static void __init omap2_gp_timer_init(void) | |
60 | { | |
77900a2f | 61 | u32 tick_period; |
1dbae815 | 62 | |
77900a2f | 63 | omap_dm_timer_init(); |
e32f7ec2 | 64 | gptimer = omap_dm_timer_request_specific(1); |
77900a2f | 65 | BUG_ON(gptimer == NULL); |
1dbae815 | 66 | |
77900a2f | 67 | omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); |
b097f494 | 68 | tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; |
1dbae815 TL |
69 | tick_period -= 1; |
70 | ||
77900a2f TT |
71 | setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); |
72 | omap2_gp_timer_start(tick_period); | |
1dbae815 TL |
73 | } |
74 | ||
75 | struct sys_timer omap_timer = { | |
76 | .init = omap2_gp_timer_init, | |
77 | }; |