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ce8ffef0 SH |
1 | /* |
2 | * Copyright (C) 2008 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #include <linux/types.h> | |
20 | #include <linux/init.h> | |
32c1ad9a | 21 | #include <linux/dma-mapping.h> |
ce8ffef0 SH |
22 | #include <linux/platform_device.h> |
23 | #include <linux/mtd/physmap.h> | |
3dad21a9 | 24 | #include <linux/mtd/plat-ram.h> |
ce8ffef0 | 25 | #include <linux/memory.h> |
ba54b958 | 26 | #include <linux/gpio.h> |
4353318e | 27 | #include <linux/smsc911x.h> |
ba54b958 | 28 | #include <linux/interrupt.h> |
79206750 SH |
29 | #include <linux/i2c.h> |
30 | #include <linux/i2c/at24.h> | |
dddd4a49 SH |
31 | #include <linux/delay.h> |
32 | #include <linux/spi/spi.h> | |
33 | #include <linux/irq.h> | |
eb05bbeb | 34 | #include <linux/fsl_devices.h> |
91bf9a25 | 35 | #include <linux/can/platform/sja1000.h> |
ee14373c SH |
36 | #include <linux/usb/otg.h> |
37 | #include <linux/usb/ulpi.h> | |
5a0e3ad6 | 38 | #include <linux/gfp.h> |
ce8ffef0 | 39 | |
32c1ad9a GL |
40 | #include <media/soc_camera.h> |
41 | ||
ce8ffef0 SH |
42 | #include <asm/mach-types.h> |
43 | #include <asm/mach/arch.h> | |
44 | #include <asm/mach/time.h> | |
45 | #include <asm/mach/map.h> | |
32c1ad9a | 46 | #include <mach/board-pcm037.h> |
a09e64fb | 47 | #include <mach/common.h> |
32c1ad9a GL |
48 | #include <mach/hardware.h> |
49 | #include <mach/i2c.h> | |
a09e64fb RK |
50 | #include <mach/imx-uart.h> |
51 | #include <mach/iomux-mx3.h> | |
a8df0ee8 | 52 | #include <mach/ipu.h> |
32c1ad9a GL |
53 | #include <mach/mmc.h> |
54 | #include <mach/mx3_camera.h> | |
a8df0ee8 | 55 | #include <mach/mx3fb.h> |
3287abbd | 56 | #include <mach/mxc_nand.h> |
ee14373c SH |
57 | #include <mach/mxc_ehci.h> |
58 | #include <mach/ulpi.h> | |
ce8ffef0 | 59 | |
5cf09421 | 60 | #include "devices.h" |
574ec547 GL |
61 | #include "pcm037.h" |
62 | ||
63 | static enum pcm037_board_variant pcm037_instance = PCM037_PCM970; | |
64 | ||
65 | static int __init pcm037_variant_setup(char *str) | |
66 | { | |
67 | if (!strcmp("eet", str)) | |
68 | pcm037_instance = PCM037_EET; | |
69 | else if (strcmp("pcm970", str)) | |
70 | pr_warning("Unknown pcm037 baseboard variant %s\n", str); | |
71 | ||
72 | return 1; | |
73 | } | |
74 | ||
75 | /* Supported values: "pcm970" (default) and "eet" */ | |
76 | __setup("pcm037_variant=", pcm037_variant_setup); | |
77 | ||
78 | enum pcm037_board_variant pcm037_variant(void) | |
79 | { | |
80 | return pcm037_instance; | |
81 | } | |
82 | ||
83 | /* UART1 with RTS/CTS handshake signals */ | |
84 | static unsigned int pcm037_uart1_handshake_pins[] = { | |
85 | MX31_PIN_CTS1__CTS1, | |
86 | MX31_PIN_RTS1__RTS1, | |
87 | MX31_PIN_TXD1__TXD1, | |
88 | MX31_PIN_RXD1__RXD1, | |
89 | }; | |
90 | ||
91 | /* UART1 without RTS/CTS handshake signals */ | |
92 | static unsigned int pcm037_uart1_pins[] = { | |
93 | MX31_PIN_TXD1__TXD1, | |
94 | MX31_PIN_RXD1__RXD1, | |
95 | }; | |
5cf09421 | 96 | |
01ac7d58 SH |
97 | static unsigned int pcm037_pins[] = { |
98 | /* I2C */ | |
99 | MX31_PIN_CSPI2_MOSI__SCL, | |
100 | MX31_PIN_CSPI2_MISO__SDA, | |
32c1ad9a GL |
101 | MX31_PIN_CSPI2_SS2__I2C3_SDA, |
102 | MX31_PIN_CSPI2_SCLK__I2C3_SCL, | |
01ac7d58 SH |
103 | /* SDHC1 */ |
104 | MX31_PIN_SD1_DATA3__SD1_DATA3, | |
105 | MX31_PIN_SD1_DATA2__SD1_DATA2, | |
106 | MX31_PIN_SD1_DATA1__SD1_DATA1, | |
107 | MX31_PIN_SD1_DATA0__SD1_DATA0, | |
108 | MX31_PIN_SD1_CLK__SD1_CLK, | |
109 | MX31_PIN_SD1_CMD__SD1_CMD, | |
110 | IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */ | |
111 | IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */ | |
112 | /* SPI1 */ | |
113 | MX31_PIN_CSPI1_MOSI__MOSI, | |
114 | MX31_PIN_CSPI1_MISO__MISO, | |
115 | MX31_PIN_CSPI1_SCLK__SCLK, | |
116 | MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, | |
117 | MX31_PIN_CSPI1_SS0__SS0, | |
118 | MX31_PIN_CSPI1_SS1__SS1, | |
119 | MX31_PIN_CSPI1_SS2__SS2, | |
01ac7d58 SH |
120 | /* UART2 */ |
121 | MX31_PIN_TXD2__TXD2, | |
122 | MX31_PIN_RXD2__RXD2, | |
123 | MX31_PIN_CTS2__CTS2, | |
124 | MX31_PIN_RTS2__RTS2, | |
125 | /* UART3 */ | |
126 | MX31_PIN_CSPI3_MOSI__RXD3, | |
127 | MX31_PIN_CSPI3_MISO__TXD3, | |
128 | MX31_PIN_CSPI3_SCLK__RTS3, | |
129 | MX31_PIN_CSPI3_SPI_RDY__CTS3, | |
130 | /* LAN9217 irq pin */ | |
131 | IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), | |
132 | /* Onewire */ | |
133 | MX31_PIN_BATT_LINE__OWIRE, | |
134 | /* Framebuffer */ | |
135 | MX31_PIN_LD0__LD0, | |
136 | MX31_PIN_LD1__LD1, | |
137 | MX31_PIN_LD2__LD2, | |
138 | MX31_PIN_LD3__LD3, | |
139 | MX31_PIN_LD4__LD4, | |
140 | MX31_PIN_LD5__LD5, | |
141 | MX31_PIN_LD6__LD6, | |
142 | MX31_PIN_LD7__LD7, | |
143 | MX31_PIN_LD8__LD8, | |
144 | MX31_PIN_LD9__LD9, | |
145 | MX31_PIN_LD10__LD10, | |
146 | MX31_PIN_LD11__LD11, | |
147 | MX31_PIN_LD12__LD12, | |
148 | MX31_PIN_LD13__LD13, | |
149 | MX31_PIN_LD14__LD14, | |
150 | MX31_PIN_LD15__LD15, | |
151 | MX31_PIN_LD16__LD16, | |
152 | MX31_PIN_LD17__LD17, | |
153 | MX31_PIN_VSYNC3__VSYNC3, | |
154 | MX31_PIN_HSYNC__HSYNC, | |
155 | MX31_PIN_FPSHIFT__FPSHIFT, | |
156 | MX31_PIN_DRDY0__DRDY0, | |
157 | MX31_PIN_D3_REV__D3_REV, | |
158 | MX31_PIN_CONTRAST__CONTRAST, | |
159 | MX31_PIN_D3_SPL__D3_SPL, | |
160 | MX31_PIN_D3_CLS__D3_CLS, | |
161 | MX31_PIN_LCS0__GPI03_23, | |
32c1ad9a GL |
162 | /* CSI */ |
163 | IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO), | |
164 | MX31_PIN_CSI_D6__CSI_D6, | |
165 | MX31_PIN_CSI_D7__CSI_D7, | |
166 | MX31_PIN_CSI_D8__CSI_D8, | |
167 | MX31_PIN_CSI_D9__CSI_D9, | |
168 | MX31_PIN_CSI_D10__CSI_D10, | |
169 | MX31_PIN_CSI_D11__CSI_D11, | |
170 | MX31_PIN_CSI_D12__CSI_D12, | |
171 | MX31_PIN_CSI_D13__CSI_D13, | |
172 | MX31_PIN_CSI_D14__CSI_D14, | |
173 | MX31_PIN_CSI_D15__CSI_D15, | |
174 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, | |
175 | MX31_PIN_CSI_MCLK__CSI_MCLK, | |
176 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, | |
177 | MX31_PIN_CSI_VSYNC__CSI_VSYNC, | |
e0fd4db3 LF |
178 | /* GPIO */ |
179 | IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), | |
ee14373c | 180 | /* OTG */ |
eb05bbeb GL |
181 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, |
182 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | |
183 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | |
184 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | |
185 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | |
186 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | |
187 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | |
188 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | |
189 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | |
190 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | |
191 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | |
192 | MX31_PIN_USBOTG_STP__USBOTG_STP, | |
ee14373c SH |
193 | /* USB host 2 */ |
194 | IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), | |
195 | IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), | |
196 | IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), | |
197 | IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), | |
198 | IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), | |
199 | IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), | |
200 | IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), | |
201 | IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), | |
202 | IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), | |
203 | IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), | |
204 | IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), | |
205 | IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), | |
eb05bbeb GL |
206 | }; |
207 | ||
ee14373c SH |
208 | static struct physmap_flash_data pcm037_flash_data = { |
209 | .width = 2, | |
210 | }; | |
eb05bbeb | 211 | |
ee14373c SH |
212 | static struct resource pcm037_flash_resource = { |
213 | .start = 0xa0000000, | |
214 | .end = 0xa1ffffff, | |
215 | .flags = IORESOURCE_MEM, | |
eb05bbeb GL |
216 | }; |
217 | ||
ce8ffef0 SH |
218 | static struct platform_device pcm037_flash = { |
219 | .name = "physmap-flash", | |
220 | .id = 0, | |
221 | .dev = { | |
222 | .platform_data = &pcm037_flash_data, | |
223 | }, | |
224 | .resource = &pcm037_flash_resource, | |
225 | .num_resources = 1, | |
226 | }; | |
227 | ||
228 | static struct imxuart_platform_data uart_pdata = { | |
a9b06233 | 229 | .flags = IMXUART_HAVE_RTSCTS, |
ce8ffef0 SH |
230 | }; |
231 | ||
4353318e | 232 | static struct resource smsc911x_resources[] = { |
3f4f54b4 | 233 | { |
f568dd7f UKK |
234 | .start = MX31_CS1_BASE_ADDR + 0x300, |
235 | .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, | |
ba54b958 | 236 | .flags = IORESOURCE_MEM, |
3f4f54b4 | 237 | }, { |
ba54b958 GL |
238 | .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), |
239 | .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), | |
4353318e | 240 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
ba54b958 GL |
241 | }, |
242 | }; | |
243 | ||
4353318e SG |
244 | static struct smsc911x_platform_config smsc911x_info = { |
245 | .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY | | |
246 | SMSC911X_SAVE_MAC_ADDRESS, | |
247 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
248 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
249 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
ba54b958 GL |
250 | }; |
251 | ||
252 | static struct platform_device pcm037_eth = { | |
4353318e | 253 | .name = "smsc911x", |
ba54b958 | 254 | .id = -1, |
4353318e SG |
255 | .num_resources = ARRAY_SIZE(smsc911x_resources), |
256 | .resource = smsc911x_resources, | |
ba54b958 | 257 | .dev = { |
4353318e | 258 | .platform_data = &smsc911x_info, |
ba54b958 GL |
259 | }, |
260 | }; | |
261 | ||
3dad21a9 SH |
262 | static struct platdata_mtd_ram pcm038_sram_data = { |
263 | .bankwidth = 2, | |
264 | }; | |
265 | ||
266 | static struct resource pcm038_sram_resource = { | |
f568dd7f UKK |
267 | .start = MX31_CS4_BASE_ADDR, |
268 | .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, | |
3dad21a9 SH |
269 | .flags = IORESOURCE_MEM, |
270 | }; | |
271 | ||
272 | static struct platform_device pcm037_sram_device = { | |
273 | .name = "mtd-ram", | |
274 | .id = 0, | |
275 | .dev = { | |
276 | .platform_data = &pcm038_sram_data, | |
277 | }, | |
278 | .num_resources = 1, | |
279 | .resource = &pcm038_sram_resource, | |
280 | }; | |
281 | ||
3287abbd SH |
282 | static struct mxc_nand_platform_data pcm037_nand_board_info = { |
283 | .width = 1, | |
284 | .hw_ecc = 1, | |
285 | }; | |
286 | ||
79206750 SH |
287 | static struct imxi2c_platform_data pcm037_i2c_1_data = { |
288 | .bitrate = 100000, | |
79206750 SH |
289 | }; |
290 | ||
32c1ad9a GL |
291 | static struct imxi2c_platform_data pcm037_i2c_2_data = { |
292 | .bitrate = 20000, | |
293 | }; | |
294 | ||
79206750 SH |
295 | static struct at24_platform_data board_eeprom = { |
296 | .byte_len = 4096, | |
297 | .page_size = 32, | |
298 | .flags = AT24_FLAG_ADDR16, | |
299 | }; | |
300 | ||
32c1ad9a GL |
301 | static int pcm037_camera_power(struct device *dev, int on) |
302 | { | |
303 | /* disable or enable the camera in X7 or X8 PCM970 connector */ | |
304 | gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on); | |
305 | return 0; | |
306 | } | |
307 | ||
9d00278d | 308 | static struct i2c_board_info pcm037_i2c_camera[] = { |
32c1ad9a GL |
309 | { |
310 | I2C_BOARD_INFO("mt9t031", 0x5d), | |
9d00278d GL |
311 | }, { |
312 | I2C_BOARD_INFO("mt9v022", 0x48), | |
32c1ad9a GL |
313 | }, |
314 | }; | |
315 | ||
9d00278d GL |
316 | static struct soc_camera_link iclink_mt9v022 = { |
317 | .bus_id = 0, /* Must match with the camera ID */ | |
318 | .board_info = &pcm037_i2c_camera[1], | |
319 | .i2c_adapter_id = 2, | |
320 | .module_name = "mt9v022", | |
321 | }; | |
322 | ||
323 | static struct soc_camera_link iclink_mt9t031 = { | |
32c1ad9a GL |
324 | .bus_id = 0, /* Must match with the camera ID */ |
325 | .power = pcm037_camera_power, | |
9d00278d | 326 | .board_info = &pcm037_i2c_camera[0], |
32c1ad9a GL |
327 | .i2c_adapter_id = 2, |
328 | .module_name = "mt9t031", | |
329 | }; | |
330 | ||
79206750 | 331 | static struct i2c_board_info pcm037_i2c_devices[] = { |
32c1ad9a | 332 | { |
79206750 SH |
333 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ |
334 | .platform_data = &board_eeprom, | |
335 | }, { | |
cf87a6e2 | 336 | I2C_BOARD_INFO("pcf8563", 0x51), |
79206750 SH |
337 | } |
338 | }; | |
32c1ad9a | 339 | |
9d00278d | 340 | static struct platform_device pcm037_mt9t031 = { |
32c1ad9a GL |
341 | .name = "soc-camera-pdrv", |
342 | .id = 0, | |
343 | .dev = { | |
9d00278d GL |
344 | .platform_data = &iclink_mt9t031, |
345 | }, | |
346 | }; | |
347 | ||
348 | static struct platform_device pcm037_mt9v022 = { | |
349 | .name = "soc-camera-pdrv", | |
350 | .id = 1, | |
351 | .dev = { | |
352 | .platform_data = &iclink_mt9v022, | |
32c1ad9a GL |
353 | }, |
354 | }; | |
79206750 | 355 | |
dddd4a49 SH |
356 | /* Not connected by default */ |
357 | #ifdef PCM970_SDHC_RW_SWITCH | |
358 | static int pcm970_sdhc1_get_ro(struct device *dev) | |
f2cb641f | 359 | { |
dddd4a49 SH |
360 | return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6)); |
361 | } | |
362 | #endif | |
363 | ||
4f163eb8 SH |
364 | #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6) |
365 | #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6) | |
366 | ||
dddd4a49 SH |
367 | static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq, |
368 | void *data) | |
369 | { | |
370 | int ret; | |
dddd4a49 | 371 | |
4f163eb8 SH |
372 | ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect"); |
373 | if (ret) | |
374 | return ret; | |
375 | ||
376 | gpio_direction_input(SDHC1_GPIO_DET); | |
dddd4a49 | 377 | |
4f163eb8 SH |
378 | #ifdef PCM970_SDHC_RW_SWITCH |
379 | ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp"); | |
380 | if (ret) | |
381 | goto err_gpio_free; | |
382 | gpio_direction_input(SDHC1_GPIO_WP); | |
383 | #endif | |
dddd4a49 SH |
384 | |
385 | ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq, | |
386 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | |
387 | "sdhc-detect", data); | |
4f163eb8 SH |
388 | if (ret) |
389 | goto err_gpio_free_2; | |
390 | ||
391 | return 0; | |
392 | ||
393 | err_gpio_free_2: | |
394 | #ifdef PCM970_SDHC_RW_SWITCH | |
395 | gpio_free(SDHC1_GPIO_WP); | |
396 | err_gpio_free: | |
397 | #endif | |
398 | gpio_free(SDHC1_GPIO_DET); | |
399 | ||
dddd4a49 | 400 | return ret; |
f2cb641f SH |
401 | } |
402 | ||
403 | static void pcm970_sdhc1_exit(struct device *dev, void *data) | |
404 | { | |
dddd4a49 | 405 | free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data); |
4f163eb8 SH |
406 | gpio_free(SDHC1_GPIO_DET); |
407 | gpio_free(SDHC1_GPIO_WP); | |
f2cb641f SH |
408 | } |
409 | ||
f2cb641f | 410 | static struct imxmmc_platform_data sdhc_pdata = { |
dddd4a49 SH |
411 | #ifdef PCM970_SDHC_RW_SWITCH |
412 | .get_ro = pcm970_sdhc1_get_ro, | |
413 | #endif | |
f2cb641f SH |
414 | .init = pcm970_sdhc1_init, |
415 | .exit = pcm970_sdhc1_exit, | |
416 | }; | |
417 | ||
32c1ad9a GL |
418 | struct mx3_camera_pdata camera_pdata = { |
419 | .dma_dev = &mx3_ipu.dev, | |
420 | .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, | |
421 | .mclk_10khz = 2000, | |
422 | }; | |
423 | ||
424 | static int __init pcm037_camera_alloc_dma(const size_t buf_size) | |
425 | { | |
426 | dma_addr_t dma_handle; | |
427 | void *buf; | |
428 | int dma; | |
429 | ||
430 | if (buf_size < 2 * 1024 * 1024) | |
431 | return -EINVAL; | |
432 | ||
433 | buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); | |
434 | if (!buf) { | |
435 | pr_err("%s: cannot allocate camera buffer-memory\n", __func__); | |
436 | return -ENOMEM; | |
437 | } | |
438 | ||
439 | memset(buf, 0, buf_size); | |
440 | ||
441 | dma = dma_declare_coherent_memory(&mx3_camera.dev, | |
442 | dma_handle, dma_handle, buf_size, | |
443 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | |
444 | ||
445 | /* The way we call dma_declare_coherent_memory only a malloc can fail */ | |
446 | return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; | |
447 | } | |
448 | ||
ce8ffef0 SH |
449 | static struct platform_device *devices[] __initdata = { |
450 | &pcm037_flash, | |
3dad21a9 | 451 | &pcm037_sram_device, |
3170ba54 | 452 | &imx_wdt_device0, |
9d00278d GL |
453 | &pcm037_mt9t031, |
454 | &pcm037_mt9v022, | |
ce8ffef0 SH |
455 | }; |
456 | ||
a8df0ee8 GL |
457 | static struct ipu_platform_data mx3_ipu_data = { |
458 | .irq_base = MXC_IPU_IRQ_START, | |
459 | }; | |
460 | ||
461 | static const struct fb_videomode fb_modedb[] = { | |
462 | { | |
463 | /* 240x320 @ 60 Hz Sharp */ | |
464 | .name = "Sharp-LQ035Q7DH06-QVGA", | |
465 | .refresh = 60, | |
466 | .xres = 240, | |
467 | .yres = 320, | |
468 | .pixclock = 185925, | |
469 | .left_margin = 9, | |
470 | .right_margin = 16, | |
471 | .upper_margin = 7, | |
472 | .lower_margin = 9, | |
473 | .hsync_len = 1, | |
474 | .vsync_len = 1, | |
475 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | | |
476 | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, | |
477 | .vmode = FB_VMODE_NONINTERLACED, | |
478 | .flag = 0, | |
479 | }, { | |
480 | /* 240x320 @ 60 Hz */ | |
481 | .name = "TX090", | |
482 | .refresh = 60, | |
483 | .xres = 240, | |
484 | .yres = 320, | |
485 | .pixclock = 38255, | |
486 | .left_margin = 144, | |
487 | .right_margin = 0, | |
488 | .upper_margin = 7, | |
489 | .lower_margin = 40, | |
490 | .hsync_len = 96, | |
491 | .vsync_len = 1, | |
492 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, | |
493 | .vmode = FB_VMODE_NONINTERLACED, | |
494 | .flag = 0, | |
574ec547 GL |
495 | }, { |
496 | /* 240x320 @ 60 Hz */ | |
497 | .name = "CMEL-OLED", | |
498 | .refresh = 60, | |
499 | .xres = 240, | |
500 | .yres = 320, | |
501 | .pixclock = 185925, | |
502 | .left_margin = 9, | |
503 | .right_margin = 16, | |
504 | .upper_margin = 7, | |
505 | .lower_margin = 9, | |
506 | .hsync_len = 1, | |
507 | .vsync_len = 1, | |
508 | .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT, | |
509 | .vmode = FB_VMODE_NONINTERLACED, | |
510 | .flag = 0, | |
a8df0ee8 GL |
511 | }, |
512 | }; | |
513 | ||
514 | static struct mx3fb_platform_data mx3fb_pdata = { | |
515 | .dma_dev = &mx3_ipu.dev, | |
516 | .name = "Sharp-LQ035Q7DH06-QVGA", | |
517 | .mode = fb_modedb, | |
518 | .num_modes = ARRAY_SIZE(fb_modedb), | |
519 | }; | |
520 | ||
91bf9a25 SH |
521 | static struct resource pcm970_sja1000_resources[] = { |
522 | { | |
f568dd7f UKK |
523 | .start = MX31_CS5_BASE_ADDR, |
524 | .end = MX31_CS5_BASE_ADDR + 0x100 - 1, | |
91bf9a25 SH |
525 | .flags = IORESOURCE_MEM, |
526 | }, { | |
527 | .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), | |
528 | .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), | |
529 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, | |
530 | }, | |
531 | }; | |
532 | ||
533 | struct sja1000_platform_data pcm970_sja1000_platform_data = { | |
534 | .clock = 16000000 / 2, | |
535 | .ocr = 0x40 | 0x18, | |
536 | .cdr = 0x40, | |
537 | }; | |
538 | ||
539 | static struct platform_device pcm970_sja1000 = { | |
540 | .name = "sja1000_platform", | |
541 | .dev = { | |
542 | .platform_data = &pcm970_sja1000_platform_data, | |
543 | }, | |
544 | .resource = pcm970_sja1000_resources, | |
545 | .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), | |
546 | }; | |
547 | ||
ee14373c SH |
548 | static struct mxc_usbh_platform_data otg_pdata = { |
549 | .portsc = MXC_EHCI_MODE_ULPI, | |
550 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | |
551 | }; | |
552 | ||
553 | static struct mxc_usbh_platform_data usbh2_pdata = { | |
554 | .portsc = MXC_EHCI_MODE_ULPI, | |
555 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | |
556 | }; | |
557 | ||
558 | static struct fsl_usb2_platform_data otg_device_pdata = { | |
559 | .operating_mode = FSL_USB2_DR_DEVICE, | |
560 | .phy_mode = FSL_USB2_PHY_ULPI, | |
561 | }; | |
562 | ||
563 | static int otg_mode_host; | |
564 | ||
565 | static int __init pcm037_otg_mode(char *options) | |
566 | { | |
567 | if (!strcmp(options, "host")) | |
568 | otg_mode_host = 1; | |
569 | else if (!strcmp(options, "device")) | |
570 | otg_mode_host = 0; | |
571 | else | |
572 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
573 | "Defaulting to device\n"); | |
574 | return 0; | |
575 | } | |
576 | __setup("otg_mode=", pcm037_otg_mode); | |
577 | ||
ce8ffef0 SH |
578 | /* |
579 | * Board specific initialization. | |
580 | */ | |
581 | static void __init mxc_board_init(void) | |
582 | { | |
4f163eb8 | 583 | int ret; |
ee14373c SH |
584 | u32 tmp; |
585 | ||
586 | mxc_iomux_set_gpr(MUX_PGP_UH2, 1); | |
4f163eb8 | 587 | |
01ac7d58 SH |
588 | mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), |
589 | "pcm037"); | |
590 | ||
ee14373c SH |
591 | #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ |
592 | | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | |
593 | ||
594 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); | |
595 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); | |
596 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); | |
597 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); | |
598 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ | |
599 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ | |
600 | mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ | |
601 | mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ | |
602 | mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ | |
603 | mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ | |
604 | mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ | |
605 | mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ | |
606 | ||
574ec547 GL |
607 | if (pcm037_variant() == PCM037_EET) |
608 | mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, | |
609 | ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); | |
610 | else | |
611 | mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins, | |
612 | ARRAY_SIZE(pcm037_uart1_handshake_pins), | |
613 | "pcm037_uart1"); | |
614 | ||
ce8ffef0 SH |
615 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
616 | ||
5cf09421 | 617 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
13e9f612 | 618 | mxc_register_device(&mxc_uart_device1, &uart_pdata); |
5cf09421 | 619 | mxc_register_device(&mxc_uart_device2, &uart_pdata); |
d517cab1 | 620 | |
d517cab1 | 621 | mxc_register_device(&mxc_w1_master_device, NULL); |
ba54b958 | 622 | |
f8e5143b | 623 | /* LAN9217 IRQ pin */ |
4f163eb8 SH |
624 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); |
625 | if (ret) | |
626 | pr_warning("could not get LAN irq gpio\n"); | |
627 | else { | |
628 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)); | |
629 | platform_device_register(&pcm037_eth); | |
630 | } | |
631 | ||
3287abbd | 632 | |
32c1ad9a | 633 | /* I2C adapters and devices */ |
79206750 SH |
634 | i2c_register_board_info(1, pcm037_i2c_devices, |
635 | ARRAY_SIZE(pcm037_i2c_devices)); | |
636 | ||
637 | mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); | |
32c1ad9a GL |
638 | mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data); |
639 | ||
3287abbd | 640 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); |
f2cb641f | 641 | mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); |
a8df0ee8 GL |
642 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); |
643 | mxc_register_device(&mx3_fb, &mx3fb_pdata); | |
32c1ad9a GL |
644 | |
645 | /* CSI */ | |
646 | /* Camera power: default - off */ | |
647 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power"); | |
648 | if (!ret) | |
649 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1); | |
650 | else | |
9d00278d | 651 | iclink_mt9t031.power = NULL; |
32c1ad9a GL |
652 | |
653 | if (!pcm037_camera_alloc_dma(4 * 1024 * 1024)) | |
654 | mxc_register_device(&mx3_camera, &camera_pdata); | |
91bf9a25 SH |
655 | |
656 | platform_device_register(&pcm970_sja1000); | |
ee14373c SH |
657 | |
658 | #if defined(CONFIG_USB_ULPI) | |
659 | if (otg_mode_host) { | |
660 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | |
661 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | |
662 | ||
663 | mxc_register_device(&mxc_otg_host, &otg_pdata); | |
664 | } | |
665 | ||
666 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | |
667 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | |
668 | ||
669 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | |
670 | #endif | |
671 | if (!otg_mode_host) | |
672 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | |
673 | ||
ce8ffef0 SH |
674 | } |
675 | ||
ce8ffef0 SH |
676 | static void __init pcm037_timer_init(void) |
677 | { | |
30c730f8 | 678 | mx31_clocks_init(26000000); |
ce8ffef0 SH |
679 | } |
680 | ||
681 | struct sys_timer pcm037_timer = { | |
682 | .init = pcm037_timer_init, | |
683 | }; | |
684 | ||
685 | MACHINE_START(PCM037, "Phytec Phycore pcm037") | |
686 | /* Maintainer: Pengutronix */ | |
f568dd7f | 687 | .phys_io = MX31_AIPS1_BASE_ADDR, |
321ed164 | 688 | .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, |
34101237 | 689 | .boot_params = MX3x_PHYS_OFFSET + 0x100, |
cd4a05f9 | 690 | .map_io = mx31_map_io, |
c5aa0ad0 | 691 | .init_irq = mx31_init_irq, |
ce8ffef0 SH |
692 | .init_machine = mxc_board_init, |
693 | .timer = &pcm037_timer, | |
694 | MACHINE_END |