[net-next-2.6.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
	static struct resource mxc_spi_resources ## n[] = {			\
		{								\
			.start = baseaddr,					\
			.end = baseaddr + SZ_4K - 1,				\
			.flags = IORESOURCE_MEM,				\
		}, {								\
			.start = irq,						\
			.end = irq,						\
			.flags = IORESOURCE_IRQ,				\
		},								\
	};									\
										\
	struct platform_device mxc_spi_device ## n = {				\
		.name = "spi_imx",						\
		.id = n,							\
		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
		.resource = mxc_spi_resources ## n,				\
	}

DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)				\
	static struct resource timer ## n ##_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_gpt ## n = {				\
		.name = "imx_gpt",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(timer ## n ## _resources),	\
		.resource = timer ## n ## _resources,			\
	}

/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif

/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
static struct resource mxc_wdt_resources[] = {
	{
		.start = MX2x_WDOG_BASE_ADDR,
		.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "imx2-wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = MX2x_OWIRE_BASE_ADDR,
		.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)			\
	static struct resource pfx ## _nand_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		},							\
	};								\
									\
	struct platform_device pfx ## _nand_device = {			\
		.name = "mxc_nand",					\
		.id = 0,						\
		.num_resources = ARRAY_SIZE(pfx ## _nand_resources),	\
		.resource = pfx ## _nand_resources,			\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
#endif

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = MX2x_LCDC_BASE_ADDR,
		.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_LCDC,
		.end = MX2x_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start = MX27_FEC_BASE_ADDR,
		.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_FEC,
		.end = MX27_INT_FEC,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)				\
	static struct resource mxc_i2c_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_i2c_device ## n = {			\
		.name = "imx-i2c",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),	\
		.resource = mxc_i2c_resources ## n,			\
	}

DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start = MX2x_PWM_BASE_ADDR,
		.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX2x_INT_PWM,
		.end = MX2x_INT_PWM,
		.flags = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq)			\
	static struct resource mxc_sdhc_resources ## n[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}, {							\
			.start = dmareq,				\
			.end = dmareq,					\
			.flags = IORESOURCE_DMA,			\
		},							\
	};								\
									\
	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32);	\
									\
	struct platform_device mxc_sdhc_device ## n = {			\
		.name = "mxc-mmc",					\
		.id = n,						\
		.dev = {						\
			.dma_mask = &mxc_sdhc ## n ## _dmamask,		\
			.coherent_dma_mask = DMA_BIT_MASK(32),		\
		},							\
		.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n),	\
		.resource = mxc_sdhc_resources ## n,		\
	}

DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR,
		.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB3,
		.end = MX27_INT_USB3,
		.flags = IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x200,
		.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB1,
		.end = MX27_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = DMA_BIT_MASK(32);

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX27_USBOTG_BASE_ADDR + 0x400,
		.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MX27_INT_USB2,
		.end = MX27_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = DMA_BIT_MASK(32),
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix)			\
	{								\
		.name = _name,						\
		.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,	\
		.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix,		\
		.flags = IORESOURCE_DMA,				\
	}

#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq)			\
	static struct resource imx_ssi_resources ## n[] = {		\
		{							\
			.start = MX2x_SSI ## ssin ## _BASE_ADDR,	\
			.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f,	\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = MX2x_INT_SSI1,				\
			.end = MX2x_INT_SSI1,				\
			.flags = IORESOURCE_IRQ,			\
		},							\
		DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0),		\
		DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0),		\
		DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1),		\
		DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1),		\
	};								\
									\
	struct platform_device imx_ssi_device ## n = {			\
		.name = "imx-ssi",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(imx_ssi_resources ## n),	\
		.resource = imx_ssi_resources ## n,			\
	}

DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);

/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)				\
	{								\
		.chip.label = "gpio-" #n,				\
		.irq = _irq,						\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORT(SOC, n)					\
	{								\
		.chip.label = "gpio-" #n,				\
		.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR +	\
				n * 0x100),				\
		.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32,	\
	}

#define DEFINE_MXC_GPIO_PORTS(SOC, pfx)					\
	static struct mxc_gpio_port pfx ## _gpio_ports[] = {		\
		DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO),	\
		DEFINE_MXC_GPIO_PORT(SOC, 1),				\
		DEFINE_MXC_GPIO_PORT(SOC, 2),				\
		DEFINE_MXC_GPIO_PORT(SOC, 3),				\
		DEFINE_MXC_GPIO_PORT(SOC, 4),				\
		DEFINE_MXC_GPIO_PORT(SOC, 5),				\
	}

#ifdef CONFIG_MACH_MX21
DEFINE_MXC_GPIO_PORTS(MX21, imx21);
#endif

#ifdef CONFIG_MACH_MX27
DEFINE_MXC_GPIO_PORTS(MX27, imx27);
#endif

int __init mxc_register_gpios(void)
{
#ifdef CONFIG_MACH_MX21
	if (cpu_is_mx21())
		return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
	else
#endif
#ifdef CONFIG_MACH_MX27
	if (cpu_is_mx27())
		return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
	else
#endif
		return 0;
}

#ifdef CONFIG_MACH_MX21
static struct resource mx21_usbhc_resources[] = {
	{
		.start	= MX21_BASE_ADDR,
		.end	= MX21_BASE_ADDR + 0x1FFF,
		.flags	= IORESOURCE_MEM,
	},
	{
		.start		= MX21_INT_USBHOST,
		.end		= MX21_INT_USBHOST,
		.flags		= IORESOURCE_IRQ,
	},
};

struct platform_device mx21_usbhc_device = {
	.name		= "imx21-hcd",
	.id		= 0,
	.dev		= {
		.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
	.num_resources	= ARRAY_SIZE(mx21_usbhc_resources),
	.resource	= mx21_usbhc_resources,
};
#endif
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
3eb352c7	34	#include <linux/dma-mapping.h>
fc80a5e3	35
80b02c17	36	#include <mach/irqs.h>
a09e64fb	37	#include <mach/hardware.h>
058b7a6f	38	#include <mach/common.h>
1a02be0e	39	#include <mach/mmc.h>
058b7a6f HS	40
058b7a6f HS	41	#include "devices.h"
fc80a5e3	42
f420db84 SH	43	/*
	44	* SPI master controller
	45	*
	46	* - i.MX1: 2 channel (slighly different register setting)
	47	* - i.MX21: 2 channel
	48	* - i.MX27: 3 channel
	49	*/
68c94b40 UKK	50	#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
	51	static struct resource mxc_spi_resources ## n[] = { \
	52	{ \
	53	.start = baseaddr, \
	54	.end = baseaddr + SZ_4K - 1, \
	55	.flags = IORESOURCE_MEM, \
	56	}, { \
	57	.start = irq, \
	58	.end = irq, \
	59	.flags = IORESOURCE_IRQ, \
	60	}, \
	61	}; \
	62	\
	63	struct platform_device mxc_spi_device ## n = { \
	64	.name = "spi_imx", \
	65	.id = n, \
	66	.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
	67	.resource = mxc_spi_resources ## n, \
	68	}
f420db84	69
68c94b40 UKK	70	DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
68c94b40 UKK	71	DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
f420db84 SH	72
f420db84 SH	73	#ifdef CONFIG_MACH_MX27
68c94b40	74	DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
f420db84 SH	75	#endif
f420db84 SH	76
fc80a5e3 JB	77	/*
fc80a5e3 JB	78	* General Purpose Timer
bf50bcc2 SH	79	* - i.MX21: 3 timers
bf50bcc2 SH	80	* - i.MX27: 6 timers
fc80a5e3	81	*/
2b84a364 UKK	82	#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
	83	static struct resource timer ## n ##_resources[] = { \
	84	{ \
	85	.start = baseaddr, \
	86	.end = baseaddr + SZ_4K - 1, \
	87	.flags = IORESOURCE_MEM, \
	88	}, { \
	89	.start = irq, \
	90	.end = irq, \
	91	.flags = IORESOURCE_IRQ, \
	92	} \
	93	}; \
	94	\
	95	struct platform_device mxc_gpt ## n = { \
	96	.name = "imx_gpt", \
	97	.id = n, \
	98	.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
	99	.resource = timer ## n ## _resources, \
fc80a5e3	100	}
fc80a5e3	101
2b84a364 UKK	102	/* We use gpt1 as system timer, so do not add a device for this one */
	103	DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
	104	DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
fc80a5e3 JB	105
fc80a5e3 JB	106	#ifdef CONFIG_MACH_MX27
2b84a364 UKK	107	DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
	108	DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
	109	DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
fc80a5e3 JB	110	#endif
fc80a5e3 JB	111
6d38c1cf	112	/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
fc80a5e3 JB	113	static struct resource mxc_wdt_resources[] = {
fc80a5e3 JB	114	{
58152a16 UKK	115	.start = MX2x_WDOG_BASE_ADDR,
	116	.end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
	117	.flags = IORESOURCE_MEM,
fc80a5e3 JB	118	},
	119	};
	120
	121	struct platform_device mxc_wdt = {
6d38c1cf	122	.name = "imx2-wdt",
fc80a5e3 JB	123	.id = 0,
	124	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	125	.resource = mxc_wdt_resources,
	126	};
	127
3d89baa7 SH	128	static struct resource mxc_w1_master_resources[] = {
3d89baa7 SH	129	{
58152a16 UKK	130	.start = MX2x_OWIRE_BASE_ADDR,
58152a16 UKK	131	.end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
3d89baa7 SH	132	.flags = IORESOURCE_MEM,
	133	},
	134	};
	135
	136	struct platform_device mxc_w1_master_device = {
	137	.name = "mxc_w1",
	138	.id = 0,
	139	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	140	.resource = mxc_w1_master_resources,
	141	};
	142
f0d3ab49 UKK	143	#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \
	144	static struct resource pfx ## _nand_resources[] = { \
	145	{ \
	146	.start = baseaddr, \
	147	.end = baseaddr + SZ_4K - 1, \
	148	.flags = IORESOURCE_MEM, \
	149	}, { \
	150	.start = irq, \
	151	.end = irq, \
	152	.flags = IORESOURCE_IRQ, \
	153	}, \
	154	}; \
	155	\
	156	struct platform_device pfx ## _nand_device = { \
	157	.name = "mxc_nand", \
	158	.id = 0, \
	159	.num_resources = ARRAY_SIZE(pfx ## _nand_resources), \
	160	.resource = pfx ## _nand_resources, \
	161	}
02870978	162
f0d3ab49 UKK	163	#ifdef CONFIG_MACH_MX21
	164	DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
	165	#endif
	166
	167	#ifdef CONFIG_MACH_MX27
	168	DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
	169	#endif
02870978	170
e4813551 HS	171	/*
	172	* lcdc:
	173	* - i.MX1: the basic controller
	174	* - i.MX21: to be checked
	175	* - i.MX27: like i.MX1, with slightly variations
	176	*/
	177	static struct resource mxc_fb[] = {
	178	{
58152a16 UKK	179	.start = MX2x_LCDC_BASE_ADDR,
58152a16 UKK	180	.end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
e4813551	181	.flags = IORESOURCE_MEM,
bf50bcc2	182	}, {
58152a16 UKK	183	.start = MX2x_INT_LCDC,
58152a16 UKK	184	.end = MX2x_INT_LCDC,
e4813551 HS	185	.flags = IORESOURCE_IRQ,
	186	}
	187	};
	188
	189	/* mxc lcd driver */
	190	struct platform_device mxc_fb_device = {
	191	.name = "imx-fb",
	192	.id = 0,
	193	.num_resources = ARRAY_SIZE(mxc_fb),
	194	.resource = mxc_fb,
	195	.dev = {
3eb352c7	196	.coherent_dma_mask = DMA_BIT_MASK(32),
e4813551 HS	197	},
	198	};
	199
879fea1b SH	200	#ifdef CONFIG_MACH_MX27
	201	static struct resource mxc_fec_resources[] = {
	202	{
58152a16 UKK	203	.start = MX27_FEC_BASE_ADDR,
	204	.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
	205	.flags = IORESOURCE_MEM,
879fea1b	206	}, {
58152a16 UKK	207	.start = MX27_INT_FEC,
	208	.end = MX27_INT_FEC,
	209	.flags = IORESOURCE_IRQ,
879fea1b SH	210	},
	211	};
	212
	213	struct platform_device mxc_fec_device = {
	214	.name = "fec",
	215	.id = 0,
	216	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	217	.resource = mxc_fec_resources,
	218	};
e4813551 HS	219	#endif
e4813551 HS	220
9309b2ba UKK	221	#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
	222	static struct resource mxc_i2c_resources ## n[] = { \
	223	{ \
	224	.start = baseaddr, \
	225	.end = baseaddr + SZ_4K - 1, \
	226	.flags = IORESOURCE_MEM, \
	227	}, { \
	228	.start = irq, \
	229	.end = irq, \
	230	.flags = IORESOURCE_IRQ, \
	231	} \
	232	}; \
	233	\
	234	struct platform_device mxc_i2c_device ## n = { \
	235	.name = "imx-i2c", \
	236	.id = n, \
	237	.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
	238	.resource = mxc_i2c_resources ## n, \
c5d4dbff	239	}
c5d4dbff	240
9309b2ba	241	DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
c5d4dbff SH	242
c5d4dbff SH	243	#ifdef CONFIG_MACH_MX27
9309b2ba	244	DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
c5d4dbff SH	245	#endif
c5d4dbff SH	246
824b16e6	247	static struct resource mxc_pwm_resources[] = {
bf50bcc2	248	{
58152a16 UKK	249	.start = MX2x_PWM_BASE_ADDR,
	250	.end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
	251	.flags = IORESOURCE_MEM,
bf50bcc2	252	}, {
58152a16 UKK	253	.start = MX2x_INT_PWM,
	254	.end = MX2x_INT_PWM,
	255	.flags = IORESOURCE_IRQ,
824b16e6 SH	256	}
	257	};
	258
	259	struct platform_device mxc_pwm_device = {
	260	.name = "mxc_pwm",
	261	.id = 0,
	262	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	263	.resource = mxc_pwm_resources,
824b16e6 SH	264	};
824b16e6 SH	265
ccd0e42c UKK	266	#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
	267	static struct resource mxc_sdhc_resources ## n[] = { \
	268	{ \
	269	.start = baseaddr, \
	270	.end = baseaddr + SZ_4K - 1, \
	271	.flags = IORESOURCE_MEM, \
	272	}, { \
	273	.start = irq, \
	274	.end = irq, \
	275	.flags = IORESOURCE_IRQ, \
	276	}, { \
	277	.start = dmareq, \
	278	.end = dmareq, \
	279	.flags = IORESOURCE_DMA, \
	280	}, \
	281	}; \
	282	\
988addf8	283	static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
ccd0e42c UKK	284	\
	285	struct platform_device mxc_sdhc_device ## n = { \
	286	.name = "mxc-mmc", \
	287	.id = n, \
	288	.dev = { \
	289	.dma_mask = &mxc_sdhc ## n ## _dmamask, \
988addf8	290	.coherent_dma_mask = DMA_BIT_MASK(32), \
ccd0e42c UKK	291	}, \
	292	.num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
	293	.resource = mxc_sdhc_resources ## n, \
	294	}
1a02be0e	295
ccd0e42c UKK	296	DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
ccd0e42c UKK	297	DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
1a02be0e	298
f6d2fa7d	299	#ifdef CONFIG_MACH_MX27
627fb3b9 M	300	static struct resource otg_resources[] = {
627fb3b9 M	301	{
58152a16 UKK	302	.start = MX27_USBOTG_BASE_ADDR,
	303	.end = MX27_USBOTG_BASE_ADDR + 0x1ff,
	304	.flags = IORESOURCE_MEM,
627fb3b9	305	}, {
58152a16 UKK	306	.start = MX27_INT_USB3,
	307	.end = MX27_INT_USB3,
	308	.flags = IORESOURCE_IRQ,
627fb3b9 M	309	},
	310	};
	311
3eb352c7	312	static u64 otg_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	313
	314	/* OTG gadget device */
	315	struct platform_device mxc_otg_udc_device = {
	316	.name = "fsl-usb2-udc",
	317	.id = -1,
	318	.dev = {
	319	.dma_mask = &otg_dmamask,
3eb352c7	320	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	321	},
	322	.resource = otg_resources,
	323	.num_resources = ARRAY_SIZE(otg_resources),
	324	};
	325
	326	/* OTG host */
	327	struct platform_device mxc_otg_host = {
	328	.name = "mxc-ehci",
	329	.id = 0,
	330	.dev = {
3eb352c7	331	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	332	.dma_mask = &otg_dmamask,
	333	},
	334	.resource = otg_resources,
	335	.num_resources = ARRAY_SIZE(otg_resources),
	336	};
	337
	338	/* USB host 1 */
	339
3eb352c7	340	static u64 usbh1_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	341
	342	static struct resource mxc_usbh1_resources[] = {
	343	{
58152a16 UKK	344	.start = MX27_USBOTG_BASE_ADDR + 0x200,
58152a16 UKK	345	.end = MX27_USBOTG_BASE_ADDR + 0x3ff,
627fb3b9 M	346	.flags = IORESOURCE_MEM,
627fb3b9 M	347	}, {
58152a16 UKK	348	.start = MX27_INT_USB1,
58152a16 UKK	349	.end = MX27_INT_USB1,
627fb3b9 M	350	.flags = IORESOURCE_IRQ,
	351	},
	352	};
	353
	354	struct platform_device mxc_usbh1 = {
	355	.name = "mxc-ehci",
	356	.id = 1,
	357	.dev = {
3eb352c7	358	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	359	.dma_mask = &usbh1_dmamask,
	360	},
	361	.resource = mxc_usbh1_resources,
	362	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	363	};
	364
	365	/* USB host 2 */
3eb352c7	366	static u64 usbh2_dmamask = DMA_BIT_MASK(32);
627fb3b9 M	367
	368	static struct resource mxc_usbh2_resources[] = {
	369	{
58152a16 UKK	370	.start = MX27_USBOTG_BASE_ADDR + 0x400,
58152a16 UKK	371	.end = MX27_USBOTG_BASE_ADDR + 0x5ff,
627fb3b9 M	372	.flags = IORESOURCE_MEM,
627fb3b9 M	373	}, {
58152a16 UKK	374	.start = MX27_INT_USB2,
58152a16 UKK	375	.end = MX27_INT_USB2,
627fb3b9 M	376	.flags = IORESOURCE_IRQ,
	377	},
	378	};
	379
	380	struct platform_device mxc_usbh2 = {
	381	.name = "mxc-ehci",
	382	.id = 2,
	383	.dev = {
3eb352c7	384	.coherent_dma_mask = DMA_BIT_MASK(32),
627fb3b9 M	385	.dma_mask = &usbh2_dmamask,
	386	},
	387	.resource = mxc_usbh2_resources,
	388	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	389	};
f6d2fa7d	390	#endif
627fb3b9	391
69ddb488 UKK	392	#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
	393	{ \
	394	.name = _name, \
	395	.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	396	.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
	397	.flags = IORESOURCE_DMA, \
	398	}
23291df4	399
69ddb488 UKK	400	#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
	401	static struct resource imx_ssi_resources ## n[] = { \
	402	{ \
	403	.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
	404	.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
	405	.flags = IORESOURCE_MEM, \
	406	}, { \
	407	.start = MX2x_INT_SSI1, \
	408	.end = MX2x_INT_SSI1, \
	409	.flags = IORESOURCE_IRQ, \
	410	}, \
	411	DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
	412	DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
	413	DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
	414	DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
	415	}; \
	416	\
	417	struct platform_device imx_ssi_device ## n = { \
	418	.name = "imx-ssi", \
	419	.id = n, \
	420	.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
	421	.resource = imx_ssi_resources ## n, \
	422	}
23291df4	423
69ddb488 UKK	424	DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
69ddb488 UKK	425	DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
23291df4	426
fc80a5e3	427	/* GPIO port description */
897359d5 UKK	428	#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
	429	{ \
	430	.chip.label = "gpio-" #n, \
	431	.irq = _irq, \
	432	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	433	n * 0x100), \
	434	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
	435	}
	436
	437	#define DEFINE_MXC_GPIO_PORT(SOC, n) \
	438	{ \
	439	.chip.label = "gpio-" #n, \
	440	.base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
	441	n * 0x100), \
	442	.virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
fc80a5e3	443	}
897359d5 UKK	444
	445	#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
	446	static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
	447	DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
	448	DEFINE_MXC_GPIO_PORT(SOC, 1), \
	449	DEFINE_MXC_GPIO_PORT(SOC, 2), \
	450	DEFINE_MXC_GPIO_PORT(SOC, 3), \
	451	DEFINE_MXC_GPIO_PORT(SOC, 4), \
	452	DEFINE_MXC_GPIO_PORT(SOC, 5), \
	453	}
	454
	455	#ifdef CONFIG_MACH_MX21
	456	DEFINE_MXC_GPIO_PORTS(MX21, imx21);
	457	#endif
	458
	459	#ifdef CONFIG_MACH_MX27
	460	DEFINE_MXC_GPIO_PORTS(MX27, imx27);
	461	#endif
fc80a5e3 JB	462
	463	int __init mxc_register_gpios(void)
	464	{
897359d5 UKK	465	#ifdef CONFIG_MACH_MX21
	466	if (cpu_is_mx21())
	467	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
	468	else
	469	#endif
	470	#ifdef CONFIG_MACH_MX27
	471	if (cpu_is_mx27())
	472	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
	473	else
	474	#endif
	475	return 0;
fc80a5e3	476	}
4e0fa90d MF	477
	478	#ifdef CONFIG_MACH_MX21
	479	static struct resource mx21_usbhc_resources[] = {
	480	{
988addf8 RK	481	.start = MX21_BASE_ADDR,
988addf8 RK	482	.end = MX21_BASE_ADDR + 0x1FFF,
4e0fa90d MF	483	.flags = IORESOURCE_MEM,
	484	},
	485	{
988addf8 RK	486	.start = MX21_INT_USBHOST,
988addf8 RK	487	.end = MX21_INT_USBHOST,
4e0fa90d MF	488	.flags = IORESOURCE_IRQ,
	489	},
	490	};
	491
	492	struct platform_device mx21_usbhc_device = {
	493	.name = "imx21-hcd",
	494	.id = 0,
	495	.dev = {
	496	.dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
	497	.coherent_dma_mask = DMA_BIT_MASK(32),
	498	},
	499	.num_resources = ARRAY_SIZE(mx21_usbhc_resources),
	500	.resource = mx21_usbhc_resources,
	501	};
	502	#endif
	503