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AT91: SAM9G45 - add a separate clock entry for every single TC block
[net-next-2.6.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
CommitLineData
789b23bc
NF		 1/*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
15#include <linux/dma-mapping.h>
16#include <linux/platform_device.h>
17#include <linux/i2c-gpio.h>
18
19#include <linux/fb.h>
20#include <video/atmel_lcdc.h>
21
22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9g45.h>
25#include <mach/at91sam9g45_matrix.h>
26#include <mach/at91sam9_smc.h>
40262b2b 27#include <mach/at_hdmac.h>
789b23bc
NF		 28
29#include "generic.h"
30
31
40262b2b
NF		 32/* --------------------------------------------------------------------
33 * HDMAC - AHB DMA Controller
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
37static u64 hdmac_dmamask = DMA_BIT_MASK(32);
38
39static struct at_dma_platform_data atdma_pdata = {
40 .nr_channels = 8,
41};
42
43static struct resource hdmac_resources[] = {
44 [0] = {
45 .start = AT91_BASE_SYS + AT91_DMA,
46 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
47 .flags = IORESOURCE_MEM,
48 },
8d2602e0 49 [1] = {
40262b2b
NF		 50 .start = AT91SAM9G45_ID_DMA,
51 .end = AT91SAM9G45_ID_DMA,
52 .flags = IORESOURCE_IRQ,
53 },
54};
55
56static struct platform_device at_hdmac_device = {
57 .name = "at_hdmac",
58 .id = -1,
59 .dev = {
60 .dma_mask = &hdmac_dmamask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 .platform_data = &atdma_pdata,
63 },
64 .resource = hdmac_resources,
65 .num_resources = ARRAY_SIZE(hdmac_resources),
66};
67
68void __init at91_add_device_hdmac(void)
69{
70 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
71 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
72 platform_device_register(&at_hdmac_device);
73}
74#else
75void __init at91_add_device_hdmac(void) {}
76#endif
77
78
789b23bc
NF		 79/* --------------------------------------------------------------------
80 * USB Host (OHCI)
81 * -------------------------------------------------------------------- */
82
83#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84static u64 ohci_dmamask = DMA_BIT_MASK(32);
85static struct at91_usbh_data usbh_ohci_data;
86
87static struct resource usbh_ohci_resources[] = {
88 [0] = {
89 .start = AT91SAM9G45_OHCI_BASE,
90 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = AT91SAM9G45_ID_UHPHS,
95 .end = AT91SAM9G45_ID_UHPHS,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static struct platform_device at91_usbh_ohci_device = {
101 .name = "at91_ohci",
102 .id = -1,
103 .dev = {
104 .dma_mask = &ohci_dmamask,
105 .coherent_dma_mask = DMA_BIT_MASK(32),
106 .platform_data = &usbh_ohci_data,
107 },
108 .resource = usbh_ohci_resources,
109 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
110};
111
112void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
113{
114 int i;
115
116 if (!data)
117 return;
118
119 /* Enable VBus control for UHP ports */
120 for (i = 0; i < data->ports; i++) {
121 if (data->vbus_pin[i])
122 at91_set_gpio_output(data->vbus_pin[i], 0);
123 }
124
125 usbh_ohci_data = *data;
126 platform_device_register(&at91_usbh_ohci_device);
127}
128#else
129void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
130#endif
131
132
f51f78c0
NF		 133/* --------------------------------------------------------------------
134 * USB Host HS (EHCI)
135 * Needs an OHCI host for low and full speed management
136 * -------------------------------------------------------------------- */
137
138#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
139static u64 ehci_dmamask = DMA_BIT_MASK(32);
140static struct at91_usbh_data usbh_ehci_data;
141
142static struct resource usbh_ehci_resources[] = {
143 [0] = {
144 .start = AT91SAM9G45_EHCI_BASE,
145 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 .start = AT91SAM9G45_ID_UHPHS,
150 .end = AT91SAM9G45_ID_UHPHS,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155static struct platform_device at91_usbh_ehci_device = {
156 .name = "atmel-ehci",
157 .id = -1,
158 .dev = {
159 .dma_mask = &ehci_dmamask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 .platform_data = &usbh_ehci_data,
162 },
163 .resource = usbh_ehci_resources,
164 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
165};
166
167void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
168{
169 int i;
170
171 if (!data)
172 return;
173
174 /* Enable VBus control for UHP ports */
175 for (i = 0; i < data->ports; i++) {
176 if (data->vbus_pin[i])
177 at91_set_gpio_output(data->vbus_pin[i], 0);
178 }
179
180 usbh_ehci_data = *data;
181 at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
182 platform_device_register(&at91_usbh_ehci_device);
183}
184#else
185void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
186#endif
187
188
789b23bc
NF		 189/* --------------------------------------------------------------------
190 * USB HS Device (Gadget)
191 * -------------------------------------------------------------------- */
192
193#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
194static struct resource usba_udc_resources[] = {
195 [0] = {
196 .start = AT91SAM9G45_UDPHS_FIFO,
197 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = AT91SAM9G45_BASE_UDPHS,
202 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
203 .flags = IORESOURCE_MEM,
204 },
205 [2] = {
206 .start = AT91SAM9G45_ID_UDPHS,
207 .end = AT91SAM9G45_ID_UDPHS,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
213 [idx] = { \
214 .name = nam, \
215 .index = idx, \
216 .fifo_size = maxpkt, \
217 .nr_banks = maxbk, \
218 .can_dma = dma, \
219 .can_isoc = isoc, \
220 }
221
222static struct usba_ep_data usba_udc_ep[] __initdata = {
223 EP("ep0", 0, 64, 1, 0, 0),
224 EP("ep1", 1, 1024, 2, 1, 1),
225 EP("ep2", 2, 1024, 2, 1, 1),
226 EP("ep3", 3, 1024, 3, 1, 0),
227 EP("ep4", 4, 1024, 3, 1, 0),
228 EP("ep5", 5, 1024, 3, 1, 1),
229 EP("ep6", 6, 1024, 3, 1, 1),
230};
231
232#undef EP
233
234/*
235 * pdata doesn't have room for any endpoints, so we need to
236 * append room for the ones we need right after it.
237 */
238static struct {
239 struct usba_platform_data pdata;
240 struct usba_ep_data ep[7];
241} usba_udc_data;
242
243static struct platform_device at91_usba_udc_device = {
244 .name = "atmel_usba_udc",
245 .id = -1,
246 .dev = {
247 .platform_data = &usba_udc_data.pdata,
248 },
249 .resource = usba_udc_resources,
250 .num_resources = ARRAY_SIZE(usba_udc_resources),
251};
252
253void __init at91_add_device_usba(struct usba_platform_data *data)
254{
255 usba_udc_data.pdata.vbus_pin = -EINVAL;
256 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
257 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
258
259 if (data && data->vbus_pin > 0) {
260 at91_set_gpio_input(data->vbus_pin, 0);
261 at91_set_deglitch(data->vbus_pin, 1);
262 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
263 }
264
265 /* Pullup pin is handled internally by USB device peripheral */
266
267 /* Clocks */
268 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
269 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
270
271 platform_device_register(&at91_usba_udc_device);
272}
273#else
274void __init at91_add_device_usba(struct usba_platform_data *data) {}
275#endif
276
277
278/* --------------------------------------------------------------------
279 * Ethernet
280 * -------------------------------------------------------------------- */
281
282#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
283static u64 eth_dmamask = DMA_BIT_MASK(32);
284static struct at91_eth_data eth_data;
285
286static struct resource eth_resources[] = {
287 [0] = {
288 .start = AT91SAM9G45_BASE_EMAC,
289 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
290 .flags = IORESOURCE_MEM,
291 },
292 [1] = {
293 .start = AT91SAM9G45_ID_EMAC,
294 .end = AT91SAM9G45_ID_EMAC,
295 .flags = IORESOURCE_IRQ,
296 },
297};
298
299static struct platform_device at91sam9g45_eth_device = {
300 .name = "macb",
301 .id = -1,
302 .dev = {
303 .dma_mask = &eth_dmamask,
304 .coherent_dma_mask = DMA_BIT_MASK(32),
305 .platform_data = &eth_data,
306 },
307 .resource = eth_resources,
308 .num_resources = ARRAY_SIZE(eth_resources),
309};
310
311void __init at91_add_device_eth(struct at91_eth_data *data)
312{
313 if (!data)
314 return;
315
316 if (data->phy_irq_pin) {
317 at91_set_gpio_input(data->phy_irq_pin, 0);
318 at91_set_deglitch(data->phy_irq_pin, 1);
319 }
320
321 /* Pins used for MII and RMII */
322 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
323 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
324 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
325 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
326 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
327 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
328 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
329 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
330 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
331 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
332
333 if (!data->is_rmii) {
334 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
335 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
336 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
337 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
338 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
339 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
340 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
341 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
342 }
343
344 eth_data = *data;
345 platform_device_register(&at91sam9g45_eth_device);
346}
347#else
348void __init at91_add_device_eth(struct at91_eth_data *data) {}
349#endif
350
351
352/* --------------------------------------------------------------------
353 * NAND / SmartMedia
354 * -------------------------------------------------------------------- */
355
356#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
357static struct atmel_nand_data nand_data;
358
359#define NAND_BASE AT91_CHIPSELECT_3
360
361static struct resource nand_resources[] = {
362 [0] = {
363 .start = NAND_BASE,
364 .end = NAND_BASE + SZ_256M - 1,
365 .flags = IORESOURCE_MEM,
366 },
367 [1] = {
368 .start = AT91_BASE_SYS + AT91_ECC,
369 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
370 .flags = IORESOURCE_MEM,
371 }
372};
373
374static struct platform_device at91sam9g45_nand_device = {
375 .name = "atmel_nand",
376 .id = -1,
377 .dev = {
378 .platform_data = &nand_data,
379 },
380 .resource = nand_resources,
381 .num_resources = ARRAY_SIZE(nand_resources),
382};
383
384void __init at91_add_device_nand(struct atmel_nand_data *data)
385{
386 unsigned long csa;
387
388 if (!data)
389 return;
390
391 csa = at91_sys_read(AT91_MATRIX_EBICSA);
392 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
393
394 /* enable pin */
395 if (data->enable_pin)
396 at91_set_gpio_output(data->enable_pin, 1);
397
398 /* ready/busy pin */
399 if (data->rdy_pin)
400 at91_set_gpio_input(data->rdy_pin, 1);
401
402 /* card detect pin */
403 if (data->det_pin)
404 at91_set_gpio_input(data->det_pin, 1);
405
406 nand_data = *data;
407 platform_device_register(&at91sam9g45_nand_device);
408}
409#else
410void __init at91_add_device_nand(struct atmel_nand_data *data) {}
411#endif
412
413
414/* --------------------------------------------------------------------
415 * TWI (i2c)
416 * -------------------------------------------------------------------- */
417
418/*
419 * Prefer the GPIO code since the TWI controller isn't robust
420 * (gets overruns and underruns under load) and can only issue
421 * repeated STARTs in one scenario (the driver doesn't yet handle them).
422 */
423#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
424static struct i2c_gpio_platform_data pdata_i2c0 = {
425 .sda_pin = AT91_PIN_PA20,
426 .sda_is_open_drain = 1,
427 .scl_pin = AT91_PIN_PA21,
428 .scl_is_open_drain = 1,
429 .udelay = 2, /* ~100 kHz */
430};
431
432static struct platform_device at91sam9g45_twi0_device = {
433 .name = "i2c-gpio",
434 .id = 0,
435 .dev.platform_data = &pdata_i2c0,
436};
437
438static struct i2c_gpio_platform_data pdata_i2c1 = {
439 .sda_pin = AT91_PIN_PB10,
440 .sda_is_open_drain = 1,
441 .scl_pin = AT91_PIN_PB11,
442 .scl_is_open_drain = 1,
443 .udelay = 2, /* ~100 kHz */
444};
445
446static struct platform_device at91sam9g45_twi1_device = {
447 .name = "i2c-gpio",
448 .id = 1,
449 .dev.platform_data = &pdata_i2c1,
450};
451
452void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
453{
454 i2c_register_board_info(i2c_id, devices, nr_devices);
455
456 if (i2c_id == 0) {
457 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
458 at91_set_multi_drive(AT91_PIN_PA20, 1);
459
460 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
461 at91_set_multi_drive(AT91_PIN_PA21, 1);
462
463 platform_device_register(&at91sam9g45_twi0_device);
464 } else {
465 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
466 at91_set_multi_drive(AT91_PIN_PB10, 1);
467
468 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
469 at91_set_multi_drive(AT91_PIN_PB11, 1);
470
471 platform_device_register(&at91sam9g45_twi1_device);
472 }
473}
474
475#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
476static struct resource twi0_resources[] = {
477 [0] = {
478 .start = AT91SAM9G45_BASE_TWI0,
479 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
480 .flags = IORESOURCE_MEM,
481 },
482 [1] = {
483 .start = AT91SAM9G45_ID_TWI0,
484 .end = AT91SAM9G45_ID_TWI0,
485 .flags = IORESOURCE_IRQ,
486 },
487};
488
489static struct platform_device at91sam9g45_twi0_device = {
490 .name = "at91_i2c",
491 .id = 0,
492 .resource = twi0_resources,
493 .num_resources = ARRAY_SIZE(twi0_resources),
494};
495
496static struct resource twi1_resources[] = {
497 [0] = {
498 .start = AT91SAM9G45_BASE_TWI1,
499 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
500 .flags = IORESOURCE_MEM,
501 },
502 [1] = {
503 .start = AT91SAM9G45_ID_TWI1,
504 .end = AT91SAM9G45_ID_TWI1,
505 .flags = IORESOURCE_IRQ,
506 },
507};
508
509static struct platform_device at91sam9g45_twi1_device = {
510 .name = "at91_i2c",
511 .id = 1,
512 .resource = twi1_resources,
513 .num_resources = ARRAY_SIZE(twi1_resources),
514};
515
516void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
517{
518 i2c_register_board_info(i2c_id, devices, nr_devices);
519
520 /* pins used for TWI interface */
521 if (i2c_id == 0) {
522 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
523 at91_set_multi_drive(AT91_PIN_PA20, 1);
524
525 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
526 at91_set_multi_drive(AT91_PIN_PA21, 1);
527
528 platform_device_register(&at91sam9g45_twi0_device);
529 } else {
530 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
531 at91_set_multi_drive(AT91_PIN_PB10, 1);
532
533 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
534 at91_set_multi_drive(AT91_PIN_PB11, 1);
535
536 platform_device_register(&at91sam9g45_twi1_device);
537 }
538}
539#else
540void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
541#endif
542
543
544/* --------------------------------------------------------------------
545 * SPI
546 * -------------------------------------------------------------------- */
547
548#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
549static u64 spi_dmamask = DMA_BIT_MASK(32);
550
551static struct resource spi0_resources[] = {
552 [0] = {
553 .start = AT91SAM9G45_BASE_SPI0,
554 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
555 .flags = IORESOURCE_MEM,
556 },
557 [1] = {
558 .start = AT91SAM9G45_ID_SPI0,
559 .end = AT91SAM9G45_ID_SPI0,
560 .flags = IORESOURCE_IRQ,
561 },
562};
563
564static struct platform_device at91sam9g45_spi0_device = {
565 .name = "atmel_spi",
566 .id = 0,
567 .dev = {
568 .dma_mask = &spi_dmamask,
569 .coherent_dma_mask = DMA_BIT_MASK(32),
570 },
571 .resource = spi0_resources,
572 .num_resources = ARRAY_SIZE(spi0_resources),
573};
574
575static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
576
577static struct resource spi1_resources[] = {
578 [0] = {
579 .start = AT91SAM9G45_BASE_SPI1,
580 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
581 .flags = IORESOURCE_MEM,
582 },
583 [1] = {
584 .start = AT91SAM9G45_ID_SPI1,
585 .end = AT91SAM9G45_ID_SPI1,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
590static struct platform_device at91sam9g45_spi1_device = {
591 .name = "atmel_spi",
592 .id = 1,
593 .dev = {
594 .dma_mask = &spi_dmamask,
595 .coherent_dma_mask = DMA_BIT_MASK(32),
596 },
597 .resource = spi1_resources,
598 .num_resources = ARRAY_SIZE(spi1_resources),
599};
600
601static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
602
603void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
604{
605 int i;
606 unsigned long cs_pin;
607 short enable_spi0 = 0;
608 short enable_spi1 = 0;
609
610 /* Choose SPI chip-selects */
611 for (i = 0; i < nr_devices; i++) {
612 if (devices[i].controller_data)
613 cs_pin = (unsigned long) devices[i].controller_data;
614 else if (devices[i].bus_num == 0)
615 cs_pin = spi0_standard_cs[devices[i].chip_select];
616 else
617 cs_pin = spi1_standard_cs[devices[i].chip_select];
618
619 if (devices[i].bus_num == 0)
620 enable_spi0 = 1;
621 else
622 enable_spi1 = 1;
623
624 /* enable chip-select pin */
625 at91_set_gpio_output(cs_pin, 1);
626
627 /* pass chip-select pin to driver */
628 devices[i].controller_data = (void *) cs_pin;
629 }
630
631 spi_register_board_info(devices, nr_devices);
632
633 /* Configure SPI bus(es) */
634 if (enable_spi0) {
635 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
636 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
637 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
638
639 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
640 platform_device_register(&at91sam9g45_spi0_device);
641 }
642 if (enable_spi1) {
643 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
644 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
645 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
646
647 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
648 platform_device_register(&at91sam9g45_spi1_device);
649 }
650}
651#else
652void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
653#endif
654
655
378ac65e
NF		 656/* --------------------------------------------------------------------
657 * AC97
658 * -------------------------------------------------------------------- */
659
660#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
661static u64 ac97_dmamask = DMA_BIT_MASK(32);
662static struct ac97c_platform_data ac97_data;
663
664static struct resource ac97_resources[] = {
665 [0] = {
666 .start = AT91SAM9G45_BASE_AC97C,
667 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
668 .flags = IORESOURCE_MEM,
669 },
670 [1] = {
671 .start = AT91SAM9G45_ID_AC97C,
672 .end = AT91SAM9G45_ID_AC97C,
673 .flags = IORESOURCE_IRQ,
674 },
675};
676
677static struct platform_device at91sam9g45_ac97_device = {
678 .name = "atmel_ac97c",
679 .id = 0,
680 .dev = {
681 .dma_mask = &ac97_dmamask,
682 .coherent_dma_mask = DMA_BIT_MASK(32),
683 .platform_data = &ac97_data,
684 },
685 .resource = ac97_resources,
686 .num_resources = ARRAY_SIZE(ac97_resources),
687};
688
689void __init at91_add_device_ac97(struct ac97c_platform_data *data)
690{
691 if (!data)
692 return;
693
694 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
695 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
696 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
697 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
698
699 /* reset */
700 if (data->reset_pin)
701 at91_set_gpio_output(data->reset_pin, 0);
702
703 ac97_data = *data;
704 platform_device_register(&at91sam9g45_ac97_device);
705}
706#else
707void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
708#endif
709
710
789b23bc
NF		 711/* --------------------------------------------------------------------
712 * LCD Controller
713 * -------------------------------------------------------------------- */
714
715#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
716static u64 lcdc_dmamask = DMA_BIT_MASK(32);
717static struct atmel_lcdfb_info lcdc_data;
718
719static struct resource lcdc_resources[] = {
720 [0] = {
721 .start = AT91SAM9G45_LCDC_BASE,
722 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
723 .flags = IORESOURCE_MEM,
724 },
725 [1] = {
726 .start = AT91SAM9G45_ID_LCDC,
727 .end = AT91SAM9G45_ID_LCDC,
728 .flags = IORESOURCE_IRQ,
729 },
730};
731
732static struct platform_device at91_lcdc_device = {
733 .name = "atmel_lcdfb",
734 .id = 0,
735 .dev = {
736 .dma_mask = &lcdc_dmamask,
737 .coherent_dma_mask = DMA_BIT_MASK(32),
738 .platform_data = &lcdc_data,
739 },
740 .resource = lcdc_resources,
741 .num_resources = ARRAY_SIZE(lcdc_resources),
742};
743
744void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
745{
746 if (!data)
747 return;
748
749 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
750
751 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
752 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
753 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
754 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
755 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
756 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
757 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
758 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
759 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
760 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
761 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
762 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
763 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
764 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
765 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
766 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
767 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
768 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
769 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
770 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
771 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
772 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
773 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
774 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
775 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
776 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
777 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
778 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
779 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
780
781 lcdc_data = *data;
782 platform_device_register(&at91_lcdc_device);
783}
784#else
785void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
786#endif
787
788
789/* --------------------------------------------------------------------
790 * Timer/Counter block
791 * -------------------------------------------------------------------- */
792
793#ifdef CONFIG_ATMEL_TCLIB
794static struct resource tcb0_resources[] = {
795 [0] = {
796 .start = AT91SAM9G45_BASE_TCB0,
797 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
798 .flags = IORESOURCE_MEM,
799 },
800 [1] = {
801 .start = AT91SAM9G45_ID_TCB,
802 .end = AT91SAM9G45_ID_TCB,
803 .flags = IORESOURCE_IRQ,
804 },
805};
806
807static struct platform_device at91sam9g45_tcb0_device = {
808 .name = "atmel_tcb",
809 .id = 0,
810 .resource = tcb0_resources,
811 .num_resources = ARRAY_SIZE(tcb0_resources),
812};
813
814/* TCB1 begins with TC3 */
815static struct resource tcb1_resources[] = {
816 [0] = {
817 .start = AT91SAM9G45_BASE_TCB1,
818 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
819 .flags = IORESOURCE_MEM,
820 },
821 [1] = {
822 .start = AT91SAM9G45_ID_TCB,
823 .end = AT91SAM9G45_ID_TCB,
824 .flags = IORESOURCE_IRQ,
825 },
826};
827
828static struct platform_device at91sam9g45_tcb1_device = {
829 .name = "atmel_tcb",
830 .id = 1,
831 .resource = tcb1_resources,
832 .num_resources = ARRAY_SIZE(tcb1_resources),
833};
834
835static void __init at91_add_device_tc(void)
836{
837 /* this chip has one clock and irq for all six TC channels */
ab64511c 838 at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
789b23bc 839 platform_device_register(&at91sam9g45_tcb0_device);
ab64511c 840 at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
789b23bc
NF		 841 platform_device_register(&at91sam9g45_tcb1_device);
842}
843#else
844static void __init at91_add_device_tc(void) { }
845#endif
846
847
848/* --------------------------------------------------------------------
849 * RTC
850 * -------------------------------------------------------------------- */
851
852#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
853static struct platform_device at91sam9g45_rtc_device = {
854 .name = "at91_rtc",
855 .id = -1,
856 .num_resources = 0,
857};
858
859static void __init at91_add_device_rtc(void)
860{
861 platform_device_register(&at91sam9g45_rtc_device);
862}
863#else
864static void __init at91_add_device_rtc(void) {}
865#endif
866
867
985f37f8
NF		 868/* --------------------------------------------------------------------
869 * Touchscreen
870 * -------------------------------------------------------------------- */
871
872#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
873static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
874static struct at91_tsadcc_data tsadcc_data;
875
876static struct resource tsadcc_resources[] = {
877 [0] = {
878 .start = AT91SAM9G45_BASE_TSC,
879 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
880 .flags = IORESOURCE_MEM,
881 },
882 [1] = {
883 .start = AT91SAM9G45_ID_TSC,
884 .end = AT91SAM9G45_ID_TSC,
885 .flags = IORESOURCE_IRQ,
886 }
887};
888
889static struct platform_device at91sam9g45_tsadcc_device = {
890 .name = "atmel_tsadcc",
891 .id = -1,
892 .dev = {
893 .dma_mask = &tsadcc_dmamask,
894 .coherent_dma_mask = DMA_BIT_MASK(32),
895 .platform_data = &tsadcc_data,
896 },
897 .resource = tsadcc_resources,
898 .num_resources = ARRAY_SIZE(tsadcc_resources),
899};
900
901void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
902{
903 if (!data)
904 return;
905
906 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
907 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
908 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
909 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
910
911 tsadcc_data = *data;
912 platform_device_register(&at91sam9g45_tsadcc_device);
913}
914#else
915void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
916#endif
917
918
789b23bc
NF		 919/* --------------------------------------------------------------------
920 * RTT
921 * -------------------------------------------------------------------- */
922
923static struct resource rtt_resources[] = {
924 {
925 .start = AT91_BASE_SYS + AT91_RTT,
926 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
927 .flags = IORESOURCE_MEM,
928 }
929};
930
931static struct platform_device at91sam9g45_rtt_device = {
932 .name = "at91_rtt",
933 .id = 0,
934 .resource = rtt_resources,
935 .num_resources = ARRAY_SIZE(rtt_resources),
936};
937
938static void __init at91_add_device_rtt(void)
939{
940 platform_device_register(&at91sam9g45_rtt_device);
941}
942
943
944/* --------------------------------------------------------------------
945 * Watchdog
946 * -------------------------------------------------------------------- */
947
4726374f 948#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
789b23bc
NF		 949static struct platform_device at91sam9g45_wdt_device = {
950 .name = "at91_wdt",
951 .id = -1,
952 .num_resources = 0,
953};
954
955static void __init at91_add_device_watchdog(void)
956{
957 platform_device_register(&at91sam9g45_wdt_device);
958}
959#else
960static void __init at91_add_device_watchdog(void) {}
961#endif
962
963
964/* --------------------------------------------------------------------
965 * PWM
966 * --------------------------------------------------------------------*/
967
968#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
969static u32 pwm_mask;
970
971static struct resource pwm_resources[] = {
972 [0] = {
973 .start = AT91SAM9G45_BASE_PWMC,
974 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
975 .flags = IORESOURCE_MEM,
976 },
977 [1] = {
978 .start = AT91SAM9G45_ID_PWMC,
979 .end = AT91SAM9G45_ID_PWMC,
980 .flags = IORESOURCE_IRQ,
981 },
982};
983
984static struct platform_device at91sam9g45_pwm0_device = {
985 .name = "atmel_pwm",
986 .id = -1,
987 .dev = {
988 .platform_data = &pwm_mask,
989 },
990 .resource = pwm_resources,
991 .num_resources = ARRAY_SIZE(pwm_resources),
992};
993
994void __init at91_add_device_pwm(u32 mask)
995{
996 if (mask & (1 << AT91_PWM0))
997 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
998
999 if (mask & (1 << AT91_PWM1))
1000 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1001
1002 if (mask & (1 << AT91_PWM2))
1003 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1004
1005 if (mask & (1 << AT91_PWM3))
1006 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1007
1008 pwm_mask = mask;
1009
1010 platform_device_register(&at91sam9g45_pwm0_device);
1011}
1012#else
1013void __init at91_add_device_pwm(u32 mask) {}
1014#endif
1015
1016
1017/* --------------------------------------------------------------------
1018 * SSC -- Synchronous Serial Controller
1019 * -------------------------------------------------------------------- */
1020
1021#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1022static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1023
1024static struct resource ssc0_resources[] = {
1025 [0] = {
1026 .start = AT91SAM9G45_BASE_SSC0,
1027 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1028 .flags = IORESOURCE_MEM,
1029 },
1030 [1] = {
1031 .start = AT91SAM9G45_ID_SSC0,
1032 .end = AT91SAM9G45_ID_SSC0,
1033 .flags = IORESOURCE_IRQ,
1034 },
1035};
1036
1037static struct platform_device at91sam9g45_ssc0_device = {
1038 .name = "ssc",
1039 .id = 0,
1040 .dev = {
1041 .dma_mask = &ssc0_dmamask,
1042 .coherent_dma_mask = DMA_BIT_MASK(32),
1043 },
1044 .resource = ssc0_resources,
1045 .num_resources = ARRAY_SIZE(ssc0_resources),
1046};
1047
1048static inline void configure_ssc0_pins(unsigned pins)
1049{
1050 if (pins & ATMEL_SSC_TF)
1051 at91_set_A_periph(AT91_PIN_PD1, 1);
1052 if (pins & ATMEL_SSC_TK)
1053 at91_set_A_periph(AT91_PIN_PD0, 1);
1054 if (pins & ATMEL_SSC_TD)
1055 at91_set_A_periph(AT91_PIN_PD2, 1);
1056 if (pins & ATMEL_SSC_RD)
1057 at91_set_A_periph(AT91_PIN_PD3, 1);
1058 if (pins & ATMEL_SSC_RK)
1059 at91_set_A_periph(AT91_PIN_PD4, 1);
1060 if (pins & ATMEL_SSC_RF)
1061 at91_set_A_periph(AT91_PIN_PD5, 1);
1062}
1063
1064static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1065
1066static struct resource ssc1_resources[] = {
1067 [0] = {
1068 .start = AT91SAM9G45_BASE_SSC1,
1069 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1070 .flags = IORESOURCE_MEM,
1071 },
1072 [1] = {
1073 .start = AT91SAM9G45_ID_SSC1,
1074 .end = AT91SAM9G45_ID_SSC1,
1075 .flags = IORESOURCE_IRQ,
1076 },
1077};
1078
1079static struct platform_device at91sam9g45_ssc1_device = {
1080 .name = "ssc",
1081 .id = 1,
1082 .dev = {
1083 .dma_mask = &ssc1_dmamask,
1084 .coherent_dma_mask = DMA_BIT_MASK(32),
1085 },
1086 .resource = ssc1_resources,
1087 .num_resources = ARRAY_SIZE(ssc1_resources),
1088};
1089
1090static inline void configure_ssc1_pins(unsigned pins)
1091{
1092 if (pins & ATMEL_SSC_TF)
1093 at91_set_A_periph(AT91_PIN_PD14, 1);
1094 if (pins & ATMEL_SSC_TK)
1095 at91_set_A_periph(AT91_PIN_PD12, 1);
1096 if (pins & ATMEL_SSC_TD)
1097 at91_set_A_periph(AT91_PIN_PD10, 1);
1098 if (pins & ATMEL_SSC_RD)
1099 at91_set_A_periph(AT91_PIN_PD11, 1);
1100 if (pins & ATMEL_SSC_RK)
1101 at91_set_A_periph(AT91_PIN_PD13, 1);
1102 if (pins & ATMEL_SSC_RF)
1103 at91_set_A_periph(AT91_PIN_PD15, 1);
1104}
1105
1106/*
1107 * SSC controllers are accessed through library code, instead of any
1108 * kind of all-singing/all-dancing driver. For example one could be
1109 * used by a particular I2S audio codec's driver, while another one
1110 * on the same system might be used by a custom data capture driver.
1111 */
1112void __init at91_add_device_ssc(unsigned id, unsigned pins)
1113{
1114 struct platform_device *pdev;
1115
1116 /*
1117 * NOTE: caller is responsible for passing information matching
1118 * "pins" to whatever will be using each particular controller.
1119 */
1120 switch (id) {
1121 case AT91SAM9G45_ID_SSC0:
1122 pdev = &at91sam9g45_ssc0_device;
1123 configure_ssc0_pins(pins);
1124 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1125 break;
1126 case AT91SAM9G45_ID_SSC1:
1127 pdev = &at91sam9g45_ssc1_device;
1128 configure_ssc1_pins(pins);
1129 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1130 break;
1131 default:
1132 return;
1133 }
1134
1135 platform_device_register(pdev);
1136}
1137
1138#else
1139void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1140#endif
1141
1142
1143/* --------------------------------------------------------------------
1144 * UART
1145 * -------------------------------------------------------------------- */
1146
1147#if defined(CONFIG_SERIAL_ATMEL)
1148static struct resource dbgu_resources[] = {
1149 [0] = {
1150 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1151 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1152 .flags = IORESOURCE_MEM,
1153 },
1154 [1] = {
1155 .start = AT91_ID_SYS,
1156 .end = AT91_ID_SYS,
1157 .flags = IORESOURCE_IRQ,
1158 },
1159};
1160
1161static struct atmel_uart_data dbgu_data = {
1162 .use_dma_tx = 0,
1163 .use_dma_rx = 0,
1164 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1165};
1166
1167static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1168
1169static struct platform_device at91sam9g45_dbgu_device = {
1170 .name = "atmel_usart",
1171 .id = 0,
1172 .dev = {
1173 .dma_mask = &dbgu_dmamask,
1174 .coherent_dma_mask = DMA_BIT_MASK(32),
1175 .platform_data = &dbgu_data,
1176 },
1177 .resource = dbgu_resources,
1178 .num_resources = ARRAY_SIZE(dbgu_resources),
1179};
1180
1181static inline void configure_dbgu_pins(void)
1182{
1183 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1184 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1185}
1186
1187static struct resource uart0_resources[] = {
1188 [0] = {
1189 .start = AT91SAM9G45_BASE_US0,
1190 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1191 .flags = IORESOURCE_MEM,
1192 },
1193 [1] = {
1194 .start = AT91SAM9G45_ID_US0,
1195 .end = AT91SAM9G45_ID_US0,
1196 .flags = IORESOURCE_IRQ,
1197 },
1198};
1199
1200static struct atmel_uart_data uart0_data = {
1201 .use_dma_tx = 1,
1202 .use_dma_rx = 1,
1203};
1204
1205static u64 uart0_dmamask = DMA_BIT_MASK(32);
1206
1207static struct platform_device at91sam9g45_uart0_device = {
1208 .name = "atmel_usart",
1209 .id = 1,
1210 .dev = {
1211 .dma_mask = &uart0_dmamask,
1212 .coherent_dma_mask = DMA_BIT_MASK(32),
1213 .platform_data = &uart0_data,
1214 },
1215 .resource = uart0_resources,
1216 .num_resources = ARRAY_SIZE(uart0_resources),
1217};
1218
1219static inline void configure_usart0_pins(unsigned pins)
1220{
1221 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1222 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1223
1224 if (pins & ATMEL_UART_RTS)
1225 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1226 if (pins & ATMEL_UART_CTS)
1227 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1228}
1229
1230static struct resource uart1_resources[] = {
1231 [0] = {
1232 .start = AT91SAM9G45_BASE_US1,
1233 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1234 .flags = IORESOURCE_MEM,
1235 },
1236 [1] = {
1237 .start = AT91SAM9G45_ID_US1,
1238 .end = AT91SAM9G45_ID_US1,
1239 .flags = IORESOURCE_IRQ,
1240 },
1241};
1242
1243static struct atmel_uart_data uart1_data = {
1244 .use_dma_tx = 1,
1245 .use_dma_rx = 1,
1246};
1247
1248static u64 uart1_dmamask = DMA_BIT_MASK(32);
1249
1250static struct platform_device at91sam9g45_uart1_device = {
1251 .name = "atmel_usart",
1252 .id = 2,
1253 .dev = {
1254 .dma_mask = &uart1_dmamask,
1255 .coherent_dma_mask = DMA_BIT_MASK(32),
1256 .platform_data = &uart1_data,
1257 },
1258 .resource = uart1_resources,
1259 .num_resources = ARRAY_SIZE(uart1_resources),
1260};
1261
1262static inline void configure_usart1_pins(unsigned pins)
1263{
1264 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1265 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1266
1267 if (pins & ATMEL_UART_RTS)
1268 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1269 if (pins & ATMEL_UART_CTS)
1270 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1271}
1272
1273static struct resource uart2_resources[] = {
1274 [0] = {
1275 .start = AT91SAM9G45_BASE_US2,
1276 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1277 .flags = IORESOURCE_MEM,
1278 },
1279 [1] = {
1280 .start = AT91SAM9G45_ID_US2,
1281 .end = AT91SAM9G45_ID_US2,
1282 .flags = IORESOURCE_IRQ,
1283 },
1284};
1285
1286static struct atmel_uart_data uart2_data = {
1287 .use_dma_tx = 1,
1288 .use_dma_rx = 1,
1289};
1290
1291static u64 uart2_dmamask = DMA_BIT_MASK(32);
1292
1293static struct platform_device at91sam9g45_uart2_device = {
1294 .name = "atmel_usart",
1295 .id = 3,
1296 .dev = {
1297 .dma_mask = &uart2_dmamask,
1298 .coherent_dma_mask = DMA_BIT_MASK(32),
1299 .platform_data = &uart2_data,
1300 },
1301 .resource = uart2_resources,
1302 .num_resources = ARRAY_SIZE(uart2_resources),
1303};
1304
1305static inline void configure_usart2_pins(unsigned pins)
1306{
1307 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1308 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1309
1310 if (pins & ATMEL_UART_RTS)
1311 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1312 if (pins & ATMEL_UART_CTS)
1313 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1314}
1315
1316static struct resource uart3_resources[] = {
1317 [0] = {
1318 .start = AT91SAM9G45_BASE_US3,
1319 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1320 .flags = IORESOURCE_MEM,
1321 },
1322 [1] = {
1323 .start = AT91SAM9G45_ID_US3,
1324 .end = AT91SAM9G45_ID_US3,
1325 .flags = IORESOURCE_IRQ,
1326 },
1327};
1328
1329static struct atmel_uart_data uart3_data = {
1330 .use_dma_tx = 1,
1331 .use_dma_rx = 1,
1332};
1333
1334static u64 uart3_dmamask = DMA_BIT_MASK(32);
1335
1336static struct platform_device at91sam9g45_uart3_device = {
1337 .name = "atmel_usart",
1338 .id = 4,
1339 .dev = {
1340 .dma_mask = &uart3_dmamask,
1341 .coherent_dma_mask = DMA_BIT_MASK(32),
1342 .platform_data = &uart3_data,
1343 },
1344 .resource = uart3_resources,
1345 .num_resources = ARRAY_SIZE(uart3_resources),
1346};
1347
1348static inline void configure_usart3_pins(unsigned pins)
1349{
1350 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1351 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1352
1353 if (pins & ATMEL_UART_RTS)
1354 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1355 if (pins & ATMEL_UART_CTS)
1356 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1357}
1358
1359static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1360struct platform_device *atmel_default_console_device; /* the serial console device */
1361
1362void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1363{
1364 struct platform_device *pdev;
1365
1366 switch (id) {
1367 case 0: /* DBGU */
1368 pdev = &at91sam9g45_dbgu_device;
1369 configure_dbgu_pins();
1370 at91_clock_associate("mck", &pdev->dev, "usart");
1371 break;
1372 case AT91SAM9G45_ID_US0:
1373 pdev = &at91sam9g45_uart0_device;
1374 configure_usart0_pins(pins);
1375 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1376 break;
1377 case AT91SAM9G45_ID_US1:
1378 pdev = &at91sam9g45_uart1_device;
1379 configure_usart1_pins(pins);
1380 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1381 break;
1382 case AT91SAM9G45_ID_US2:
1383 pdev = &at91sam9g45_uart2_device;
1384 configure_usart2_pins(pins);
1385 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1386 break;
1387 case AT91SAM9G45_ID_US3:
1388 pdev = &at91sam9g45_uart3_device;
1389 configure_usart3_pins(pins);
1390 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1391 break;
1392 default:
1393 return;
1394 }
1395 pdev->id = portnr; /* update to mapped ID */
1396
1397 if (portnr < ATMEL_MAX_UART)
1398 at91_uarts[portnr] = pdev;
1399}
1400
1401void __init at91_set_serial_console(unsigned portnr)
1402{
1403 if (portnr < ATMEL_MAX_UART)
1404 atmel_default_console_device = at91_uarts[portnr];
1405}
1406
1407void __init at91_add_device_serial(void)
1408{
1409 int i;
1410
1411 for (i = 0; i < ATMEL_MAX_UART; i++) {
1412 if (at91_uarts[i])
1413 platform_device_register(at91_uarts[i]);
1414 }
1415
1416 if (!atmel_default_console_device)
1417 printk(KERN_INFO "AT91: No default serial console defined.\n");
1418}
1419#else
1420void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1421void __init at91_set_serial_console(unsigned portnr) {}
1422void __init at91_add_device_serial(void) {}
1423#endif
1424
1425
1426/* -------------------------------------------------------------------- */
1427/*
1428 * These devices are always present and don't need any board-specific
1429 * setup.
1430 */
1431static int __init at91_add_standard_devices(void)
1432{
40262b2b 1433 at91_add_device_hdmac();
789b23bc
NF		 1434 at91_add_device_rtc();
1435 at91_add_device_rtt();
1436 at91_add_device_watchdog();
1437 at91_add_device_tc();
1438 return 0;
1439}
1440
1441arch_initcall(at91_add_standard_devices);
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