[net-next-2.6.git] / Documentation / Intel-IOMMU.txt

Linux IOMMU Support
===================

The architecture spec can be obtained from the below location.

http://www.intel.com/technology/virtualization/

This guide gives a quick cheat sheet for some basic understanding.

Some Keywords

DMAR - DMA remapping
DRHD - DMA Engine Reporting Structure
RMRR - Reserved memory Region Reporting Structure
ZLR  - Zero length reads from PCI devices
IOVA - IO Virtual address.

Basic stuff
-----------

ACPI enumerates and lists the different DMA engines in the platform, and
device scope relationships between PCI devices and which DMA engine  controls
them.

What is RMRR?
-------------

There are some devices the BIOS controls, for e.g USB devices to perform
PS2 emulation. The regions of memory used for these devices are marked
reserved in the e820 map. When we turn on DMA translation, DMA to those
regions will fail. Hence BIOS uses RMRR to specify these regions along with
devices that need to access these regions. OS is expected to setup
unity mappings for these regions for these devices to access these regions.

How is IOVA generated?
---------------------

Well behaved drivers call pci_map_*() calls before sending command to device
that needs to perform DMA. Once DMA is completed and mapping is no longer
required, device performs a pci_unmap_*() calls to unmap the region.

The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
device has its own domain (hence protection). Devices under p2p bridges
share the virtual address with all devices under the p2p bridge due to
transaction id aliasing for p2p bridges.

IOVA generation is pretty generic. We used the same technique as vmalloc()
but these are not global address spaces, but separate for each domain.
Different DMA engines may support different number of domains.

We also allocate gaurd pages with each mapping, so we can attempt to catch
any overflow that might happen.


Graphics Problems?
------------------
If you encounter issues with graphics devices, you can try adding
option intel_iommu=igfx_off to turn off the integrated graphics engine.

Some exceptions to IOVA
-----------------------
Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
The same is true for peer to peer transactions. Hence we reserve the
address from PCI MMIO ranges so they are not allocated for IOVA addresses.


Fault reporting
---------------
When errors are reported, the DMA engine signals via an interrupt. The fault
reason and device that caused it with fault reason is printed on console.

See below for sample.


Boot Message Sample
-------------------

Something like this gets printed indicating presence of DMAR tables
in ACPI.

ACPI: DMAR (v001 A M I  OEMDMAR  0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0

When DMAR is being processed and initialized by ACPI, prints DMAR locations
and any RMRR's processed.

ACPI DMAR:Host address width 36
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff

When DMAR is enabled for use, you will notice..

PCI-DMA: Using DMAR IOMMU

Fault reporting
---------------

DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
DMAR:[fault reason 05] PTE Write access is not set
DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
DMAR:[fault reason 05] PTE Write access is not set

TBD
----

- For compatibility testing, could use unity map domain for all devices, just
  provide a 1-1 for all useful memory under a single domain for all devices.
- API for paravirt ops for abstracting functionlity for VMM folks.
Commit	Line	Data
ba395927 KA	1	Linux IOMMU Support
	2	===================
	3
	4	The architecture spec can be obtained from the below location.
	5
	6	http://www.intel.com/technology/virtualization/
	7
	8	This guide gives a quick cheat sheet for some basic understanding.
	9
	10	Some Keywords
	11
	12	DMAR - DMA remapping
	13	DRHD - DMA Engine Reporting Structure
	14	RMRR - Reserved memory Region Reporting Structure
	15	ZLR - Zero length reads from PCI devices
	16	IOVA - IO Virtual address.
	17
	18	Basic stuff
	19	-----------
	20
	21	ACPI enumerates and lists the different DMA engines in the platform, and
	22	device scope relationships between PCI devices and which DMA engine controls
	23	them.
	24
	25	What is RMRR?
	26	-------------
	27
	28	There are some devices the BIOS controls, for e.g USB devices to perform
	29	PS2 emulation. The regions of memory used for these devices are marked
	30	reserved in the e820 map. When we turn on DMA translation, DMA to those
	31	regions will fail. Hence BIOS uses RMRR to specify these regions along with
	32	devices that need to access these regions. OS is expected to setup
	33	unity mappings for these regions for these devices to access these regions.
	34
	35	How is IOVA generated?
	36	---------------------
	37
	38	Well behaved drivers call pci_map_*() calls before sending command to device
	39	that needs to perform DMA. Once DMA is completed and mapping is no longer
	40	required, device performs a pci_unmap_*() calls to unmap the region.
	41
	42	The Intel IOMMU driver allocates a virtual address per domain. Each PCIE
	43	device has its own domain (hence protection). Devices under p2p bridges
	44	share the virtual address with all devices under the p2p bridge due to
	45	transaction id aliasing for p2p bridges.
	46
	47	IOVA generation is pretty generic. We used the same technique as vmalloc()
	48	but these are not global address spaces, but separate for each domain.
	49	Different DMA engines may support different number of domains.
	50
	51	We also allocate gaurd pages with each mapping, so we can attempt to catch
	52	any overflow that might happen.
	53
	54
	55	Graphics Problems?
	56	------------------
	57	If you encounter issues with graphics devices, you can try adding
	58	option intel_iommu=igfx_off to turn off the integrated graphics engine.
	59
	60	Some exceptions to IOVA
	61	-----------------------
	62	Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
	63	The same is true for peer to peer transactions. Hence we reserve the
	64	address from PCI MMIO ranges so they are not allocated for IOVA addresses.
65
3460a6d9 KA	66
	67	Fault reporting
	68	---------------
	69	When errors are reported, the DMA engine signals via an interrupt. The fault
	70	reason and device that caused it with fault reason is printed on console.
	71
	72	See below for sample.
	73
	74
ba395927 KA	75	Boot Message Sample
	76	-------------------
	77
	78	Something like this gets printed indicating presence of DMAR tables
	79	in ACPI.
	80
	81	ACPI: DMAR (v001 A M I OEMDMAR 0x00000001 MSFT 0x00000097) @ 0x000000007f5b5ef0
	82
	83	When DMAR is being processed and initialized by ACPI, prints DMAR locations
	84	and any RMRR's processed.
	85
	86	ACPI DMAR:Host address width 36
	87	ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed90000
	88	ACPI DMAR:DRHD (flags: 0x00000000)base: 0x00000000fed91000
	89	ACPI DMAR:DRHD (flags: 0x00000001)base: 0x00000000fed93000
	90	ACPI DMAR:RMRR base: 0x00000000000ed000 end: 0x00000000000effff
	91	ACPI DMAR:RMRR base: 0x000000007f600000 end: 0x000000007fffffff
	92
	93	When DMAR is enabled for use, you will notice..
	94
	95	PCI-DMA: Using DMAR IOMMU
	96
3460a6d9 KA	97	Fault reporting
	98	---------------
	99
	100	DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
	101	DMAR:[fault reason 05] PTE Write access is not set
	102	DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
	103	DMAR:[fault reason 05] PTE Write access is not set
	104
ba395927 KA	105	TBD
	106	----
	107
	108	- For compatibility testing, could use unity map domain for all devices, just
	109	provide a 1-1 for all useful memory under a single domain for all devices.
	110	- API for paravirt ops for abstracting functionlity for VMM folks.