X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=f863aee6648b49b0db38d2cdc077640669a2a424;hp=317a28e7a02548a02b51a2e7a4191c553ce92a83;hb=9b9d55dee3e9b742a52ce6934770baaf1168d72f;hpb=cd0ff491e3c0fdb01fb189987c4d822b1113cc53

diff --git a/jme.h b/jme.h
index 317a28e..f863aee 100644
--- a/jme.h
+++ b/jme.h
@@ -25,7 +25,7 @@
 #define __JME_H_INCLUDEE__
 
 #define DRV_NAME	"jme"
-#define DRV_VERSION	"1.0"
+#define DRV_VERSION	"1.0.3"
 #define PFX		DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250	0x0250
@@ -444,7 +444,7 @@ struct jme_adapter {
 	u32			rx_ring_mask;
 	u8			mrrs;
 	unsigned int		fpgaver;
-	unsigned int		chipver;
+	unsigned int		chiprev;
 	u8			rev;
 	u32			msg_enable;
 	struct ethtool_cmd	old_ecmd;
@@ -963,6 +963,36 @@ enum jme_gpreg0_vals {
 				  GPREG0_PHYADDR_1,
 };
 
+/*
+ * General Purpose REG-1
+ * Note: All theses bits defined here are for
+ *       Chip mode revision 0x11 only
+ */
+enum jme_gpreg1_masks {
+	GPREG1_INTRDELAYUNIT	= 0x00000018,
+	GPREG1_INTRDELAYENABLE	= 0x00000007,
+};
+
+enum jme_gpreg1_vals {
+	GPREG1_RSSPATCH		= 0x00000040,
+	GPREG1_HALFMODEPATCH	= 0x00000020,
+
+	GPREG1_INTDLYUNIT_16NS	= 0x00000000,
+	GPREG1_INTDLYUNIT_256NS	= 0x00000008,
+	GPREG1_INTDLYUNIT_1US	= 0x00000010,
+	GPREG1_INTDLYUNIT_16US	= 0x00000018,
+
+	GPREG1_INTDLYEN_1U	= 0x00000001,
+	GPREG1_INTDLYEN_2U	= 0x00000002,
+	GPREG1_INTDLYEN_3U	= 0x00000003,
+	GPREG1_INTDLYEN_4U	= 0x00000004,
+	GPREG1_INTDLYEN_5U	= 0x00000005,
+	GPREG1_INTDLYEN_6U	= 0x00000006,
+	GPREG1_INTDLYEN_7U	= 0x00000007,
+
+	GPREG1_DEFAULT		= 0x00000000,
+};
+
 /*
  * Interrupt Status Bits
  */
@@ -1050,13 +1080,13 @@ enum jme_pcctx_bits {
  */
 enum jme_chipmode_bit_masks {
 	CM_FPGAVER_MASK		= 0xFFFF0000,
-	CM_CHIPVER_MASK		= 0x0000FF00,
+	CM_CHIPREV_MASK		= 0x0000FF00,
 	CM_CHIPMODE_MASK	= 0x0000000F,
 };
 
 enum jme_chipmode_shifts {
 	CM_FPGAVER_SHIFT	= 16,
-	CM_CHIPVER_SHIFT	= 8,
+	CM_CHIPREV_SHIFT	= 8,
 };
 
 /*
@@ -1092,12 +1122,14 @@ static char *MAC_REG_NAME[] = {
 	"JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
 	"JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
 	"JME_PMCS"};
+
 static char *PE_REG_NAME[] = {
 	"UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
 	"UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
 	"UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
 	"JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
 	"JME_SMBCSR",   "JME_SMBINTF"};
+
 static char *MISC_REG_NAME[] = {
 	"JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
 	"JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
@@ -1108,11 +1140,12 @@ static char *MISC_REG_NAME[] = {
 	"UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
 	"JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
 	"JME_PCCSRX0"};
+
 static inline void reg_dbg(const struct jme_adapter *jme,
 		const char *msg, u32 val, u32 reg)
 {
 	const char *regname;
-	switch(reg & 0xF00) {
+	switch (reg & 0xF00) {
 	case 0x000:
 		regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
 		break;
@@ -1120,7 +1153,7 @@ static inline void reg_dbg(const struct jme_adapter *jme,
 		regname = PE_REG_NAME[(reg & 0xFF) >> 2];
 		break;
 	case 0x800:
-		regname = MISC_REG_NAME[(reg & 0xFF) >>2];
+		regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
 		break;
 	default:
 		regname = PE_REG_NAME[0];
@@ -1178,6 +1211,14 @@ enum jme_phy_reg17_vals {
 
 #define BMSR_ANCOMP               0x0020
 
+/*
+ * Workaround
+ */
+static inline int is_buggy250(unsigned short device, unsigned int chiprev)
+{
+	return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
+}
+
 /*
  * Function prototypes
  */