X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=cc060200355b2790f644b1c20de60baff64c20c2;hp=a24cad1cd1c530a487f090bb47ef1d33debf3491;hb=d3d9c4123d1393421a84626ba40e6d925df6bdc1;hpb=ed457bcc95e7b5ce1eef28712b305f5f36788ac1

diff --git a/jme.h b/jme.h
index a24cad1..cc06020 100644
--- a/jme.h
+++ b/jme.h
@@ -24,9 +24,10 @@
 
 #ifndef __JME_H_INCLUDED__
 #define __JME_H_INCLUDED__
+#include <linux/interrupt.h>
 
 #define DRV_NAME	"jme"
-#define DRV_VERSION	"1.0.7-jmmod"
+#define DRV_VERSION	"1.0.8.9-jmmod-noasd"
 #define PFX		DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250	0x0250
@@ -42,11 +43,11 @@
 	NETIF_MSG_TX_ERR | \
 	NETIF_MSG_HW)
 
-#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
+#ifndef pr_err
 #define pr_err(fmt, arg...) \
 	printk(KERN_ERR fmt, ##arg)
 #endif
-#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
+#ifndef netdev_err
 #define netdev_err(netdev, fmt, arg...) \
 	pr_err(fmt, ##arg)
 #endif
@@ -94,11 +95,15 @@ do {									\
 #define msg_hw(priv, fmt, args...) \
 	jme_msg(KERN_ERR, hw, priv, fmt, ## args)
 
+#ifndef netif_info
 #define netif_info(priv, type, dev, fmt, args...) \
 	msg_ ## type(priv, fmt, ## args)
+#endif
+#ifndef netif_err
 #define netif_err(priv, type, dev, fmt, args...) \
 	msg_ ## type(priv, fmt, ## args)
 #endif
+#endif
 
 #ifndef NETIF_F_TSO6
 #define NETIF_F_TSO6 0
@@ -107,6 +112,27 @@ do {									\
 #define NETIF_F_IPV6_CSUM 0
 #endif
 
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
+#define __NO_BOOL__
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
+#define __USE_NDO_FIX_FEATURES__
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,1,0)
+#define __UNIFY_VLAN_RX_PATH__
+#define __USE_NDO_SET_RX_MODE__
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+#define __USE_SKB_FRAG_API__
+#endif
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)
+#define __NEW_FIX_FEATURES_TYPE__
+#endif
+
 /*
  * Extra PCI Configuration space interface
  */
@@ -155,7 +181,6 @@ enum jme_spi_op_bits {
 };
 
 #define HALF_US 500	/* 500 ns */
-#define JMESPIIOCTL	SIOCDEVPRIVATE
 
 #define PCI_PRIV_PE1		0xE4
 
@@ -461,10 +486,10 @@ struct jme_ring {
 	netdev->get_stats = fun_ptr
 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 /*
- * CentOS 5.5 have *_hdr helpers back-ported
+ * CentOS 5.2 have *_hdr helpers back-ported
  */
 #ifdef RHEL_RELEASE_CODE
-#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,5)
+#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
 #define __DEFINE_IPHDR_HELPERS__
 #endif
 #else
@@ -530,6 +555,17 @@ static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
 	__napi_schedule(&priv->napi);
 #endif
 
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
+#define JME_NEW_PM_API
+#endif
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
+static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
+{
+	return ep->speed;
+}
+#endif
+
 /*
  * Jmac Adapter Private data
  */
@@ -555,6 +591,7 @@ struct jme_adapter {
 	u32			reg_rxmcs;
 	u32			reg_ghc;
 	u32			reg_pmcs;
+	u32			reg_gpreg1;
 	u32			phylink;
 	u32			tx_ring_size;
 	u32			tx_ring_mask;
@@ -570,7 +607,9 @@ struct jme_adapter {
 	u32			msg_enable;
 	struct ethtool_cmd	old_ecmd;
 	unsigned int		old_mtu;
+#ifndef __UNIFY_VLAN_RX_PATH__
 	struct vlan_group	*vlgrp;
+#endif
 	struct dynpcc_info	dpi;
 	atomic_t		intr_sem;
 	atomic_t		link_changing;
@@ -578,9 +617,11 @@ struct jme_adapter {
 	atomic_t		rx_cleaning;
 	atomic_t		rx_empty;
 	int			(*jme_rx)(struct sk_buff *skb);
+#ifndef __UNIFY_VLAN_RX_PATH__
 	int			(*jme_vlan_rx)(struct sk_buff *skb,
 					  struct vlan_group *grp,
 					  unsigned short vlan_tag);
+#endif
 	DECLARE_NAPI_STRUCT
 	DECLARE_NET_DEVICE_STATS
 };
@@ -597,8 +638,10 @@ jme_get_stats(struct net_device *netdev)
 enum jme_flags_bits {
 	JME_FLAG_MSI		= 1,
 	JME_FLAG_SSET		= 2,
+#ifndef __USE_NDO_FIX_FEATURES__
 	JME_FLAG_TXCSUM		= 3,
 	JME_FLAG_TSO		= 4,
+#endif
 	JME_FLAG_POLL		= 5,
 	JME_FLAG_SHUTDOWN	= 6,
 };
@@ -798,6 +841,14 @@ enum jme_txtrhd_shifts {
 	TXTRHD_TXRL_SHIFT	= 0,
 };
 
+enum jme_txtrhd_values {
+	TXTRHD_FULLDUPLEX	= 0x00000000,
+	TXTRHD_HALFDUPLEX	= TXTRHD_TXPEN |
+				  ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
+				  TXTRHD_TXREN |
+				  ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
+};
+
 /*
  * RX Control/Status Bits
  */
@@ -867,7 +918,7 @@ enum jme_rxcs_values {
 	RXCS_RETRYCNT_60	= 0x00000F00,
 
 	RXCS_DEFAULT		= RXCS_FIFOTHTP_128T |
-				  RXCS_FIFOTHNP_128QW |
+				  RXCS_FIFOTHNP_16QW |
 				  RXCS_DMAREQSZ_128B |
 				  RXCS_RETRYGAP_256ns |
 				  RXCS_RETRYCNT_32,
@@ -897,6 +948,25 @@ enum jme_rxmcs_bits {
 				  RXMCS_CHECKSUM,
 };
 
+/*	Extern PHY common register 2	*/
+
+#define PHY_GAD_TEST_MODE_1			0x00002000
+#define PHY_GAD_TEST_MODE_MSK			0x0000E000
+#define JM_PHY_SPEC_REG_READ			0x00004000
+#define JM_PHY_SPEC_REG_WRITE			0x00008000
+#define PHY_CALIBRATION_DELAY			20
+#define JM_PHY_SPEC_ADDR_REG			0x1E
+#define JM_PHY_SPEC_DATA_REG			0x1F
+
+#define JM_PHY_EXT_COMM_0_REG			0x30
+#define JM_PHY_EXT_COMM_1_REG			0x31
+#define JM_PHY_EXT_COMM_2_REG			0x32
+#define JM_PHY_EXT_COMM_2_CALI_ENABLE		0x01
+#define JM_PHY_EXT_COMM_2_CALI_MODE_0		0x02
+#define JM_PHY_EXT_COMM_2_CALI_LATCH		0x10
+#define PCI_PRIV_SHARE_NICCTRL			0xF5
+#define JME_FLAG_PHYEA_ENABLE			0x2
+
 /*
  * Wakeup Frame setup interface registers
  */
@@ -953,6 +1023,8 @@ static inline u32 smi_phy_addr(int x)
  */
 enum jme_ghc_bit_mask {
 	GHC_SWRST		= 0x40000000,
+	GHC_TO_CLK_SRC		= 0x00C00000,
+	GHC_TXMAC_CLK_SRC	= 0x00300000,
 	GHC_DPX			= 0x00000040,
 	GHC_SPEED		= 0x00000030,
 	GHC_LINK_POLL		= 0x00000001,
@@ -982,6 +1054,7 @@ enum jme_ghc_txmac_clk {
  * Power management control and status register
  */
 enum jme_pmcs_bit_masks {
+	PMCS_STMASK	= 0xFFFF0000,
 	PMCS_WF7DET	= 0x80000000,
 	PMCS_WF6DET	= 0x40000000,
 	PMCS_WF5DET	= 0x20000000,
@@ -993,6 +1066,7 @@ enum jme_pmcs_bit_masks {
 	PMCS_LFDET	= 0x00040000,
 	PMCS_LRDET	= 0x00020000,
 	PMCS_MFDET	= 0x00010000,
+	PMCS_ENMASK	= 0x0000FFFF,
 	PMCS_WF7EN	= 0x00008000,
 	PMCS_WF6EN	= 0x00004000,
 	PMCS_WF5EN	= 0x00002000,
@@ -1131,18 +1205,17 @@ enum jme_gpreg0_vals {
 
 /*
  * General Purpose REG-1
- * Note: All theses bits defined here are for
- *       Chip mode revision 0x11 only
  */
-enum jme_gpreg1_masks {
+enum jme_gpreg1_bit_masks {
+	GPREG1_RXCLKOFF		= 0x04000000,
+	GPREG1_PCREQN		= 0x00020000,
+	GPREG1_HALFMODEPATCH	= 0x00000040, /* For Chip revision 0x11 only */
+	GPREG1_RSSPATCH		= 0x00000020, /* For Chip revision 0x11 only */
 	GPREG1_INTRDELAYUNIT	= 0x00000018,
 	GPREG1_INTRDELAYENABLE	= 0x00000007,
 };
 
 enum jme_gpreg1_vals {
-	GPREG1_RSSPATCH		= 0x00000040,
-	GPREG1_HALFMODEPATCH	= 0x00000020,
-
 	GPREG1_INTDLYUNIT_16NS	= 0x00000000,
 	GPREG1_INTDLYUNIT_256NS	= 0x00000008,
 	GPREG1_INTDLYUNIT_1US	= 0x00000010,
@@ -1156,7 +1229,7 @@ enum jme_gpreg1_vals {
 	GPREG1_INTDLYEN_6U	= 0x00000006,
 	GPREG1_INTDLYEN_7U	= 0x00000007,
 
-	GPREG1_DEFAULT		= 0x00000000,
+	GPREG1_DEFAULT		= GPREG1_PCREQN,
 };
 
 /*
@@ -1388,6 +1461,7 @@ static inline int new_phy_power_ctrl(u8 chip_main_rev)
  */
 static int jme_set_settings(struct net_device *netdev,
 				struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
 static void jme_set_multi(struct net_device *netdev);
 
 #endif