X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=82f4cc6efdc5f2ef96b9ed8d30d4026b1169b4ee;hp=f048a8f7c4f09e1ea208589b738d8f48eb544aea;hb=192570e059855213a9e0010227fc6d1768be4a38;hpb=3bf61c55fb82b9c312d3ccf77c83eb23e4cdf437 diff --git a/jme.h b/jme.h index f048a8f..82f4cc6 100644 --- a/jme.h +++ b/jme.h @@ -24,12 +24,12 @@ #include #define DRV_NAME "jme" -#define DRV_VERSION "0.3" +#define DRV_VERSION "0.9a" #define PFX DRV_NAME ": " #ifdef DEBUG #define dprintk(devname, fmt, args...) \ - printk(KERN_DEBUG PFX "%s: " fmt, devname, ## args) + printk(KERN_DEBUG "%s: " fmt, devname, ## args) #else #define dprintk(devname, fmt, args...) #endif @@ -46,13 +46,29 @@ #define rx_dbg(args...) #endif +#ifdef QUEUE_DEBUG +#define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define queue_dbg(args...) +#endif + +#ifdef CSUM_DEBUG +#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define csum_dbg(args...) +#endif + +#ifdef VLAN_DEBUG +#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define vlan_dbg(args...) +#endif + #define jprintk(devname, fmt, args...) \ - printk(KERN_INFO PFX "%s: " fmt, devname, ## args) + printk(KERN_INFO "%s: " fmt, devname, ## args) #define jeprintk(devname, fmt, args...) \ - printk(KERN_ERR PFX "%s: " fmt, devname, ## args) - -#define USE_IEVE_SHADOW 0 + printk(KERN_ERR "%s: " fmt, devname, ## args) #define DEFAULT_MSG_ENABLE \ (NETIF_MSG_DRV | \ @@ -73,30 +89,40 @@ enum pci_conf_dcsr_mrrs_vals { MRRS_4096B = 0x50, }; +#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 +#define MIN_ETHERNET_PACKET_SIZE 60 + enum dynamic_pcc_values { + PCC_OFF = 0, PCC_P1 = 1, PCC_P2 = 2, PCC_P3 = 3, + PCC_OFF_TO = 0, PCC_P1_TO = 1, - PCC_P2_TO = 250, - PCC_P3_TO = 1000, + PCC_P2_TO = 64, + PCC_P3_TO = 128, + PCC_OFF_CNT = 0, PCC_P1_CNT = 1, - PCC_P2_CNT = 64, - PCC_P3_CNT = 255, + PCC_P2_CNT = 16, + PCC_P3_CNT = 32, }; struct dynpcc_info { - unsigned long check_point; unsigned long last_bytes; unsigned long last_pkts; + unsigned long intr_cnt; unsigned char cur; unsigned char attempt; unsigned char cnt; }; -#define PCC_INTERVAL (HZ / 10) +#define PCC_INTERVAL_US 100000 +#define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) #define PCC_P3_THRESHOLD 3*1024*1024 -#define PCC_P2_THRESHOLD 1000 +#define PCC_P2_THRESHOLD 800 +#define PCC_INTR_THRESHOLD 800 +#define PCC_TX_TO 333 +#define PCC_TX_CNT 8 /* * TX/RX Descriptors @@ -104,13 +130,11 @@ struct dynpcc_info { * TX/RX Ring DESC Count Must be multiple of 16 * RX Ring DESC Count Must be <= 1024 */ -#define RING_DESC_NR 512 /* Must be power of 2 */ #define RING_DESC_ALIGN 16 /* Descriptor alignment */ #define TX_DESC_SIZE 16 #define TX_RING_NR 8 -#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE -#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE) +#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN struct txdesc { union { @@ -149,9 +173,27 @@ struct txdesc { /* DW3 */ __u32 bufaddrl; } desc2; + struct { + /* DW0 */ + __u8 ehdrsz; + __u8 rsv1; + __u8 rsv2; + __u8 flags; + + /* DW1 */ + __u16 trycnt; + __u16 segcnt; + + /* DW2 */ + __u16 pktsz; + __u16 rsv3; + + /* DW3 */ + __u32 bufaddrl; + } descwb; }; }; -enum jme_txdesc_flag_bits { +enum jme_txdesc_flags_bits { TXFLAG_OWN = 0x80, TXFLAG_INT = 0x40, TXFLAG_64BIT = 0x20, @@ -161,23 +203,33 @@ enum jme_txdesc_flag_bits { TXFLAG_LSEN = 0x02, TXFLAG_TAGON = 0x01, }; +#define TXDESC_MSS_SHIFT 2 +enum jme_rxdescwb_flags_bits { + TXWBFLAG_OWN = 0x80, + TXWBFLAG_INT = 0x40, + TXWBFLAG_TMOUT = 0x20, + TXWBFLAG_TRYOUT = 0x10, + TXWBFLAG_COL = 0x08, + + TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | + TXWBFLAG_TRYOUT | + TXWBFLAG_COL, +}; #define RX_DESC_SIZE 16 #define RX_RING_NR 4 -#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE -#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE) +#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN #define RX_BUF_DMA_ALIGN 8 -//#define RX_BUF_SIZE 1600 -#define RX_BUF_SIZE 9200 -//#define RX_BUF_SIZE 4000 #define RX_PREPAD_SIZE 10 - -/* - * Will use mtu in the future - */ -#define RX_BUF_ALLOC_SIZE RX_BUF_SIZE + RX_BUF_DMA_ALIGN +#define ETH_CRC_LEN 2 +#define RX_VLANHDR_LEN 2 +#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ + ETH_HLEN + \ + ETH_CRC_LEN + \ + RX_VLANHDR_LEN + \ + RX_BUF_DMA_ALIGN) struct rxdesc { union { @@ -268,6 +320,7 @@ struct jme_buffer_info { int nr_desc; }; +#define MAX_RING_DESC_NR 1024 struct jme_ring { void* alloc; /* pointer to allocated memory */ volatile void* desc; /* pointer to ring memory */ @@ -275,12 +328,12 @@ struct jme_ring { dma_addr_t dma; /* phys address for ring dma */ /* Buffer information corresponding to each descriptor */ - struct jme_buffer_info bufinf[RING_DESC_NR]; + struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; - u16 next_to_use; - u16 next_to_clean; + int next_to_use; + int next_to_clean; - u16 nr_free; + atomic_t nr_free; }; #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) @@ -307,28 +360,53 @@ struct jme_adapter { struct mii_if_info mii_if; struct jme_ring rxring[RX_RING_NR]; struct jme_ring txring[TX_RING_NR]; - spinlock_t rx_lock; - spinlock_t tx_lock; spinlock_t phy_lock; + spinlock_t macaddr_lock; + spinlock_t rxmcs_lock; + struct tasklet_struct rxempty_task; struct tasklet_struct rxclean_task; struct tasklet_struct txclean_task; struct tasklet_struct linkch_task; + struct tasklet_struct pcc_task; __u32 flags; __u32 reg_txcs; + __u32 reg_txpfc; + __u32 reg_rxcs; __u32 reg_rxmcs; __u32 reg_ghc; + __u32 reg_pmcs; + __u32 phylink; + __u32 tx_ring_size; + __u32 tx_ring_mask; + __u32 tx_wake_threshold; + __u32 rx_ring_size; + __u32 rx_ring_mask; + __u8 mrrs; + struct ethtool_cmd old_ecmd; + unsigned int old_mtu; + struct vlan_group* vlgrp; struct dynpcc_info dpi; atomic_t intr_sem; + atomic_t link_changing; + atomic_t tx_cleaning; + atomic_t rx_cleaning; + atomic_t rx_empty; + struct napi_struct napi; DECLARE_NET_DEVICE_STATS }; enum shadow_reg_val { SHADOW_IEVE = 0, }; +enum jme_flags_bits { + JME_FLAG_MSI = 0x00000001, + JME_FLAG_SSET = 0x00000002, + JME_FLAG_TXCSUM = 0x00000004, + JME_FLAG_TSO = 0x00000008, + JME_FLAG_POLL = 0x00000010, +}; +#define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ +#define TX_TIMEOUT (5*HZ) -#define JME_FLAG_RXQ0_EMPTY 0x00000001 -#define JME_FLAG_RXQ1_EMPTY 0x00000002 -#define JME_FLAG_RXQ2_EMPTY 0x00000004 -#define JME_FLAG_RXQ3_EMPTY 0x00000008 /* * MMaped I/O Resters @@ -340,6 +418,13 @@ enum jme_iomap_offsets { JME_RSS = 0x0C00, }; +enum jme_iomap_lens { + JME_MAC_LEN = 0x80, + JME_PHY_LEN = 0x58, + JME_MISC_LEN = 0x98, + JME_RSS_LEN = 0xFF, +}; + enum jme_iomap_regs { JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ @@ -373,6 +458,7 @@ enum jme_iomap_regs { JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ + JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ @@ -426,7 +512,7 @@ enum jme_txcs_value { TXCS_DEFAULT = TXCS_FIFOTH_4QW | TXCS_BURST, }; -#define JME_TX_DISABLE_TIMEOUT 200 /* 200 usec */ +#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * TX MAC Control/Status Bits @@ -468,6 +554,23 @@ enum jme_txmcs_values { TXMCS_PADDING, }; +enum jme_txpfc_bits_masks { + TXPFC_VLAN_TAG = 0xFFFF0000, + TXPFC_VLAN_EN = 0x00008000, + TXPFC_PF_EN = 0x00000001, +}; + +enum jme_txtrhd_bits_masks { + TXTRHD_TXPEN = 0x80000000, + TXTRHD_TXP = 0x7FFFFF00, + TXTRHD_TXREN = 0x00000080, + TXTRHD_TXRL = 0x0000007F, +}; +enum jme_txtrhd_shifts { + TXTRHD_TXP_SHIFT = 8, + TXTRHD_TXRL_SHIFT = 0, +}; + /* * RX Control/Status Bits @@ -542,7 +645,7 @@ enum jme_rxcs_values { RXCS_RETRYGAP_256ns | RXCS_RETRYCNT_32, }; -#define JME_RX_DISABLE_TIMEOUT 200 /* 200 usec */ +#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * RX MAC Control/Status Bits @@ -559,6 +662,25 @@ enum jme_rxmcs_bits { RXMCS_VTAGRM = 0x00000004, RXMCS_PREPAD = 0x00000002, RXMCS_CHECKSUM = 0x00000001, + + RXMCS_DEFAULT = RXMCS_VTAGRM | + RXMCS_PREPAD | + RXMCS_FLOWCTRL | + RXMCS_CHECKSUM, +}; + +/* + * Wakeup Frame setup interface registers + */ +#define WAKEUP_FRAME_NR 8 +#define WAKEUP_FRAME_MASK_DWNR 4 +enum jme_wfoi_bit_masks { + WFOI_MASK_SEL = 0x00000070, + WFOI_CRC_SEL = 0x00000008, + WFOI_FRAME_SEL = 0x00000007, +}; +enum jme_wfoi_shifts { + WFOI_MASK_SHIFT = 4, }; /* @@ -592,7 +714,6 @@ __always_inline __u32 smi_phy_addr(int x) return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); } #define JME_PHY_TIMEOUT 1000 /* 1000 usec */ -#define JME_PHY_RST_TIMEOUT 100 /* 100 usec */ /* * Global Host Control @@ -609,6 +730,34 @@ enum jme_ghc_speed_val { GHC_SPEED_1000M = 0x00000030, }; +/* + * Power management control and status register + */ +enum jme_pmcs_bit_masks { + PMCS_WF7DET = 0x80000000, + PMCS_WF6DET = 0x40000000, + PMCS_WF5DET = 0x20000000, + PMCS_WF4DET = 0x10000000, + PMCS_WF3DET = 0x08000000, + PMCS_WF2DET = 0x04000000, + PMCS_WF1DET = 0x02000000, + PMCS_WF0DET = 0x01000000, + PMCS_LFDET = 0x00040000, + PMCS_LRDET = 0x00020000, + PMCS_MFDET = 0x00010000, + PMCS_WF7EN = 0x00008000, + PMCS_WF6EN = 0x00004000, + PMCS_WF5EN = 0x00002000, + PMCS_WF4EN = 0x00001000, + PMCS_WF3EN = 0x00000800, + PMCS_WF2EN = 0x00000400, + PMCS_WF1EN = 0x00000200, + PMCS_WF0EN = 0x00000100, + PMCS_LFEN = 0x00000004, + PMCS_LREN = 0x00000002, + PMCS_MFEN = 0x00000001, +}; + /* * Giga PHY Status Registers */ @@ -618,25 +767,34 @@ enum jme_phy_link_bit_mask { PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, PHY_LINK_UP = 0x00000400, PHY_LINK_AUTONEG_COMPLETE = 0x00000200, + PHY_LINK_MDI_STAT = 0x00000040, }; enum jme_phy_link_speed_val { PHY_LINK_SPEED_10M = 0x00000000, PHY_LINK_SPEED_100M = 0x00004000, PHY_LINK_SPEED_1000M = 0x00008000, }; -#define JME_AUTONEG_TIMEOUT 500 /* 500 ms */ +#define JME_SPDRSV_TIMEOUT 500 /* 500 us */ /* * SMB Control and Status */ -enum jme_smbcsr_bit_mask -{ +enum jme_smbcsr_bit_mask { SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, }; #define JME_SMB_TIMEOUT 10 /* 10 msec */ +/* + * Timer Control/Status Register + */ +enum jme_tmcsr_bit_masks { + TMCSR_SWIT = 0x80000000, + TMCSR_EN = 0x01000000, + TMCSR_CNT = 0x00FFFFFF, +}; + /* * General Purpost REG-0 @@ -715,7 +873,9 @@ enum jme_interrupt_bits INTR_TX1 = 0x00000002, INTR_TX0 = 0x00000001, }; -static const __u32 INTR_ENABLE = INTR_LINKCH | +static const __u32 INTR_ENABLE = INTR_SWINTR | + INTR_TMINTR | + INTR_LINKCH | INTR_RX0EMP | INTR_PCCRX0TO | INTR_PCCRX0 | @@ -766,19 +926,19 @@ enum jme_shadow_base_address_bits { */ __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg) { - return le32_to_cpu(readl(jme->regs + reg)); + return le32_to_cpu(readl((__u8*)jme->regs + reg)); } __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val) { - writel(cpu_to_le32(val), jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); } __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) { /* * Read after write should cause flush */ - writel(cpu_to_le32(val), jme->regs + reg); - readl(jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); + readl((__u8*)jme->regs + reg); } /* @@ -802,3 +962,4 @@ static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); static int jme_set_macaddr(struct net_device *netdev, void *p); static void jme_set_multi(struct net_device *netdev); +