X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=82f4cc6efdc5f2ef96b9ed8d30d4026b1169b4ee;hp=9e9d72faa3cd2373cef1a86bf88f1311928543b1;hb=192570e059855213a9e0010227fc6d1768be4a38;hpb=8c19888420327ac6bc1d75dc9c5ecf8cf0fd4a10 diff --git a/jme.h b/jme.h index 9e9d72f..82f4cc6 100644 --- a/jme.h +++ b/jme.h @@ -24,7 +24,7 @@ #include #define DRV_NAME "jme" -#define DRV_VERSION "0.5" +#define DRV_VERSION "0.9a" #define PFX DRV_NAME ": " #ifdef DEBUG @@ -46,14 +46,30 @@ #define rx_dbg(args...) #endif +#ifdef QUEUE_DEBUG +#define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define queue_dbg(args...) +#endif + +#ifdef CSUM_DEBUG +#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define csum_dbg(args...) +#endif + +#ifdef VLAN_DEBUG +#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define vlan_dbg(args...) +#endif + #define jprintk(devname, fmt, args...) \ printk(KERN_INFO "%s: " fmt, devname, ## args) #define jeprintk(devname, fmt, args...) \ printk(KERN_ERR "%s: " fmt, devname, ## args) -#define USE_IEVE_SHADOW 0 - #define DEFAULT_MSG_ENABLE \ (NETIF_MSG_DRV | \ NETIF_MSG_PROBE | \ @@ -73,31 +89,39 @@ enum pci_conf_dcsr_mrrs_vals { MRRS_4096B = 0x50, }; +#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 +#define MIN_ETHERNET_PACKET_SIZE 60 + enum dynamic_pcc_values { + PCC_OFF = 0, PCC_P1 = 1, PCC_P2 = 2, PCC_P3 = 3, + PCC_OFF_TO = 0, PCC_P1_TO = 1, - PCC_P2_TO = 250, - PCC_P3_TO = 1000, + PCC_P2_TO = 64, + PCC_P3_TO = 128, + PCC_OFF_CNT = 0, PCC_P1_CNT = 1, - PCC_P2_CNT = 64, - PCC_P3_CNT = 255, + PCC_P2_CNT = 16, + PCC_P3_CNT = 32, }; struct dynpcc_info { - unsigned long check_point; unsigned long last_bytes; unsigned long last_pkts; + unsigned long intr_cnt; unsigned char cur; unsigned char attempt; unsigned char cnt; }; -#define PCC_INTERVAL (HZ / 10) +#define PCC_INTERVAL_US 100000 +#define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) #define PCC_P3_THRESHOLD 3*1024*1024 -#define PCC_P2_THRESHOLD 1000 -#define PCC_TX_TO 60000 +#define PCC_P2_THRESHOLD 800 +#define PCC_INTR_THRESHOLD 800 +#define PCC_TX_TO 333 #define PCC_TX_CNT 8 /* @@ -106,13 +130,11 @@ struct dynpcc_info { * TX/RX Ring DESC Count Must be multiple of 16 * RX Ring DESC Count Must be <= 1024 */ -#define RING_DESC_NR 512 /* Must be power of 2 */ #define RING_DESC_ALIGN 16 /* Descriptor alignment */ #define TX_DESC_SIZE 16 #define TX_RING_NR 8 -#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE -#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE) +#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN struct txdesc { union { @@ -181,6 +203,7 @@ enum jme_txdesc_flags_bits { TXFLAG_LSEN = 0x02, TXFLAG_TAGON = 0x01, }; +#define TXDESC_MSS_SHIFT 2 enum jme_rxdescwb_flags_bits { TXWBFLAG_OWN = 0x80, TXWBFLAG_INT = 0x40, @@ -196,17 +219,17 @@ enum jme_rxdescwb_flags_bits { #define RX_DESC_SIZE 16 #define RX_RING_NR 4 -#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE -#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE) +#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN #define RX_BUF_DMA_ALIGN 8 -#define RX_BUF_SIZE 9216 #define RX_PREPAD_SIZE 10 - -/* - * Will use mtu in the future - */ -#define RX_BUF_ALLOC_SIZE RX_BUF_SIZE + RX_BUF_DMA_ALIGN +#define ETH_CRC_LEN 2 +#define RX_VLANHDR_LEN 2 +#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ + ETH_HLEN + \ + ETH_CRC_LEN + \ + RX_VLANHDR_LEN + \ + RX_BUF_DMA_ALIGN) struct rxdesc { union { @@ -297,6 +320,7 @@ struct jme_buffer_info { int nr_desc; }; +#define MAX_RING_DESC_NR 1024 struct jme_ring { void* alloc; /* pointer to allocated memory */ volatile void* desc; /* pointer to ring memory */ @@ -304,12 +328,12 @@ struct jme_ring { dma_addr_t dma; /* phys address for ring dma */ /* Buffer information corresponding to each descriptor */ - struct jme_buffer_info bufinf[RING_DESC_NR]; + struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; - u16 next_to_use; - u16 next_to_clean; + int next_to_use; + int next_to_clean; - u16 nr_free; + atomic_t nr_free; }; #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) @@ -336,7 +360,6 @@ struct jme_adapter { struct mii_if_info mii_if; struct jme_ring rxring[RX_RING_NR]; struct jme_ring txring[TX_RING_NR]; - spinlock_t tx_lock; spinlock_t phy_lock; spinlock_t macaddr_lock; spinlock_t rxmcs_lock; @@ -344,25 +367,42 @@ struct jme_adapter { struct tasklet_struct rxclean_task; struct tasklet_struct txclean_task; struct tasklet_struct linkch_task; - __u32 features; + struct tasklet_struct pcc_task; + __u32 flags; __u32 reg_txcs; __u32 reg_txpfc; + __u32 reg_rxcs; __u32 reg_rxmcs; __u32 reg_ghc; + __u32 reg_pmcs; __u32 phylink; + __u32 tx_ring_size; + __u32 tx_ring_mask; + __u32 tx_wake_threshold; + __u32 rx_ring_size; + __u32 rx_ring_mask; __u8 mrrs; + struct ethtool_cmd old_ecmd; + unsigned int old_mtu; + struct vlan_group* vlgrp; struct dynpcc_info dpi; atomic_t intr_sem; atomic_t link_changing; atomic_t tx_cleaning; atomic_t rx_cleaning; + atomic_t rx_empty; + struct napi_struct napi; DECLARE_NET_DEVICE_STATS }; enum shadow_reg_val { SHADOW_IEVE = 0, }; -enum jme_features_bits { - JME_FEATURE_LALALA = 0x00000001, +enum jme_flags_bits { + JME_FLAG_MSI = 0x00000001, + JME_FLAG_SSET = 0x00000002, + JME_FLAG_TXCSUM = 0x00000004, + JME_FLAG_TSO = 0x00000008, + JME_FLAG_POLL = 0x00000010, }; #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ #define TX_TIMEOUT (5*HZ) @@ -418,6 +458,7 @@ enum jme_iomap_regs { JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ + JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ @@ -471,7 +512,7 @@ enum jme_txcs_value { TXCS_DEFAULT = TXCS_FIFOTH_4QW | TXCS_BURST, }; -#define JME_TX_DISABLE_TIMEOUT 5 /* 5 msec */ +#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * TX MAC Control/Status Bits @@ -599,13 +640,12 @@ enum jme_rxcs_values { RXCS_RETRYCNT_60 = 0x00000F00, RXCS_DEFAULT = RXCS_FIFOTHTP_128T | - //RXCS_FIFOTHNP_128QW | - RXCS_FIFOTHNP_32QW | + RXCS_FIFOTHNP_128QW | RXCS_DMAREQSZ_128B | RXCS_RETRYGAP_256ns | RXCS_RETRYCNT_32, }; -#define JME_RX_DISABLE_TIMEOUT 5 /* 5 msec */ +#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ /* * RX MAC Control/Status Bits @@ -622,13 +662,27 @@ enum jme_rxmcs_bits { RXMCS_VTAGRM = 0x00000004, RXMCS_PREPAD = 0x00000002, RXMCS_CHECKSUM = 0x00000001, - + RXMCS_DEFAULT = RXMCS_VTAGRM | RXMCS_PREPAD | RXMCS_FLOWCTRL | RXMCS_CHECKSUM, }; +/* + * Wakeup Frame setup interface registers + */ +#define WAKEUP_FRAME_NR 8 +#define WAKEUP_FRAME_MASK_DWNR 4 +enum jme_wfoi_bit_masks { + WFOI_MASK_SEL = 0x00000070, + WFOI_CRC_SEL = 0x00000008, + WFOI_FRAME_SEL = 0x00000007, +}; +enum jme_wfoi_shifts { + WFOI_MASK_SHIFT = 4, +}; + /* * SMI Related definitions */ @@ -676,6 +730,34 @@ enum jme_ghc_speed_val { GHC_SPEED_1000M = 0x00000030, }; +/* + * Power management control and status register + */ +enum jme_pmcs_bit_masks { + PMCS_WF7DET = 0x80000000, + PMCS_WF6DET = 0x40000000, + PMCS_WF5DET = 0x20000000, + PMCS_WF4DET = 0x10000000, + PMCS_WF3DET = 0x08000000, + PMCS_WF2DET = 0x04000000, + PMCS_WF1DET = 0x02000000, + PMCS_WF0DET = 0x01000000, + PMCS_LFDET = 0x00040000, + PMCS_LRDET = 0x00020000, + PMCS_MFDET = 0x00010000, + PMCS_WF7EN = 0x00008000, + PMCS_WF6EN = 0x00004000, + PMCS_WF5EN = 0x00002000, + PMCS_WF4EN = 0x00001000, + PMCS_WF3EN = 0x00000800, + PMCS_WF2EN = 0x00000400, + PMCS_WF1EN = 0x00000200, + PMCS_WF0EN = 0x00000100, + PMCS_LFEN = 0x00000004, + PMCS_LREN = 0x00000002, + PMCS_MFEN = 0x00000001, +}; + /* * Giga PHY Status Registers */ @@ -697,14 +779,22 @@ enum jme_phy_link_speed_val { /* * SMB Control and Status */ -enum jme_smbcsr_bit_mask -{ +enum jme_smbcsr_bit_mask { SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, }; #define JME_SMB_TIMEOUT 10 /* 10 msec */ +/* + * Timer Control/Status Register + */ +enum jme_tmcsr_bit_masks { + TMCSR_SWIT = 0x80000000, + TMCSR_EN = 0x01000000, + TMCSR_CNT = 0x00FFFFFF, +}; + /* * General Purpost REG-0 @@ -783,7 +873,9 @@ enum jme_interrupt_bits INTR_TX1 = 0x00000002, INTR_TX0 = 0x00000001, }; -static const __u32 INTR_ENABLE = INTR_LINKCH | +static const __u32 INTR_ENABLE = INTR_SWINTR | + INTR_TMINTR | + INTR_LINKCH | INTR_RX0EMP | INTR_PCCRX0TO | INTR_PCCRX0 | @@ -834,19 +926,19 @@ enum jme_shadow_base_address_bits { */ __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg) { - return le32_to_cpu(readl(jme->regs + reg)); + return le32_to_cpu(readl((__u8*)jme->regs + reg)); } __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val) { - writel(cpu_to_le32(val), jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); } __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) { /* * Read after write should cause flush */ - writel(cpu_to_le32(val), jme->regs + reg); - readl(jme->regs + reg); + writel(cpu_to_le32(val), (__u8*)jme->regs + reg); + readl((__u8*)jme->regs + reg); } /*