X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=57a270bb57e1c8d86793833effd1b2311c8ac7fd;hp=214d62fd7272f90c551b6544f38817a08fa5075d;hb=186fc2591e3b5b6e35e66aef88e4ef7c4d87fd58;hpb=b3821cc585b81f316d02684eb74ef3b9259681c8 diff --git a/jme.h b/jme.h index 214d62f..57a270b 100644 --- a/jme.h +++ b/jme.h @@ -24,7 +24,7 @@ #include #define DRV_NAME "jme" -#define DRV_VERSION "0.9" +#define DRV_VERSION "0.9c" #define PFX DRV_NAME ": " #ifdef DEBUG @@ -93,17 +93,20 @@ enum pci_conf_dcsr_mrrs_vals { #define MIN_ETHERNET_PACKET_SIZE 60 enum dynamic_pcc_values { + PCC_OFF = 0, PCC_P1 = 1, PCC_P2 = 2, PCC_P3 = 3, + PCC_OFF_TO = 0, PCC_P1_TO = 1, - PCC_P2_TO = 250, - PCC_P3_TO = 1000, + PCC_P2_TO = 64, + PCC_P3_TO = 128, + PCC_OFF_CNT = 0, PCC_P1_CNT = 1, - PCC_P2_CNT = 64, - PCC_P3_CNT = 255, + PCC_P2_CNT = 16, + PCC_P3_CNT = 32, }; struct dynpcc_info { unsigned long last_bytes; @@ -115,7 +118,7 @@ struct dynpcc_info { }; #define PCC_INTERVAL_US 100000 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) -#define PCC_P3_THRESHOLD 3*1024*1024 +#define PCC_P3_THRESHOLD 2*1024*1024 #define PCC_P2_THRESHOLD 800 #define PCC_INTR_THRESHOLD 800 #define PCC_TX_TO 333 @@ -315,6 +318,7 @@ struct jme_buffer_info { dma_addr_t mapping; int len; int nr_desc; + unsigned long start_xmit; }; #define MAX_RING_DESC_NR 1024 @@ -328,8 +332,7 @@ struct jme_ring { struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; int next_to_use; - int next_to_clean; - + atomic_t next_to_clean; atomic_t nr_free; }; @@ -344,6 +347,41 @@ struct jme_ring { #define DECLARE_NET_DEVICE_STATS #endif +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +#define DECLARE_NAPI_STRUCT +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + dev->poll = pollfn; \ + dev->weight = q; +#define JME_NAPI_HOLDER(holder) struct net_device *holder +#define JME_NAPI_WEIGHT(w) int *w +#define JME_NAPI_WEIGHT_VAL(w) *w +#define JME_NAPI_WEIGHT_SET(w, r) *w = r +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) +#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); +#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev); +#else +#define DECLARE_NAPI_STRUCT struct napi_struct napi; +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + netif_napi_add(dev, napis, pollfn, q); +#define JME_NAPI_HOLDER(holder) struct napi_struct *holder +#define JME_NAPI_WEIGHT(w) int w +#define JME_NAPI_WEIGHT_VAL(w) w +#define JME_NAPI_WEIGHT_SET(w, r) +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) +#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); +#define JME_NAPI_DISABLE(priv) \ + if(!napi_disable_pending(&priv->napi)) \ + napi_disable(&priv->napi); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev, &priv->napi) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev, &priv->napi); +#endif + /* * Jmac Adapter Private data */ @@ -379,6 +417,8 @@ struct jme_adapter { __u32 rx_ring_size; __u32 rx_ring_mask; __u8 mrrs; + __u32 fpgaver; + __u32 chipver; struct ethtool_cmd old_ecmd; unsigned int old_mtu; struct vlan_group* vlgrp; @@ -387,6 +427,12 @@ struct jme_adapter { atomic_t link_changing; atomic_t tx_cleaning; atomic_t rx_cleaning; + atomic_t rx_empty; + int (*jme_rx)(struct sk_buff *skb); + int (*jme_vlan_rx)(struct sk_buff *skb, + struct vlan_group *grp, + unsigned short vlan_tag); + DECLARE_NAPI_STRUCT DECLARE_NET_DEVICE_STATS }; enum shadow_reg_val { @@ -397,10 +443,29 @@ enum jme_flags_bits { JME_FLAG_SSET = 0x00000002, JME_FLAG_TXCSUM = 0x00000004, JME_FLAG_TSO = 0x00000008, + JME_FLAG_POLL = 0x00000010, }; #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ #define TX_TIMEOUT (5*HZ) +#define JME_REG_LEN 0x500 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +__always_inline static struct jme_adapter* +jme_napi_priv(struct net_device *holder) +{ + struct jme_adapter* jme; + jme = netdev_priv(holder); + return jme; +} +#else +__always_inline static struct jme_adapter* +jme_napi_priv(struct napi_struct *napi) +{ + struct jme_adapter* jme; + jme = container_of(napi, struct jme_adapter, napi); + return jme; +} +#endif /* * MMaped I/O Resters @@ -450,6 +515,7 @@ enum jme_iomap_regs { JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ + JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ @@ -461,6 +527,7 @@ enum jme_iomap_regs { JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */ JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */ JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */ + JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */ JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */ JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */ JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */ @@ -707,7 +774,8 @@ __always_inline __u32 smi_phy_addr(int x) { return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); } -#define JME_PHY_TIMEOUT 1000 /* 1000 usec */ +#define JME_PHY_TIMEOUT 1000 /* 1000 msec */ +#define JME_PHY_REG_NR 32 /* * Global Host Control @@ -777,8 +845,33 @@ enum jme_smbcsr_bit_mask { SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, + SMBCSR_INITDONE = 0x00000010, + SMBCSR_BUSY = 0x0000000F, +}; +enum jme_smbintf_bit_mask { + SMBINTF_HWDATR = 0xFF000000, + SMBINTF_HWDATW = 0x00FF0000, + SMBINTF_HWADDR = 0x0000FF00, + SMBINTF_HWRWN = 0x00000020, + SMBINTF_HWCMD = 0x00000010, + SMBINTF_FASTM = 0x00000008, + SMBINTF_GPIOSCL = 0x00000004, + SMBINTF_GPIOSDA = 0x00000002, + SMBINTF_GPIOEN = 0x00000001, +}; +enum jme_smbintf_vals { + SMBINTF_HWRWN_READ = 0x00000020, + SMBINTF_HWRWN_WRITE = 0x00000000, }; -#define JME_SMB_TIMEOUT 10 /* 10 msec */ +enum jme_smbintf_shifts { + SMBINTF_HWDATR_SHIFT = 24, + SMBINTF_HWDATW_SHIFT = 16, + SMBINTF_HWADDR_SHIFT = 8, +}; +#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ +#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ +#define JME_SMB_LEN 256 +#define JME_EEPROM_MAGIC 0x250 /* * Timer Control/Status Register @@ -797,6 +890,7 @@ enum jme_gpreg0_masks { GPREG0_DISSH = 0xFF000000, GPREG0_PCIRLMT = 0x00300000, GPREG0_PCCNOMUTCLR = 0x00040000, + GPREG0_LNKINTPOLL = 0x00001000, GPREG0_PCCTMR = 0x00000300, GPREG0_PHYADDR = 0x0000001F, }; @@ -870,11 +964,11 @@ enum jme_interrupt_bits static const __u32 INTR_ENABLE = INTR_SWINTR | INTR_TMINTR | INTR_LINKCH | - INTR_RX0EMP | INTR_PCCRX0TO | INTR_PCCRX0 | INTR_PCCTXTO | - INTR_PCCTX; + INTR_PCCTX | + INTR_RX0EMP; /* * PCC Control Registers @@ -907,6 +1001,18 @@ enum jme_pcctx_bits { PCCTXQ7_EN = 0x00000080, }; +/* + * Chip Mode Register + */ +enum jme_chipmode_bit_masks { + CM_FPGAVER_MASK = 0xFFFF0000, + CM_CHIPVER_MASK = 0x0000FF00, + CM_CHIPMODE_MASK = 0x0000000F, +}; +enum jme_chipmode_shifts { + CM_FPGAVER_SHIFT = 16, + CM_CHIPVER_SHIFT = 8, +}; /* * Shadow base address register bits @@ -935,6 +1041,23 @@ __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) readl((__u8*)jme->regs + reg); } +/* + * PHY Regs + */ +enum jme_phy_reg17_bit_masks { + PREG17_SPEED = 0xC000, + PREG17_DUPLEX = 0x2000, + PREG17_SPDRSV = 0x0800, + PREG17_LNKUP = 0x0400, + PREG17_MDI = 0x0040, +}; +enum jme_phy_reg17_vals { + PREG17_SPEED_10M = 0x0000, + PREG17_SPEED_100M = 0x4000, + PREG17_SPEED_1000M = 0x8000, +}; +#define BMCR_ANCOMP 0x0020 + /* * Function prototypes for ethtool */ @@ -956,4 +1079,3 @@ static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); static int jme_set_macaddr(struct net_device *netdev, void *p); static void jme_set_multi(struct net_device *netdev); -