X-Git-Url: https://bbs.cooldavid.org/git/?p=jme.git;a=blobdiff_plain;f=jme.h;h=1f37cf3500feeba713049ee573b11461c0b385a1;hp=67ebe0db62cec2464325e73d29befc71f35bf530;hb=refs%2Fheads%2Fmsix_test;hpb=42b1055e2e1ef3ceba54535a95780dd90b8ddf5c diff --git a/jme.h b/jme.h index 67ebe0d..1f37cf3 100644 --- a/jme.h +++ b/jme.h @@ -24,9 +24,12 @@ #include #define DRV_NAME "jme" -#define DRV_VERSION "0.8" +#define DRV_VERSION "0.9d-msix" #define PFX DRV_NAME ": " +#define JME_GE_DEVICE 0x250 +#define JME_FE_DEVICE 0x260 + #ifdef DEBUG #define dprintk(devname, fmt, args...) \ printk(KERN_DEBUG "%s: " fmt, devname, ## args) @@ -58,20 +61,18 @@ #define csum_dbg(args...) #endif +#ifdef VLAN_DEBUG +#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args) +#else +#define vlan_dbg(args...) +#endif + #define jprintk(devname, fmt, args...) \ printk(KERN_INFO "%s: " fmt, devname, ## args) #define jeprintk(devname, fmt, args...) \ printk(KERN_ERR "%s: " fmt, devname, ## args) -#define DEFAULT_MSG_ENABLE \ - (NETIF_MSG_DRV | \ - NETIF_MSG_PROBE | \ - NETIF_MSG_LINK | \ - NETIF_MSG_TIMER | \ - NETIF_MSG_RX_ERR | \ - NETIF_MSG_TX_ERR) - #define PCI_CONF_DCSR_MRRS 0x59 #define PCI_CONF_DCSR_MRRS_MASK 0x70 enum pci_conf_dcsr_mrrs_vals { @@ -86,18 +87,69 @@ enum pci_conf_dcsr_mrrs_vals { #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 #define MIN_ETHERNET_PACKET_SIZE 60 + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) +#define NET_STAT(priv) priv->stats +#define NETDEV_GET_STATS(netdev, fun_ptr) \ + netdev->get_stats = fun_ptr +#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; +#else +#define NET_STAT(priv) priv->dev->stats +#define NETDEV_GET_STATS(netdev, fun_ptr) +#define DECLARE_NET_DEVICE_STATS +#endif + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +#define DECLARE_NAPI_STRUCT +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + dev->poll = pollfn; \ + dev->weight = q; +#define JME_NAPI_HOLDER(holder) struct net_device *holder +#define JME_NAPI_WEIGHT(w) int *w +#define JME_NAPI_WEIGHT_VAL(w) *w +#define JME_NAPI_WEIGHT_SET(w, r) *w = r +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev) +#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev); +#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev); +#else +#define DECLARE_NAPI_STRUCT struct napi_struct napi; +#define NETIF_NAPI_SET(dev, napis, pollfn, q) \ + netif_napi_add(dev, napis, pollfn, q); +#define JME_NAPI_HOLDER(holder) struct napi_struct *holder +#define JME_NAPI_WEIGHT(w) int w +#define JME_NAPI_WEIGHT_VAL(w) w +#define JME_NAPI_WEIGHT_SET(w, r) +#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis) +#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); +#define JME_NAPI_DISABLE(priv) \ + if(!napi_disable_pending(&priv->napi)) \ + napi_disable(&priv->napi); +#define JME_RX_SCHEDULE_PREP(priv) \ + netif_rx_schedule_prep(priv->dev, &priv->napi) +#define JME_RX_SCHEDULE(priv) \ + __netif_rx_schedule(priv->dev, &priv->napi); +#endif + + enum dynamic_pcc_values { + PCC_OFF = 0, PCC_P1 = 1, PCC_P2 = 2, PCC_P3 = 3, + PCC_OFF_TO = 0, PCC_P1_TO = 1, - PCC_P2_TO = 250, - PCC_P3_TO = 1000, + PCC_P2_TO = 64, + PCC_P3_TO = 128, + PCC_OFF_CNT = 0, PCC_P1_CNT = 1, - PCC_P2_CNT = 64, - PCC_P3_CNT = 255, + PCC_P2_CNT = 16, + PCC_P3_CNT = 32, }; struct dynpcc_info { unsigned long last_bytes; @@ -109,11 +161,11 @@ struct dynpcc_info { }; #define PCC_INTERVAL_US 100000 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US)) -#define PCC_P3_THRESHOLD 3*1024*1024 +#define PCC_P3_THRESHOLD 2*1024*1024 #define PCC_P2_THRESHOLD 800 #define PCC_INTR_THRESHOLD 800 -#define PCC_TX_TO 100 -#define PCC_TX_CNT 16 +#define PCC_TX_TO 333 +#define PCC_TX_CNT 8 /* * TX/RX Descriptors @@ -121,13 +173,11 @@ struct dynpcc_info { * TX/RX Ring DESC Count Must be multiple of 16 * RX Ring DESC Count Must be <= 1024 */ -#define RING_DESC_NR 512 /* Must be power of 2 */ #define RING_DESC_ALIGN 16 /* Descriptor alignment */ #define TX_DESC_SIZE 16 #define TX_RING_NR 8 -#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE -#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE) +#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN struct txdesc { union { @@ -196,6 +246,7 @@ enum jme_txdesc_flags_bits { TXFLAG_LSEN = 0x02, TXFLAG_TAGON = 0x01, }; +#define TXDESC_MSS_SHIFT 2 enum jme_rxdescwb_flags_bits { TXWBFLAG_OWN = 0x80, TXWBFLAG_INT = 0x40, @@ -211,8 +262,7 @@ enum jme_rxdescwb_flags_bits { #define RX_DESC_SIZE 16 #define RX_RING_NR 4 -#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE -#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE) +#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN #define RX_BUF_DMA_ALIGN 8 #define RX_PREPAD_SIZE 10 @@ -311,8 +361,10 @@ struct jme_buffer_info { dma_addr_t mapping; int len; int nr_desc; + unsigned long start_xmit; }; +#define MAX_RING_DESC_NR 1024 struct jme_ring { void* alloc; /* pointer to allocated memory */ volatile void* desc; /* pointer to ring memory */ @@ -320,24 +372,20 @@ struct jme_ring { dma_addr_t dma; /* phys address for ring dma */ /* Buffer information corresponding to each descriptor */ - struct jme_buffer_info bufinf[RING_DESC_NR]; - - u16 next_to_use; - u16 next_to_clean; + struct jme_buffer_info bufinf[MAX_RING_DESC_NR]; + int next_to_use; + atomic_t next_to_clean; atomic_t nr_free; }; -#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21) -#define NET_STAT(priv) priv->stats -#define NETDEV_GET_STATS(netdev, fun_ptr) \ - netdev->get_stats = fun_ptr -#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats; -#else -#define NET_STAT(priv) priv->dev->stats -#define NETDEV_GET_STATS(netdev, fun_ptr) -#define DECLARE_NET_DEVICE_STATS -#endif +#define JME_MSIX_VEC_NR 3 +struct jme_msix_info { + irq_handler_t handler; + __u16 vector; + __u8 requested; + char name[16]; +}; /* * Jmac Adapter Private data @@ -360,6 +408,7 @@ struct jme_adapter { struct tasklet_struct txclean_task; struct tasklet_struct linkch_task; struct tasklet_struct pcc_task; + struct jme_msix_info msix[JME_MSIX_VEC_NR]; __u32 flags; __u32 reg_txcs; __u32 reg_txpfc; @@ -368,7 +417,14 @@ struct jme_adapter { __u32 reg_ghc; __u32 reg_pmcs; __u32 phylink; + __u32 tx_ring_size; + __u32 tx_ring_mask; + __u32 tx_wake_threshold; + __u32 rx_ring_size; + __u32 rx_ring_mask; __u8 mrrs; + __u32 fpgaver; + __u32 chipver; struct ethtool_cmd old_ecmd; unsigned int old_mtu; struct vlan_group* vlgrp; @@ -377,6 +433,12 @@ struct jme_adapter { atomic_t link_changing; atomic_t tx_cleaning; atomic_t rx_cleaning; + atomic_t rx_empty; + int (*jme_rx)(struct sk_buff *skb); + int (*jme_vlan_rx)(struct sk_buff *skb, + struct vlan_group *grp, + unsigned short vlan_tag); + DECLARE_NAPI_STRUCT DECLARE_NET_DEVICE_STATS }; enum shadow_reg_val { @@ -384,11 +446,33 @@ enum shadow_reg_val { }; enum jme_flags_bits { JME_FLAG_MSI = 0x00000001, - JME_FLAG_SSET = 0x00000002, + JME_FLAG_MSIX = 0x00000002, + JME_FLAG_SSET = 0x00000004, + JME_FLAG_TXCSUM = 0x00000008, + JME_FLAG_TSO = 0x00000010, + JME_FLAG_POLL = 0x00000020, }; #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */ #define TX_TIMEOUT (5*HZ) +#define JME_REG_LEN 0x500 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23) +__always_inline static struct jme_adapter* +jme_napi_priv(struct net_device *holder) +{ + struct jme_adapter* jme; + jme = netdev_priv(holder); + return jme; +} +#else +__always_inline static struct jme_adapter* +jme_napi_priv(struct napi_struct *napi) +{ + struct jme_adapter* jme; + jme = container_of(napi, struct jme_adapter, napi); + return jme; +} +#endif /* * MMaped I/O Resters @@ -438,17 +522,20 @@ enum jme_iomap_regs { JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ + JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */ JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */ JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */ + JME_MSIX_ENT = JME_MISC| 0x10, /* MSIX Entry table */ JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */ JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */ JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */ JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */ JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */ JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */ + JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */ JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */ JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */ JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */ @@ -644,13 +731,27 @@ enum jme_rxmcs_bits { RXMCS_VTAGRM = 0x00000004, RXMCS_PREPAD = 0x00000002, RXMCS_CHECKSUM = 0x00000001, - + RXMCS_DEFAULT = RXMCS_VTAGRM | RXMCS_PREPAD | RXMCS_FLOWCTRL | RXMCS_CHECKSUM, }; +/* + * Wakeup Frame setup interface registers + */ +#define WAKEUP_FRAME_NR 8 +#define WAKEUP_FRAME_MASK_DWNR 4 +enum jme_wfoi_bit_masks { + WFOI_MASK_SEL = 0x00000070, + WFOI_CRC_SEL = 0x00000008, + WFOI_FRAME_SEL = 0x00000007, +}; +enum jme_wfoi_shifts { + WFOI_MASK_SHIFT = 4, +}; + /* * SMI Related definitions */ @@ -681,7 +782,8 @@ __always_inline __u32 smi_phy_addr(int x) { return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK); } -#define JME_PHY_TIMEOUT 1000 /* 1000 usec */ +#define JME_PHY_TIMEOUT 100 /* 100 msec */ +#define JME_PHY_REG_NR 32 /* * Global Host Control @@ -751,8 +853,33 @@ enum jme_smbcsr_bit_mask { SMBCSR_CNACK = 0x00020000, SMBCSR_RELOAD = 0x00010000, SMBCSR_EEPROMD = 0x00000020, + SMBCSR_INITDONE = 0x00000010, + SMBCSR_BUSY = 0x0000000F, }; -#define JME_SMB_TIMEOUT 10 /* 10 msec */ +enum jme_smbintf_bit_mask { + SMBINTF_HWDATR = 0xFF000000, + SMBINTF_HWDATW = 0x00FF0000, + SMBINTF_HWADDR = 0x0000FF00, + SMBINTF_HWRWN = 0x00000020, + SMBINTF_HWCMD = 0x00000010, + SMBINTF_FASTM = 0x00000008, + SMBINTF_GPIOSCL = 0x00000004, + SMBINTF_GPIOSDA = 0x00000002, + SMBINTF_GPIOEN = 0x00000001, +}; +enum jme_smbintf_vals { + SMBINTF_HWRWN_READ = 0x00000020, + SMBINTF_HWRWN_WRITE = 0x00000000, +}; +enum jme_smbintf_shifts { + SMBINTF_HWDATR_SHIFT = 24, + SMBINTF_HWDATW_SHIFT = 16, + SMBINTF_HWADDR_SHIFT = 8, +}; +#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ +#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ +#define JME_SMB_LEN 256 +#define JME_EEPROM_MAGIC 0x250 /* * Timer Control/Status Register @@ -771,6 +898,7 @@ enum jme_gpreg0_masks { GPREG0_DISSH = 0xFF000000, GPREG0_PCIRLMT = 0x00300000, GPREG0_PCCNOMUTCLR = 0x00040000, + GPREG0_LNKINTPOLL = 0x00001000, GPREG0_PCCTMR = 0x00000300, GPREG0_PHYADDR = 0x0000001F, }; @@ -806,8 +934,7 @@ enum jme_gpreg0_vals { /* * Interrupt Status Bits */ -enum jme_interrupt_bits -{ +enum jme_interrupt_bits { INTR_SWINTR = 0x80000000, INTR_TMINTR = 0x40000000, INTR_LINKCH = 0x20000000, @@ -841,14 +968,25 @@ enum jme_interrupt_bits INTR_TX1 = 0x00000002, INTR_TX0 = 0x00000001, }; -static const __u32 INTR_ENABLE = INTR_SWINTR | - INTR_TMINTR | - INTR_LINKCH | - INTR_RX0EMP | - INTR_PCCRX0TO | - INTR_PCCRX0 | - INTR_PCCTXTO | - INTR_PCCTX; +enum jme_interrupt_enables { + INTR_ENABLE = INTR_SWINTR | + INTR_TMINTR | + INTR_LINKCH | + INTR_PCCRX0TO | + INTR_PCCRX0 | + INTR_PCCTXTO | + INTR_PCCTX | + INTR_RX0EMP, + + INTR_EN_TX = INTR_PCCTXTO | + INTR_PCCTX, + + INTR_EN_RX0 = INTR_PCCRX0TO | + INTR_PCCRX0 | + INTR_RX0EMP, + + INTR_EN_MISC = INTR_ENABLE & ~(INTR_EN_TX | INTR_EN_RX0), +}; /* * PCC Control Registers @@ -881,6 +1019,18 @@ enum jme_pcctx_bits { PCCTXQ7_EN = 0x00000080, }; +/* + * Chip Mode Register + */ +enum jme_chipmode_bit_masks { + CM_FPGAVER_MASK = 0xFFFF0000, + CM_CHIPVER_MASK = 0x0000FF00, + CM_CHIPMODE_MASK = 0x0000000F, +}; +enum jme_chipmode_shifts { + CM_FPGAVER_SHIFT = 16, + CM_CHIPVER_SHIFT = 8, +}; /* * Shadow base address register bits @@ -909,6 +1059,23 @@ __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val) readl((__u8*)jme->regs + reg); } +/* + * PHY Regs + */ +enum jme_phy_reg17_bit_masks { + PREG17_SPEED = 0xC000, + PREG17_DUPLEX = 0x2000, + PREG17_SPDRSV = 0x0800, + PREG17_LNKUP = 0x0400, + PREG17_MDI = 0x0040, +}; +enum jme_phy_reg17_vals { + PREG17_SPEED_10M = 0x0000, + PREG17_SPEED_100M = 0x4000, + PREG17_SPEED_1000M = 0x8000, +}; +#define BMSR_ANCOMP 0x0020 + /* * Function prototypes for ethtool */ @@ -930,4 +1097,3 @@ static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev); static int jme_set_macaddr(struct net_device *netdev, void *p); static void jme_set_multi(struct net_device *netdev); -