#include <linux/version.h>
#define DRV_NAME "jme"
-#define DRV_VERSION "0.7"
+#define DRV_VERSION "0.9a"
#define PFX DRV_NAME ": "
#ifdef DEBUG
#define csum_dbg(args...)
#endif
+#ifdef VLAN_DEBUG
+#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
+#else
+#define vlan_dbg(args...)
+#endif
+
#define jprintk(devname, fmt, args...) \
printk(KERN_INFO "%s: " fmt, devname, ## args)
#define MIN_ETHERNET_PACKET_SIZE 60
enum dynamic_pcc_values {
+ PCC_OFF = 0,
PCC_P1 = 1,
PCC_P2 = 2,
PCC_P3 = 3,
+ PCC_OFF_TO = 0,
PCC_P1_TO = 1,
- PCC_P2_TO = 250,
- PCC_P3_TO = 1000,
+ PCC_P2_TO = 64,
+ PCC_P3_TO = 128,
+ PCC_OFF_CNT = 0,
PCC_P1_CNT = 1,
- PCC_P2_CNT = 64,
- PCC_P3_CNT = 255,
+ PCC_P2_CNT = 16,
+ PCC_P3_CNT = 32,
};
struct dynpcc_info {
unsigned long last_bytes;
#define PCC_P3_THRESHOLD 3*1024*1024
#define PCC_P2_THRESHOLD 800
#define PCC_INTR_THRESHOLD 800
-#define PCC_TX_TO 100
-#define PCC_TX_CNT 16
+#define PCC_TX_TO 333
+#define PCC_TX_CNT 8
/*
* TX/RX Descriptors
* TX/RX Ring DESC Count Must be multiple of 16
* RX Ring DESC Count Must be <= 1024
*/
-#define RING_DESC_NR 512 /* Must be power of 2 */
#define RING_DESC_ALIGN 16 /* Descriptor alignment */
#define TX_DESC_SIZE 16
#define TX_RING_NR 8
-#define TX_RING_ALLOC_SIZE (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
-#define TX_RING_SIZE (RING_DESC_NR * TX_DESC_SIZE)
+#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
struct txdesc {
union {
TXFLAG_LSEN = 0x02,
TXFLAG_TAGON = 0x01,
};
+#define TXDESC_MSS_SHIFT 2
enum jme_rxdescwb_flags_bits {
TXWBFLAG_OWN = 0x80,
TXWBFLAG_INT = 0x40,
#define RX_DESC_SIZE 16
#define RX_RING_NR 4
-#define RX_RING_ALLOC_SIZE (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
-#define RX_RING_SIZE (RING_DESC_NR * RX_DESC_SIZE)
+#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
#define RX_BUF_DMA_ALIGN 8
#define RX_PREPAD_SIZE 10
int nr_desc;
};
+#define MAX_RING_DESC_NR 1024
struct jme_ring {
void* alloc; /* pointer to allocated memory */
volatile void* desc; /* pointer to ring memory */
dma_addr_t dma; /* phys address for ring dma */
/* Buffer information corresponding to each descriptor */
- struct jme_buffer_info bufinf[RING_DESC_NR];
+ struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
- u16 next_to_use;
- u16 next_to_clean;
+ int next_to_use;
+ int next_to_clean;
atomic_t nr_free;
};
__u32 reg_ghc;
__u32 reg_pmcs;
__u32 phylink;
+ __u32 tx_ring_size;
+ __u32 tx_ring_mask;
+ __u32 tx_wake_threshold;
+ __u32 rx_ring_size;
+ __u32 rx_ring_mask;
__u8 mrrs;
struct ethtool_cmd old_ecmd;
unsigned int old_mtu;
+ struct vlan_group* vlgrp;
struct dynpcc_info dpi;
atomic_t intr_sem;
atomic_t link_changing;
atomic_t tx_cleaning;
atomic_t rx_cleaning;
+ atomic_t rx_empty;
+ struct napi_struct napi;
DECLARE_NET_DEVICE_STATS
};
enum shadow_reg_val {
enum jme_flags_bits {
JME_FLAG_MSI = 0x00000001,
JME_FLAG_SSET = 0x00000002,
+ JME_FLAG_TXCSUM = 0x00000004,
+ JME_FLAG_TSO = 0x00000008,
+ JME_FLAG_POLL = 0x00000010,
};
#define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
#define TX_TIMEOUT (5*HZ)
RXMCS_VTAGRM = 0x00000004,
RXMCS_PREPAD = 0x00000002,
RXMCS_CHECKSUM = 0x00000001,
-
+
RXMCS_DEFAULT = RXMCS_VTAGRM |
RXMCS_PREPAD |
RXMCS_FLOWCTRL |
RXMCS_CHECKSUM,
};
+/*
+ * Wakeup Frame setup interface registers
+ */
+#define WAKEUP_FRAME_NR 8
+#define WAKEUP_FRAME_MASK_DWNR 4
+enum jme_wfoi_bit_masks {
+ WFOI_MASK_SEL = 0x00000070,
+ WFOI_CRC_SEL = 0x00000008,
+ WFOI_FRAME_SEL = 0x00000007,
+};
+enum jme_wfoi_shifts {
+ WFOI_MASK_SHIFT = 4,
+};
+
/*
* SMI Related definitions
*/