[PATCH] jme: Fix FIFO flush issue

[jme.git] / jme.h

diff --git a/jme.h b/jme.h
index 668958c68f63cb95314c6edae3c5d9e5611b32c6..3efc897c991310c637353aaed01c9516575a02d9 100644 (file)
--- a/jme.h
+++ b/jme.h
@@ -24,9 +24,10 @@
 
 #ifndef __JME_H_INCLUDED__
 #define __JME_H_INCLUDED__
+#include <linux/interrupt.h>
 
 #define DRV_NAME       "jme"
-#define DRV_VERSION    "1.0.7"
+#define DRV_VERSION    "1.0.8"
 #define PFX            DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250   0x0250
@@ -101,7 +102,6 @@ enum jme_spi_op_bits {
 };
 
 #define HALF_US 500    /* 500 ns */
-#define JMESPIIOCTL    SIOCDEVPRIVATE
 
 #define PCI_PRIV_PE1           0xE4
 
@@ -450,7 +450,6 @@ struct jme_adapter {
        u32                     msg_enable;
        struct ethtool_cmd      old_ecmd;
        unsigned int            old_mtu;
-       struct vlan_group       *vlgrp;
        struct dynpcc_info      dpi;
        atomic_t                intr_sem;
        atomic_t                link_changing;
@@ -458,9 +457,6 @@ struct jme_adapter {
        atomic_t                rx_cleaning;
        atomic_t                rx_empty;
        int                     (*jme_rx)(struct sk_buff *skb);
-       int                     (*jme_vlan_rx)(struct sk_buff *skb,
-                                         struct vlan_group *grp,
-                                         unsigned short vlan_tag);
        DECLARE_NAPI_STRUCT
        DECLARE_NET_DEVICE_STATS
 };
@@ -468,8 +464,6 @@ struct jme_adapter {
 enum jme_flags_bits {
        JME_FLAG_MSI            = 1,
        JME_FLAG_SSET           = 2,
-       JME_FLAG_TXCSUM         = 3,
-       JME_FLAG_TSO            = 4,
        JME_FLAG_POLL           = 5,
        JME_FLAG_SHUTDOWN       = 6,
 };
@@ -736,7 +730,7 @@ enum jme_rxcs_values {
        RXCS_RETRYCNT_60        = 0x00000F00,
 
        RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
-                                 RXCS_FIFOTHNP_128QW |
+                                 RXCS_FIFOTHNP_16QW |
                                  RXCS_DMAREQSZ_128B |
                                  RXCS_RETRYGAP_256ns |
                                  RXCS_RETRYCNT_32,
@@ -766,6 +760,25 @@ enum jme_rxmcs_bits {
                                  RXMCS_CHECKSUM,
 };
 
+/*     Extern PHY common register 2    */
+
+#define PHY_GAD_TEST_MODE_1                    0x00002000
+#define PHY_GAD_TEST_MODE_MSK                  0x0000E000
+#define JM_PHY_SPEC_REG_READ                   0x00004000
+#define JM_PHY_SPEC_REG_WRITE                  0x00008000
+#define PHY_CALIBRATION_DELAY                  20
+#define JM_PHY_SPEC_ADDR_REG                   0x1E
+#define JM_PHY_SPEC_DATA_REG                   0x1F
+
+#define JM_PHY_EXT_COMM_0_REG                  0x30
+#define JM_PHY_EXT_COMM_1_REG                  0x31
+#define JM_PHY_EXT_COMM_2_REG                  0x32
+#define JM_PHY_EXT_COMM_2_CALI_ENABLE          0x01
+#define JM_PHY_EXT_COMM_2_CALI_MODE_0          0x02
+#define JM_PHY_EXT_COMM_2_CALI_LATCH           0x10
+#define PCI_PRIV_SHARE_NICCTRL                 0xF5
+#define JME_FLAG_PHYEA_ENABLE                  0x2
+
 /*
  * Wakeup Frame setup interface registers
  */
@@ -853,6 +866,7 @@ enum jme_ghc_txmac_clk {
  * Power management control and status register
  */
 enum jme_pmcs_bit_masks {
+       PMCS_STMASK     = 0xFFFF0000,
        PMCS_WF7DET     = 0x80000000,
        PMCS_WF6DET     = 0x40000000,
        PMCS_WF5DET     = 0x20000000,
@@ -864,6 +878,7 @@ enum jme_pmcs_bit_masks {
        PMCS_LFDET      = 0x00040000,
        PMCS_LRDET      = 0x00020000,
        PMCS_MFDET      = 0x00010000,
+       PMCS_ENMASK     = 0x0000FFFF,
        PMCS_WF7EN      = 0x00008000,
        PMCS_WF6EN      = 0x00004000,
        PMCS_WF5EN      = 0x00002000,
@@ -1258,6 +1273,7 @@ static inline int new_phy_power_ctrl(u8 chip_main_rev)
  */
 static int jme_set_settings(struct net_device *netdev,
                                struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
 static void jme_set_multi(struct net_device *netdev);
 
 #endif