phyext testing

[jme.git] / jme.h

diff --git a/jme.h b/jme.h
index 2011af2543edcefb5f4e6042267a02b6c88784f3..1f65208758c90a12150f53aabf56f20301324e73 100644 (file)
--- a/jme.h
+++ b/jme.h
@@ -26,7 +26,7 @@
 #define __JME_H_INCLUDED__
 
 #define DRV_NAME       "jme"
-#define DRV_VERSION    "1.0.7-jmmod"
+#define DRV_VERSION    "1.0.8-jmmod"
 #define PFX            DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250   0x0250
@@ -555,6 +555,7 @@ struct jme_adapter {
        u32                     reg_rxmcs;
        u32                     reg_ghc;
        u32                     reg_pmcs;
+       u32                     reg_gpreg1;
        u32                     phylink;
        u32                     tx_ring_size;
        u32                     tx_ring_mask;
@@ -604,7 +605,7 @@ enum jme_flags_bits {
 };
 
 #define TX_TIMEOUT             (5 * HZ)
-#define JME_REG_LEN            0x500
+#define JME_REG_LEN            0x600
 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 
 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
@@ -955,12 +956,15 @@ static inline u32 smi_phy_addr(int x)
 
 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 #define JME_PHY_REG_NR 32
+#define JME_PHY_SPEC_REG_NR 128
 
 /*
  * Global Host Control
  */
 enum jme_ghc_bit_mask {
        GHC_SWRST               = 0x40000000,
+       GHC_TO_CLK_SRC          = 0x00C00000,
+       GHC_TXMAC_CLK_SRC       = 0x00300000,
        GHC_DPX                 = 0x00000040,
        GHC_SPEED               = 0x00000030,
        GHC_LINK_POLL           = 0x00000001,
@@ -1139,18 +1143,17 @@ enum jme_gpreg0_vals {
 
 /*
  * General Purpose REG-1
- * Note: All theses bits defined here are for
- *       Chip mode revision 0x11 only
  */
-enum jme_gpreg1_masks {
+enum jme_gpreg1_bit_masks {
+       GPREG1_RXCLKOFF         = 0x04000000,
+       GPREG1_PCREQN           = 0x00020000,
+       GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
+       GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
        GPREG1_INTRDELAYUNIT    = 0x00000018,
        GPREG1_INTRDELAYENABLE  = 0x00000007,
 };
 
 enum jme_gpreg1_vals {
-       GPREG1_HALFMODEPATCH    = 0x00000040,
-       GPREG1_RSSPATCH         = 0x00000020,
-
        GPREG1_INTDLYUNIT_16NS  = 0x00000000,
        GPREG1_INTDLYUNIT_256NS = 0x00000008,
        GPREG1_INTDLYUNIT_1US   = 0x00000010,
@@ -1164,7 +1167,7 @@ enum jme_gpreg1_vals {
        GPREG1_INTDLYEN_6U      = 0x00000006,
        GPREG1_INTDLYEN_7U      = 0x00000007,
 
-       GPREG1_DEFAULT          = 0x00000000,
+       GPREG1_DEFAULT          = GPREG1_PCREQN,
 };
 
 /*
@@ -1376,8 +1379,37 @@ enum jme_phy_reg17_vals {
        PREG17_SPEED_1000M      = 0x8000,
 };
 
+enum jme_phy_gctrl_masks {
+       JME_PHY_GCTRL_TESTMASK  = 0xA000,
+};
+
+enum jme_phy_gctrl_vals {
+       JME_PHY_GCTRL_TESTOFF   = 0x0000,
+       JME_PHY_GCTRL_TESTMODE1 = 0x2000,
+       JME_PHY_GCTRL_TESTMODE2 = 0x4000,
+       JME_PHY_GCTRL_TESTMODE3 = 0x6000,
+       JME_PHY_GCTRL_TESTMODE4 = 0x8000,
+};
+
 #define BMSR_ANCOMP               0x0020
 
+/*
+ * For extended PHY register interface
+ */
+enum jme_phy_spec_regs {
+       JME_PHY_SPEC_ADDR_REG   = 0x1E,
+       JME_PHY_SPEC_DATA_REG   = 0x1F,
+};
+enum jme_phy_spec_addr_bits {
+       JME_PHY_SPEC_REG_READ   = 0x4000u,
+       JME_PHY_SPEC_REG_WRITE  = 0x8000u,
+};
+enum jme_extphy_regs {
+       JME_PHYEXT_COMM0        = 0x30,
+       JME_PHYEXT_COMM1        = 0x31,
+       JME_PHYEXT_COMM2        = 0x32,
+};
+
 /*
  * Workaround
  */
@@ -1396,6 +1428,7 @@ static inline int new_phy_power_ctrl(u8 chip_main_rev)
  */
 static int jme_set_settings(struct net_device *netdev,
                                struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
 static void jme_set_multi(struct net_device *netdev);
 
 #endif