jme: Cleanup PM operations after using new PM API

[jme.git] / jme.h

diff --git a/jme.h b/jme.h
index c3764fc151c97fa23a99a90e53fda532f8d36ec2..1481a62a1f363c1cef2aca41a18e651407848c60 100644 (file)
--- a/jme.h
+++ b/jme.h
@@ -24,9 +24,10 @@
 
 #ifndef __JME_H_INCLUDED__
 #define __JME_H_INCLUDED__
+#include <linux/interrupt.h>
 
 #define DRV_NAME       "jme"
-#define DRV_VERSION    "1.0.7"
+#define DRV_VERSION    "1.0.8"
 #define PFX            DRV_NAME ": "
 
 #define PCI_DEVICE_ID_JMICRON_JMC250   0x0250
@@ -434,6 +435,7 @@ struct jme_adapter {
        u32                     reg_rxmcs;
        u32                     reg_ghc;
        u32                     reg_pmcs;
+       u32                     reg_gpreg1;
        u32                     phylink;
        u32                     tx_ring_size;
        u32                     tx_ring_mask;
@@ -467,8 +469,6 @@ struct jme_adapter {
 enum jme_flags_bits {
        JME_FLAG_MSI            = 1,
        JME_FLAG_SSET           = 2,
-       JME_FLAG_TXCSUM         = 3,
-       JME_FLAG_TSO            = 4,
        JME_FLAG_POLL           = 5,
        JME_FLAG_SHUTDOWN       = 6,
 };
@@ -658,6 +658,14 @@ enum jme_txtrhd_shifts {
        TXTRHD_TXRL_SHIFT       = 0,
 };
 
+enum jme_txtrhd_values {
+       TXTRHD_FULLDUPLEX       = 0x00000000,
+       TXTRHD_HALFDUPLEX       = TXTRHD_TXPEN |
+                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
+                                 TXTRHD_TXREN |
+                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
+};
+
 /*
  * RX Control/Status Bits
  */
@@ -813,6 +821,8 @@ static inline u32 smi_phy_addr(int x)
  */
 enum jme_ghc_bit_mask {
        GHC_SWRST               = 0x40000000,
+       GHC_TO_CLK_SRC          = 0x00C00000,
+       GHC_TXMAC_CLK_SRC       = 0x00300000,
        GHC_DPX                 = 0x00000040,
        GHC_SPEED               = 0x00000030,
        GHC_LINK_POLL           = 0x00000001,
@@ -842,6 +852,7 @@ enum jme_ghc_txmac_clk {
  * Power management control and status register
  */
 enum jme_pmcs_bit_masks {
+       PMCS_STMASK     = 0xFFFF0000,
        PMCS_WF7DET     = 0x80000000,
        PMCS_WF6DET     = 0x40000000,
        PMCS_WF5DET     = 0x20000000,
@@ -853,6 +864,7 @@ enum jme_pmcs_bit_masks {
        PMCS_LFDET      = 0x00040000,
        PMCS_LRDET      = 0x00020000,
        PMCS_MFDET      = 0x00010000,
+       PMCS_ENMASK     = 0x0000FFFF,
        PMCS_WF7EN      = 0x00008000,
        PMCS_WF6EN      = 0x00004000,
        PMCS_WF5EN      = 0x00002000,
@@ -991,18 +1003,17 @@ enum jme_gpreg0_vals {
 
 /*
  * General Purpose REG-1
- * Note: All theses bits defined here are for
- *       Chip mode revision 0x11 only
  */
-enum jme_gpreg1_masks {
+enum jme_gpreg1_bit_masks {
+       GPREG1_RXCLKOFF         = 0x04000000,
+       GPREG1_PCREQN           = 0x00020000,
+       GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
+       GPREG1_RSSPATCH         = 0x00000020, /* For Chip revision 0x11 only */
        GPREG1_INTRDELAYUNIT    = 0x00000018,
        GPREG1_INTRDELAYENABLE  = 0x00000007,
 };
 
 enum jme_gpreg1_vals {
-       GPREG1_RSSPATCH         = 0x00000040,
-       GPREG1_HALFMODEPATCH    = 0x00000020,
-
        GPREG1_INTDLYUNIT_16NS  = 0x00000000,
        GPREG1_INTDLYUNIT_256NS = 0x00000008,
        GPREG1_INTDLYUNIT_1US   = 0x00000010,
@@ -1016,7 +1027,7 @@ enum jme_gpreg1_vals {
        GPREG1_INTDLYEN_6U      = 0x00000006,
        GPREG1_INTDLYEN_7U      = 0x00000007,
 
-       GPREG1_DEFAULT          = 0x00000000,
+       GPREG1_DEFAULT          = GPREG1_PCREQN,
 };
 
 /*
@@ -1248,6 +1259,7 @@ static inline int new_phy_power_ctrl(u8 chip_main_rev)
  */
 static int jme_set_settings(struct net_device *netdev,
                                struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
 static void jme_set_multi(struct net_device *netdev);
 
 #endif