jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #ifndef __JME_H_INCLUDED__
  26 #define __JME_H_INCLUDED__
  27
  28 #define DRV_NAME        "jme"
  29 #define DRV_VERSION     "1.0.7"
  30 #define PFX             DRV_NAME ": "
  31
  32 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
  33 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
  34
  35 /*
  36  * Message related definitions
  37  */
  38 #define JME_DEF_MSG_ENABLE \
  39         (NETIF_MSG_PROBE | \
  40         NETIF_MSG_LINK | \
  41         NETIF_MSG_RX_ERR | \
  42         NETIF_MSG_TX_ERR | \
  43         NETIF_MSG_HW)
  44
  45 #ifdef TX_DEBUG
  46 #define tx_dbg(priv, fmt, args...)                                      \
  47         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
  48 #else
  49 #define tx_dbg(priv, fmt, args...)                                      \
  50 do {                                                                    \
  51         if (0)                                                          \
  52                 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
  53 } while (0)
  54 #endif
  55
  56 /*
  57  * Extra PCI Configuration space interface
  58  */
  59 #define PCI_DCSR_MRRS           0x59
  60 #define PCI_DCSR_MRRS_MASK      0x70
  61
  62 enum pci_dcsr_mrrs_vals {
  63         MRRS_128B       = 0x00,
  64         MRRS_256B       = 0x10,
  65         MRRS_512B       = 0x20,
  66         MRRS_1024B      = 0x30,
  67         MRRS_2048B      = 0x40,
  68         MRRS_4096B      = 0x50,
  69 };
  70
  71 #define PCI_SPI                 0xB0
  72
  73 enum pci_spi_bits {
  74         SPI_EN          = 0x10,
  75         SPI_MISO        = 0x08,
  76         SPI_MOSI        = 0x04,
  77         SPI_SCLK        = 0x02,
  78         SPI_CS          = 0x01,
  79 };
  80
  81 struct jme_spi_op {
  82         void __user *uwbuf;
  83         void __user *urbuf;
  84         __u8    wn;     /* Number of write actions */
  85         __u8    rn;     /* Number of read actions */
  86         __u8    bitn;   /* Number of bits per action */
  87         __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
  88         __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
  89
  90         /* Internal use only */
  91         u8      *kwbuf;
  92         u8      *krbuf;
  93         u8      sr;
  94         u16     halfclk; /* Half of clock cycle calculated from spd, in ns */
  95 };
  96
  97 enum jme_spi_op_bits {
  98         SPI_MODE_CPHA   = 0x01,
  99         SPI_MODE_CPOL   = 0x02,
 100         SPI_MODE_DUP    = 0x80,
 101 };
 102
 103 #define HALF_US 500     /* 500 ns */
 104 #define JMESPIIOCTL     SIOCDEVPRIVATE
 105
 106 #define PCI_PRIV_PE1            0xE4
 107
 108 enum pci_priv_pe1_bit_masks {
 109         PE1_ASPMSUPRT   = 0x00000003, /*
 110                                        * RW:
 111                                        * Aspm_support[1:0]
 112                                        * (R/W Port of 5C[11:10])
 113                                        */
 114         PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
 115         PE1_RDYDMA      = 0x00000008, /* RO: ~link.rdy_for_dma */
 116         PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
 117         PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
 118         PE1_GPREG0      = 0x0000FF00, /*
 119                                        * SRW:
 120                                        * Cfg_gp_reg0
 121                                        * [7:6] phy_giga BG control
 122                                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
 123                                        * [4:0] Reserved
 124                                        */
 125         PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
 126         PE1_GPREG1      = 0x00FF0000, /* RW: Cfg_gp_reg1 */
 127         PE1_REVID       = 0xFF000000, /* RO: Rev ID */
 128 };
 129
 130 enum pci_priv_pe1_values {
 131         PE1_GPREG0_ENBG         = 0x00000000, /* en BG */
 132         PE1_GPREG0_PDD3COLD     = 0x00004000, /* giga_PD + d3cold */
 133         PE1_GPREG0_PDPCIESD     = 0x00008000, /* giga_PD + pcie_shutdown */
 134         PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
 135 };
 136
 137 /*
 138  * Dynamic(adaptive)/Static PCC values
 139  */
 140 enum dynamic_pcc_values {
 141         PCC_OFF         = 0,
 142         PCC_P1          = 1,
 143         PCC_P2          = 2,
 144         PCC_P3          = 3,
 145
 146         PCC_OFF_TO      = 0,
 147         PCC_P1_TO       = 1,
 148         PCC_P2_TO       = 64,
 149         PCC_P3_TO       = 128,
 150
 151         PCC_OFF_CNT     = 0,
 152         PCC_P1_CNT      = 1,
 153         PCC_P2_CNT      = 16,
 154         PCC_P3_CNT      = 32,
 155 };
 156 struct dynpcc_info {
 157         unsigned long   last_bytes;
 158         unsigned long   last_pkts;
 159         unsigned long   intr_cnt;
 160         unsigned char   cur;
 161         unsigned char   attempt;
 162         unsigned char   cnt;
 163 };
 164 #define PCC_INTERVAL_US 100000
 165 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
 166 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
 167 #define PCC_P2_THRESHOLD 800
 168 #define PCC_INTR_THRESHOLD 800
 169 #define PCC_TX_TO 1000
 170 #define PCC_TX_CNT 8
 171
 172 /*
 173  * TX/RX Descriptors
 174  *
 175  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
 176  */
 177 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 178 #define TX_DESC_SIZE            16
 179 #define TX_RING_NR              8
 180 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
 181
 182 struct txdesc {
 183         union {
 184                 __u8    all[16];
 185                 __le32  dw[4];
 186                 struct {
 187                         /* DW0 */
 188                         __le16  vlan;
 189                         __u8    rsv1;
 190                         __u8    flags;
 191
 192                         /* DW1 */
 193                         __le16  datalen;
 194                         __le16  mss;
 195
 196                         /* DW2 */
 197                         __le16  pktsize;
 198                         __le16  rsv2;
 199
 200                         /* DW3 */
 201                         __le32  bufaddr;
 202                 } desc1;
 203                 struct {
 204                         /* DW0 */
 205                         __le16  rsv1;
 206                         __u8    rsv2;
 207                         __u8    flags;
 208
 209                         /* DW1 */
 210                         __le16  datalen;
 211                         __le16  rsv3;
 212
 213                         /* DW2 */
 214                         __le32  bufaddrh;
 215
 216                         /* DW3 */
 217                         __le32  bufaddrl;
 218                 } desc2;
 219                 struct {
 220                         /* DW0 */
 221                         __u8    ehdrsz;
 222                         __u8    rsv1;
 223                         __u8    rsv2;
 224                         __u8    flags;
 225
 226                         /* DW1 */
 227                         __le16  trycnt;
 228                         __le16  segcnt;
 229
 230                         /* DW2 */
 231                         __le16  pktsz;
 232                         __le16  rsv3;
 233
 234                         /* DW3 */
 235                         __le32  bufaddrl;
 236                 } descwb;
 237         };
 238 };
 239
 240 enum jme_txdesc_flags_bits {
 241         TXFLAG_OWN      = 0x80,
 242         TXFLAG_INT      = 0x40,
 243         TXFLAG_64BIT    = 0x20,
 244         TXFLAG_TCPCS    = 0x10,
 245         TXFLAG_UDPCS    = 0x08,
 246         TXFLAG_IPCS     = 0x04,
 247         TXFLAG_LSEN     = 0x02,
 248         TXFLAG_TAGON    = 0x01,
 249 };
 250
 251 #define TXDESC_MSS_SHIFT        2
 252 enum jme_txwbdesc_flags_bits {
 253         TXWBFLAG_OWN    = 0x80,
 254         TXWBFLAG_INT    = 0x40,
 255         TXWBFLAG_TMOUT  = 0x20,
 256         TXWBFLAG_TRYOUT = 0x10,
 257         TXWBFLAG_COL    = 0x08,
 258
 259         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 260                           TXWBFLAG_TRYOUT |
 261                           TXWBFLAG_COL,
 262 };
 263
 264 #define RX_DESC_SIZE            16
 265 #define RX_RING_NR              4
 266 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
 267 #define RX_BUF_DMA_ALIGN        8
 268 #define RX_PREPAD_SIZE          10
 269 #define ETH_CRC_LEN             2
 270 #define RX_VLANHDR_LEN          2
 271 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 272                                 ETH_HLEN + \
 273                                 ETH_CRC_LEN + \
 274                                 RX_VLANHDR_LEN + \
 275                                 RX_BUF_DMA_ALIGN)
 276
 277 struct rxdesc {
 278         union {
 279                 __u8    all[16];
 280                 __le32  dw[4];
 281                 struct {
 282                         /* DW0 */
 283                         __le16  rsv2;
 284                         __u8    rsv1;
 285                         __u8    flags;
 286
 287                         /* DW1 */
 288                         __le16  datalen;
 289                         __le16  wbcpl;
 290
 291                         /* DW2 */
 292                         __le32  bufaddrh;
 293
 294                         /* DW3 */
 295                         __le32  bufaddrl;
 296                 } desc1;
 297                 struct {
 298                         /* DW0 */
 299                         __le16  vlan;
 300                         __le16  flags;
 301
 302                         /* DW1 */
 303                         __le16  framesize;
 304                         __u8    errstat;
 305                         __u8    desccnt;
 306
 307                         /* DW2 */
 308                         __le32  rsshash;
 309
 310                         /* DW3 */
 311                         __u8    hashfun;
 312                         __u8    hashtype;
 313                         __le16  resrv;
 314                 } descwb;
 315         };
 316 };
 317
 318 enum jme_rxdesc_flags_bits {
 319         RXFLAG_OWN      = 0x80,
 320         RXFLAG_INT      = 0x40,
 321         RXFLAG_64BIT    = 0x20,
 322 };
 323
 324 enum jme_rxwbdesc_flags_bits {
 325         RXWBFLAG_OWN            = 0x8000,
 326         RXWBFLAG_INT            = 0x4000,
 327         RXWBFLAG_MF             = 0x2000,
 328         RXWBFLAG_64BIT          = 0x2000,
 329         RXWBFLAG_TCPON          = 0x1000,
 330         RXWBFLAG_UDPON          = 0x0800,
 331         RXWBFLAG_IPCS           = 0x0400,
 332         RXWBFLAG_TCPCS          = 0x0200,
 333         RXWBFLAG_UDPCS          = 0x0100,
 334         RXWBFLAG_TAGON          = 0x0080,
 335         RXWBFLAG_IPV4           = 0x0040,
 336         RXWBFLAG_IPV6           = 0x0020,
 337         RXWBFLAG_PAUSE          = 0x0010,
 338         RXWBFLAG_MAGIC          = 0x0008,
 339         RXWBFLAG_WAKEUP         = 0x0004,
 340         RXWBFLAG_DEST           = 0x0003,
 341         RXWBFLAG_DEST_UNI       = 0x0001,
 342         RXWBFLAG_DEST_MUL       = 0x0002,
 343         RXWBFLAG_DEST_BRO       = 0x0003,
 344 };
 345
 346 enum jme_rxwbdesc_desccnt_mask {
 347         RXWBDCNT_WBCPL  = 0x80,
 348         RXWBDCNT_DCNT   = 0x7F,
 349 };
 350
 351 enum jme_rxwbdesc_errstat_bits {
 352         RXWBERR_LIMIT   = 0x80,
 353         RXWBERR_MIIER   = 0x40,
 354         RXWBERR_NIBON   = 0x20,
 355         RXWBERR_COLON   = 0x10,
 356         RXWBERR_ABORT   = 0x08,
 357         RXWBERR_SHORT   = 0x04,
 358         RXWBERR_OVERUN  = 0x02,
 359         RXWBERR_CRCERR  = 0x01,
 360         RXWBERR_ALLERR  = 0xFF,
 361 };
 362
 363 /*
 364  * Buffer information corresponding to ring descriptors.
 365  */
 366 struct jme_buffer_info {
 367         struct sk_buff *skb;
 368         dma_addr_t mapping;
 369         int len;
 370         int nr_desc;
 371         unsigned long start_xmit;
 372 };
 373
 374 /*
 375  * The structure holding buffer information and ring descriptors all together.
 376  */
 377 struct jme_ring {
 378         void *alloc;            /* pointer to allocated memory */
 379         void *desc;             /* pointer to ring memory  */
 380         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 381         dma_addr_t dma;         /* phys address for ring dma */
 382
 383         /* Buffer information corresponding to each descriptor */
 384         struct jme_buffer_info *bufinf;
 385
 386         int next_to_use;
 387         atomic_t next_to_clean;
 388         atomic_t nr_free;
 389 };
 390
 391 #define NET_STAT(priv) (priv->dev->stats)
 392 #define NETDEV_GET_STATS(netdev, fun_ptr)
 393 #define DECLARE_NET_DEVICE_STATS
 394
 395 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
 396 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
 397         netif_napi_add(dev, napis, pollfn, q);
 398 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
 399 #define JME_NAPI_WEIGHT(w) int w
 400 #define JME_NAPI_WEIGHT_VAL(w) w
 401 #define JME_NAPI_WEIGHT_SET(w, r)
 402 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
 403 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
 404 #define JME_NAPI_DISABLE(priv) \
 405         if (!napi_disable_pending(&priv->napi)) \
 406                 napi_disable(&priv->napi);
 407 #define JME_RX_SCHEDULE_PREP(priv) \
 408         napi_schedule_prep(&priv->napi)
 409 #define JME_RX_SCHEDULE(priv) \
 410         __napi_schedule(&priv->napi);
 411
 412 /*
 413  * Jmac Adapter Private data
 414  */
 415 struct jme_adapter {
 416         struct pci_dev          *pdev;
 417         struct net_device       *dev;
 418         void __iomem            *regs;
 419         struct mii_if_info      mii_if;
 420         struct jme_ring         rxring[RX_RING_NR];
 421         struct jme_ring         txring[TX_RING_NR];
 422         spinlock_t              phy_lock;
 423         spinlock_t              macaddr_lock;
 424         spinlock_t              rxmcs_lock;
 425         struct tasklet_struct   rxempty_task;
 426         struct tasklet_struct   rxclean_task;
 427         struct tasklet_struct   txclean_task;
 428         struct tasklet_struct   linkch_task;
 429         struct tasklet_struct   pcc_task;
 430         unsigned long           flags;
 431         u32                     reg_txcs;
 432         u32                     reg_txpfc;
 433         u32                     reg_rxcs;
 434         u32                     reg_rxmcs;
 435         u32                     reg_ghc;
 436         u32                     reg_pmcs;
 437         u32                     phylink;
 438         u32                     tx_ring_size;
 439         u32                     tx_ring_mask;
 440         u32                     tx_wake_threshold;
 441         u32                     rx_ring_size;
 442         u32                     rx_ring_mask;
 443         u8                      mrrs;
 444         unsigned int            fpgaver;
 445         u8                      chiprev;
 446         u8                      chip_main_rev;
 447         u8                      chip_sub_rev;
 448         u8                      pcirev;
 449         u32                     msg_enable;
 450         struct ethtool_cmd      old_ecmd;
 451         unsigned int            old_mtu;
 452         struct vlan_group       *vlgrp;
 453         struct dynpcc_info      dpi;
 454         atomic_t                intr_sem;
 455         atomic_t                link_changing;
 456         atomic_t                tx_cleaning;
 457         atomic_t                rx_cleaning;
 458         atomic_t                rx_empty;
 459         int                     (*jme_rx)(struct sk_buff *skb);
 460         int                     (*jme_vlan_rx)(struct sk_buff *skb,
 461                                           struct vlan_group *grp,
 462                                           unsigned short vlan_tag);
 463         DECLARE_NAPI_STRUCT
 464         DECLARE_NET_DEVICE_STATS
 465 };
 466
 467 enum jme_flags_bits {
 468         JME_FLAG_MSI            = 1,
 469         JME_FLAG_SSET           = 2,
 470         JME_FLAG_TXCSUM         = 3,
 471         JME_FLAG_TSO            = 4,
 472         JME_FLAG_POLL           = 5,
 473         JME_FLAG_SHUTDOWN       = 6,
 474 };
 475
 476 #define TX_TIMEOUT              (5 * HZ)
 477 #define JME_REG_LEN             0x500
 478 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
 479
 480 static inline struct jme_adapter*
 481 jme_napi_priv(struct napi_struct *napi)
 482 {
 483         struct jme_adapter *jme;
 484         jme = container_of(napi, struct jme_adapter, napi);
 485         return jme;
 486 }
 487
 488 /*
 489  * MMaped I/O Resters
 490  */
 491 enum jme_iomap_offsets {
 492         JME_MAC         = 0x0000,
 493         JME_PHY         = 0x0400,
 494         JME_MISC        = 0x0800,
 495         JME_RSS         = 0x0C00,
 496 };
 497
 498 enum jme_iomap_lens {
 499         JME_MAC_LEN     = 0x80,
 500         JME_PHY_LEN     = 0x58,
 501         JME_MISC_LEN    = 0x98,
 502         JME_RSS_LEN     = 0xFF,
 503 };
 504
 505 enum jme_iomap_regs {
 506         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 507         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 508         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 509         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 510         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 511         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 512         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 513         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 514
 515         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 516         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 517         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 518         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 519         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 520         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 521         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 522         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 523         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 524         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 525         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 526         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 527
 528         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 529         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 530         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 531
 532
 533         JME_PHY_PWR     = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
 534         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 535         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 536         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 537         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
 538
 539
 540         JME_TMCSR       = JME_MISC | 0x00, /* Timer Control/Status Register */
 541         JME_GPREG0      = JME_MISC | 0x08, /* General purpose REG-0 */
 542         JME_GPREG1      = JME_MISC | 0x0C, /* General purpose REG-1 */
 543         JME_IEVE        = JME_MISC | 0x20, /* Interrupt Event Status */
 544         JME_IREQ        = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
 545         JME_IENS        = JME_MISC | 0x28, /* Intr Enable - Setting Port */
 546         JME_IENC        = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
 547         JME_PCCRX0      = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
 548         JME_PCCTX       = JME_MISC | 0x40, /* PCC Control for TX Queues */
 549         JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
 550         JME_SHBA_HI     = JME_MISC | 0x48, /* Shadow Register Base HI */
 551         JME_SHBA_LO     = JME_MISC | 0x4C, /* Shadow Register Base LO */
 552         JME_TIMER1      = JME_MISC | 0x70, /* Timer1 */
 553         JME_TIMER2      = JME_MISC | 0x74, /* Timer2 */
 554         JME_APMC        = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
 555         JME_PCCSRX0     = JME_MISC | 0x80, /* PCC Status of RX0 */
 556 };
 557
 558 /*
 559  * TX Control/Status Bits
 560  */
 561 enum jme_txcs_bits {
 562         TXCS_QUEUE7S    = 0x00008000,
 563         TXCS_QUEUE6S    = 0x00004000,
 564         TXCS_QUEUE5S    = 0x00002000,
 565         TXCS_QUEUE4S    = 0x00001000,
 566         TXCS_QUEUE3S    = 0x00000800,
 567         TXCS_QUEUE2S    = 0x00000400,
 568         TXCS_QUEUE1S    = 0x00000200,
 569         TXCS_QUEUE0S    = 0x00000100,
 570         TXCS_FIFOTH     = 0x000000C0,
 571         TXCS_DMASIZE    = 0x00000030,
 572         TXCS_BURST      = 0x00000004,
 573         TXCS_ENABLE     = 0x00000001,
 574 };
 575
 576 enum jme_txcs_value {
 577         TXCS_FIFOTH_16QW        = 0x000000C0,
 578         TXCS_FIFOTH_12QW        = 0x00000080,
 579         TXCS_FIFOTH_8QW         = 0x00000040,
 580         TXCS_FIFOTH_4QW         = 0x00000000,
 581
 582         TXCS_DMASIZE_64B        = 0x00000000,
 583         TXCS_DMASIZE_128B       = 0x00000010,
 584         TXCS_DMASIZE_256B       = 0x00000020,
 585         TXCS_DMASIZE_512B       = 0x00000030,
 586
 587         TXCS_SELECT_QUEUE0      = 0x00000000,
 588         TXCS_SELECT_QUEUE1      = 0x00010000,
 589         TXCS_SELECT_QUEUE2      = 0x00020000,
 590         TXCS_SELECT_QUEUE3      = 0x00030000,
 591         TXCS_SELECT_QUEUE4      = 0x00040000,
 592         TXCS_SELECT_QUEUE5      = 0x00050000,
 593         TXCS_SELECT_QUEUE6      = 0x00060000,
 594         TXCS_SELECT_QUEUE7      = 0x00070000,
 595
 596         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 597                                   TXCS_BURST,
 598 };
 599
 600 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 601
 602 /*
 603  * TX MAC Control/Status Bits
 604  */
 605 enum jme_txmcs_bit_masks {
 606         TXMCS_IFG2              = 0xC0000000,
 607         TXMCS_IFG1              = 0x30000000,
 608         TXMCS_TTHOLD            = 0x00000300,
 609         TXMCS_FBURST            = 0x00000080,
 610         TXMCS_CARRIEREXT        = 0x00000040,
 611         TXMCS_DEFER             = 0x00000020,
 612         TXMCS_BACKOFF           = 0x00000010,
 613         TXMCS_CARRIERSENSE      = 0x00000008,
 614         TXMCS_COLLISION         = 0x00000004,
 615         TXMCS_CRC               = 0x00000002,
 616         TXMCS_PADDING           = 0x00000001,
 617 };
 618
 619 enum jme_txmcs_values {
 620         TXMCS_IFG2_6_4          = 0x00000000,
 621         TXMCS_IFG2_8_5          = 0x40000000,
 622         TXMCS_IFG2_10_6         = 0x80000000,
 623         TXMCS_IFG2_12_7         = 0xC0000000,
 624
 625         TXMCS_IFG1_8_4          = 0x00000000,
 626         TXMCS_IFG1_12_6         = 0x10000000,
 627         TXMCS_IFG1_16_8         = 0x20000000,
 628         TXMCS_IFG1_20_10        = 0x30000000,
 629
 630         TXMCS_TTHOLD_1_8        = 0x00000000,
 631         TXMCS_TTHOLD_1_4        = 0x00000100,
 632         TXMCS_TTHOLD_1_2        = 0x00000200,
 633         TXMCS_TTHOLD_FULL       = 0x00000300,
 634
 635         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 636                                   TXMCS_IFG1_16_8 |
 637                                   TXMCS_TTHOLD_FULL |
 638                                   TXMCS_DEFER |
 639                                   TXMCS_CRC |
 640                                   TXMCS_PADDING,
 641 };
 642
 643 enum jme_txpfc_bits_masks {
 644         TXPFC_VLAN_TAG          = 0xFFFF0000,
 645         TXPFC_VLAN_EN           = 0x00008000,
 646         TXPFC_PF_EN             = 0x00000001,
 647 };
 648
 649 enum jme_txtrhd_bits_masks {
 650         TXTRHD_TXPEN            = 0x80000000,
 651         TXTRHD_TXP              = 0x7FFFFF00,
 652         TXTRHD_TXREN            = 0x00000080,
 653         TXTRHD_TXRL             = 0x0000007F,
 654 };
 655
 656 enum jme_txtrhd_shifts {
 657         TXTRHD_TXP_SHIFT        = 8,
 658         TXTRHD_TXRL_SHIFT       = 0,
 659 };
 660
 661 /*
 662  * RX Control/Status Bits
 663  */
 664 enum jme_rxcs_bit_masks {
 665         /* FIFO full threshold for transmitting Tx Pause Packet */
 666         RXCS_FIFOTHTP   = 0x30000000,
 667         /* FIFO threshold for processing next packet */
 668         RXCS_FIFOTHNP   = 0x0C000000,
 669         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 670         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 671         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 672         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 673         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 674         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 675         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 676         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 677         RXCS_QST        = 0x00000004, /* Receive queue start */
 678         RXCS_SUSPEND    = 0x00000002,
 679         RXCS_ENABLE     = 0x00000001,
 680 };
 681
 682 enum jme_rxcs_values {
 683         RXCS_FIFOTHTP_16T       = 0x00000000,
 684         RXCS_FIFOTHTP_32T       = 0x10000000,
 685         RXCS_FIFOTHTP_64T       = 0x20000000,
 686         RXCS_FIFOTHTP_128T      = 0x30000000,
 687
 688         RXCS_FIFOTHNP_16QW      = 0x00000000,
 689         RXCS_FIFOTHNP_32QW      = 0x04000000,
 690         RXCS_FIFOTHNP_64QW      = 0x08000000,
 691         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 692
 693         RXCS_DMAREQSZ_16B       = 0x00000000,
 694         RXCS_DMAREQSZ_32B       = 0x01000000,
 695         RXCS_DMAREQSZ_64B       = 0x02000000,
 696         RXCS_DMAREQSZ_128B      = 0x03000000,
 697
 698         RXCS_QUEUESEL_Q0        = 0x00000000,
 699         RXCS_QUEUESEL_Q1        = 0x00010000,
 700         RXCS_QUEUESEL_Q2        = 0x00020000,
 701         RXCS_QUEUESEL_Q3        = 0x00030000,
 702
 703         RXCS_RETRYGAP_256ns     = 0x00000000,
 704         RXCS_RETRYGAP_512ns     = 0x00001000,
 705         RXCS_RETRYGAP_1024ns    = 0x00002000,
 706         RXCS_RETRYGAP_2048ns    = 0x00003000,
 707         RXCS_RETRYGAP_4096ns    = 0x00004000,
 708         RXCS_RETRYGAP_8192ns    = 0x00005000,
 709         RXCS_RETRYGAP_16384ns   = 0x00006000,
 710         RXCS_RETRYGAP_32768ns   = 0x00007000,
 711
 712         RXCS_RETRYCNT_0         = 0x00000000,
 713         RXCS_RETRYCNT_4         = 0x00000100,
 714         RXCS_RETRYCNT_8         = 0x00000200,
 715         RXCS_RETRYCNT_12        = 0x00000300,
 716         RXCS_RETRYCNT_16        = 0x00000400,
 717         RXCS_RETRYCNT_20        = 0x00000500,
 718         RXCS_RETRYCNT_24        = 0x00000600,
 719         RXCS_RETRYCNT_28        = 0x00000700,
 720         RXCS_RETRYCNT_32        = 0x00000800,
 721         RXCS_RETRYCNT_36        = 0x00000900,
 722         RXCS_RETRYCNT_40        = 0x00000A00,
 723         RXCS_RETRYCNT_44        = 0x00000B00,
 724         RXCS_RETRYCNT_48        = 0x00000C00,
 725         RXCS_RETRYCNT_52        = 0x00000D00,
 726         RXCS_RETRYCNT_56        = 0x00000E00,
 727         RXCS_RETRYCNT_60        = 0x00000F00,
 728
 729         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 730                                   RXCS_FIFOTHNP_128QW |
 731                                   RXCS_DMAREQSZ_128B |
 732                                   RXCS_RETRYGAP_256ns |
 733                                   RXCS_RETRYCNT_32,
 734 };
 735
 736 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 737
 738 /*
 739  * RX MAC Control/Status Bits
 740  */
 741 enum jme_rxmcs_bits {
 742         RXMCS_ALLFRAME          = 0x00000800,
 743         RXMCS_BRDFRAME          = 0x00000400,
 744         RXMCS_MULFRAME          = 0x00000200,
 745         RXMCS_UNIFRAME          = 0x00000100,
 746         RXMCS_ALLMULFRAME       = 0x00000080,
 747         RXMCS_MULFILTERED       = 0x00000040,
 748         RXMCS_RXCOLLDEC         = 0x00000020,
 749         RXMCS_FLOWCTRL          = 0x00000008,
 750         RXMCS_VTAGRM            = 0x00000004,
 751         RXMCS_PREPAD            = 0x00000002,
 752         RXMCS_CHECKSUM          = 0x00000001,
 753
 754         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 755                                   RXMCS_PREPAD |
 756                                   RXMCS_FLOWCTRL |
 757                                   RXMCS_CHECKSUM,
 758 };
 759
 760 /*
 761  * Wakeup Frame setup interface registers
 762  */
 763 #define WAKEUP_FRAME_NR 8
 764 #define WAKEUP_FRAME_MASK_DWNR  4
 765
 766 enum jme_wfoi_bit_masks {
 767         WFOI_MASK_SEL           = 0x00000070,
 768         WFOI_CRC_SEL            = 0x00000008,
 769         WFOI_FRAME_SEL          = 0x00000007,
 770 };
 771
 772 enum jme_wfoi_shifts {
 773         WFOI_MASK_SHIFT         = 4,
 774 };
 775
 776 /*
 777  * SMI Related definitions
 778  */
 779 enum jme_smi_bit_mask {
 780         SMI_DATA_MASK           = 0xFFFF0000,
 781         SMI_REG_ADDR_MASK       = 0x0000F800,
 782         SMI_PHY_ADDR_MASK       = 0x000007C0,
 783         SMI_OP_WRITE            = 0x00000020,
 784         /* Set to 1, after req done it'll be cleared to 0 */
 785         SMI_OP_REQ              = 0x00000010,
 786         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 787         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 788         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 789         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 790 };
 791
 792 enum jme_smi_bit_shift {
 793         SMI_DATA_SHIFT          = 16,
 794         SMI_REG_ADDR_SHIFT      = 11,
 795         SMI_PHY_ADDR_SHIFT      = 6,
 796 };
 797
 798 static inline u32 smi_reg_addr(int x)
 799 {
 800         return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
 801 }
 802
 803 static inline u32 smi_phy_addr(int x)
 804 {
 805         return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
 806 }
 807
 808 #define JME_PHY_TIMEOUT 100 /* 100 msec */
 809 #define JME_PHY_REG_NR 32
 810
 811 /*
 812  * Global Host Control
 813  */
 814 enum jme_ghc_bit_mask {
 815         GHC_SWRST               = 0x40000000,
 816         GHC_DPX                 = 0x00000040,
 817         GHC_SPEED               = 0x00000030,
 818         GHC_LINK_POLL           = 0x00000001,
 819 };
 820
 821 enum jme_ghc_speed_val {
 822         GHC_SPEED_10M           = 0x00000010,
 823         GHC_SPEED_100M          = 0x00000020,
 824         GHC_SPEED_1000M         = 0x00000030,
 825 };
 826
 827 enum jme_ghc_to_clk {
 828         GHC_TO_CLK_OFF          = 0x00000000,
 829         GHC_TO_CLK_GPHY         = 0x00400000,
 830         GHC_TO_CLK_PCIE         = 0x00800000,
 831         GHC_TO_CLK_INVALID      = 0x00C00000,
 832 };
 833
 834 enum jme_ghc_txmac_clk {
 835         GHC_TXMAC_CLK_OFF       = 0x00000000,
 836         GHC_TXMAC_CLK_GPHY      = 0x00100000,
 837         GHC_TXMAC_CLK_PCIE      = 0x00200000,
 838         GHC_TXMAC_CLK_INVALID   = 0x00300000,
 839 };
 840
 841 /*
 842  * Power management control and status register
 843  */
 844 enum jme_pmcs_bit_masks {
 845         PMCS_WF7DET     = 0x80000000,
 846         PMCS_WF6DET     = 0x40000000,
 847         PMCS_WF5DET     = 0x20000000,
 848         PMCS_WF4DET     = 0x10000000,
 849         PMCS_WF3DET     = 0x08000000,
 850         PMCS_WF2DET     = 0x04000000,
 851         PMCS_WF1DET     = 0x02000000,
 852         PMCS_WF0DET     = 0x01000000,
 853         PMCS_LFDET      = 0x00040000,
 854         PMCS_LRDET      = 0x00020000,
 855         PMCS_MFDET      = 0x00010000,
 856         PMCS_WF7EN      = 0x00008000,
 857         PMCS_WF6EN      = 0x00004000,
 858         PMCS_WF5EN      = 0x00002000,
 859         PMCS_WF4EN      = 0x00001000,
 860         PMCS_WF3EN      = 0x00000800,
 861         PMCS_WF2EN      = 0x00000400,
 862         PMCS_WF1EN      = 0x00000200,
 863         PMCS_WF0EN      = 0x00000100,
 864         PMCS_LFEN       = 0x00000004,
 865         PMCS_LREN       = 0x00000002,
 866         PMCS_MFEN       = 0x00000001,
 867 };
 868
 869 /*
 870  * New PHY Power Control Register
 871  */
 872 enum jme_phy_pwr_bit_masks {
 873         PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
 874         PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
 875         PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
 876         PHY_PWR_CLKSEL  = 0x08000000, /*
 877                                        * XTL_OUT Clock select
 878                                        * (an internal free-running clock)
 879                                        * 0: xtl_out = phy_giga.A_XTL25_O
 880                                        * 1: xtl_out = phy_giga.PD_OSC
 881                                        */
 882 };
 883
 884 /*
 885  * Giga PHY Status Registers
 886  */
 887 enum jme_phy_link_bit_mask {
 888         PHY_LINK_SPEED_MASK             = 0x0000C000,
 889         PHY_LINK_DUPLEX                 = 0x00002000,
 890         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 891         PHY_LINK_UP                     = 0x00000400,
 892         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 893         PHY_LINK_MDI_STAT               = 0x00000040,
 894 };
 895
 896 enum jme_phy_link_speed_val {
 897         PHY_LINK_SPEED_10M              = 0x00000000,
 898         PHY_LINK_SPEED_100M             = 0x00004000,
 899         PHY_LINK_SPEED_1000M            = 0x00008000,
 900 };
 901
 902 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
 903
 904 /*
 905  * SMB Control and Status
 906  */
 907 enum jme_smbcsr_bit_mask {
 908         SMBCSR_CNACK    = 0x00020000,
 909         SMBCSR_RELOAD   = 0x00010000,
 910         SMBCSR_EEPROMD  = 0x00000020,
 911         SMBCSR_INITDONE = 0x00000010,
 912         SMBCSR_BUSY     = 0x0000000F,
 913 };
 914
 915 enum jme_smbintf_bit_mask {
 916         SMBINTF_HWDATR  = 0xFF000000,
 917         SMBINTF_HWDATW  = 0x00FF0000,
 918         SMBINTF_HWADDR  = 0x0000FF00,
 919         SMBINTF_HWRWN   = 0x00000020,
 920         SMBINTF_HWCMD   = 0x00000010,
 921         SMBINTF_FASTM   = 0x00000008,
 922         SMBINTF_GPIOSCL = 0x00000004,
 923         SMBINTF_GPIOSDA = 0x00000002,
 924         SMBINTF_GPIOEN  = 0x00000001,
 925 };
 926
 927 enum jme_smbintf_vals {
 928         SMBINTF_HWRWN_READ      = 0x00000020,
 929         SMBINTF_HWRWN_WRITE     = 0x00000000,
 930 };
 931
 932 enum jme_smbintf_shifts {
 933         SMBINTF_HWDATR_SHIFT    = 24,
 934         SMBINTF_HWDATW_SHIFT    = 16,
 935         SMBINTF_HWADDR_SHIFT    = 8,
 936 };
 937
 938 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
 939 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
 940 #define JME_SMB_LEN 256
 941 #define JME_EEPROM_MAGIC 0x250
 942
 943 /*
 944  * Timer Control/Status Register
 945  */
 946 enum jme_tmcsr_bit_masks {
 947         TMCSR_SWIT      = 0x80000000,
 948         TMCSR_EN        = 0x01000000,
 949         TMCSR_CNT       = 0x00FFFFFF,
 950 };
 951
 952 /*
 953  * General Purpose REG-0
 954  */
 955 enum jme_gpreg0_masks {
 956         GPREG0_DISSH            = 0xFF000000,
 957         GPREG0_PCIRLMT          = 0x00300000,
 958         GPREG0_PCCNOMUTCLR      = 0x00040000,
 959         GPREG0_LNKINTPOLL       = 0x00001000,
 960         GPREG0_PCCTMR           = 0x00000300,
 961         GPREG0_PHYADDR          = 0x0000001F,
 962 };
 963
 964 enum jme_gpreg0_vals {
 965         GPREG0_DISSH_DW7        = 0x80000000,
 966         GPREG0_DISSH_DW6        = 0x40000000,
 967         GPREG0_DISSH_DW5        = 0x20000000,
 968         GPREG0_DISSH_DW4        = 0x10000000,
 969         GPREG0_DISSH_DW3        = 0x08000000,
 970         GPREG0_DISSH_DW2        = 0x04000000,
 971         GPREG0_DISSH_DW1        = 0x02000000,
 972         GPREG0_DISSH_DW0        = 0x01000000,
 973         GPREG0_DISSH_ALL        = 0xFF000000,
 974
 975         GPREG0_PCIRLMT_8        = 0x00000000,
 976         GPREG0_PCIRLMT_6        = 0x00100000,
 977         GPREG0_PCIRLMT_5        = 0x00200000,
 978         GPREG0_PCIRLMT_4        = 0x00300000,
 979
 980         GPREG0_PCCTMR_16ns      = 0x00000000,
 981         GPREG0_PCCTMR_256ns     = 0x00000100,
 982         GPREG0_PCCTMR_1us       = 0x00000200,
 983         GPREG0_PCCTMR_1ms       = 0x00000300,
 984
 985         GPREG0_PHYADDR_1        = 0x00000001,
 986
 987         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
 988                                   GPREG0_PCCTMR_1us |
 989                                   GPREG0_PHYADDR_1,
 990 };
 991
 992 /*
 993  * General Purpose REG-1
 994  * Note: All theses bits defined here are for
 995  *       Chip mode revision 0x11 only
 996  */
 997 enum jme_gpreg1_masks {
 998         GPREG1_INTRDELAYUNIT    = 0x00000018,
 999         GPREG1_INTRDELAYENABLE  = 0x00000007,
1000 };
1001
1002 enum jme_gpreg1_vals {
1003         GPREG1_RSSPATCH         = 0x00000040,
1004         GPREG1_HALFMODEPATCH    = 0x00000020,
1005
1006         GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1007         GPREG1_INTDLYUNIT_256NS = 0x00000008,
1008         GPREG1_INTDLYUNIT_1US   = 0x00000010,
1009         GPREG1_INTDLYUNIT_16US  = 0x00000018,
1010
1011         GPREG1_INTDLYEN_1U      = 0x00000001,
1012         GPREG1_INTDLYEN_2U      = 0x00000002,
1013         GPREG1_INTDLYEN_3U      = 0x00000003,
1014         GPREG1_INTDLYEN_4U      = 0x00000004,
1015         GPREG1_INTDLYEN_5U      = 0x00000005,
1016         GPREG1_INTDLYEN_6U      = 0x00000006,
1017         GPREG1_INTDLYEN_7U      = 0x00000007,
1018
1019         GPREG1_DEFAULT          = 0x00000000,
1020 };
1021
1022 /*
1023  * Interrupt Status Bits
1024  */
1025 enum jme_interrupt_bits {
1026         INTR_SWINTR     = 0x80000000,
1027         INTR_TMINTR     = 0x40000000,
1028         INTR_LINKCH     = 0x20000000,
1029         INTR_PAUSERCV   = 0x10000000,
1030         INTR_MAGICRCV   = 0x08000000,
1031         INTR_WAKERCV    = 0x04000000,
1032         INTR_PCCRX0TO   = 0x02000000,
1033         INTR_PCCRX1TO   = 0x01000000,
1034         INTR_PCCRX2TO   = 0x00800000,
1035         INTR_PCCRX3TO   = 0x00400000,
1036         INTR_PCCTXTO    = 0x00200000,
1037         INTR_PCCRX0     = 0x00100000,
1038         INTR_PCCRX1     = 0x00080000,
1039         INTR_PCCRX2     = 0x00040000,
1040         INTR_PCCRX3     = 0x00020000,
1041         INTR_PCCTX      = 0x00010000,
1042         INTR_RX3EMP     = 0x00008000,
1043         INTR_RX2EMP     = 0x00004000,
1044         INTR_RX1EMP     = 0x00002000,
1045         INTR_RX0EMP     = 0x00001000,
1046         INTR_RX3        = 0x00000800,
1047         INTR_RX2        = 0x00000400,
1048         INTR_RX1        = 0x00000200,
1049         INTR_RX0        = 0x00000100,
1050         INTR_TX7        = 0x00000080,
1051         INTR_TX6        = 0x00000040,
1052         INTR_TX5        = 0x00000020,
1053         INTR_TX4        = 0x00000010,
1054         INTR_TX3        = 0x00000008,
1055         INTR_TX2        = 0x00000004,
1056         INTR_TX1        = 0x00000002,
1057         INTR_TX0        = 0x00000001,
1058 };
1059
1060 static const u32 INTR_ENABLE = INTR_SWINTR |
1061                                  INTR_TMINTR |
1062                                  INTR_LINKCH |
1063                                  INTR_PCCRX0TO |
1064                                  INTR_PCCRX0 |
1065                                  INTR_PCCTXTO |
1066                                  INTR_PCCTX |
1067                                  INTR_RX0EMP;
1068
1069 /*
1070  * PCC Control Registers
1071  */
1072 enum jme_pccrx_masks {
1073         PCCRXTO_MASK    = 0xFFFF0000,
1074         PCCRX_MASK      = 0x0000FF00,
1075 };
1076
1077 enum jme_pcctx_masks {
1078         PCCTXTO_MASK    = 0xFFFF0000,
1079         PCCTX_MASK      = 0x0000FF00,
1080         PCCTX_QS_MASK   = 0x000000FF,
1081 };
1082
1083 enum jme_pccrx_shifts {
1084         PCCRXTO_SHIFT   = 16,
1085         PCCRX_SHIFT     = 8,
1086 };
1087
1088 enum jme_pcctx_shifts {
1089         PCCTXTO_SHIFT   = 16,
1090         PCCTX_SHIFT     = 8,
1091 };
1092
1093 enum jme_pcctx_bits {
1094         PCCTXQ0_EN      = 0x00000001,
1095         PCCTXQ1_EN      = 0x00000002,
1096         PCCTXQ2_EN      = 0x00000004,
1097         PCCTXQ3_EN      = 0x00000008,
1098         PCCTXQ4_EN      = 0x00000010,
1099         PCCTXQ5_EN      = 0x00000020,
1100         PCCTXQ6_EN      = 0x00000040,
1101         PCCTXQ7_EN      = 0x00000080,
1102 };
1103
1104 /*
1105  * Chip Mode Register
1106  */
1107 enum jme_chipmode_bit_masks {
1108         CM_FPGAVER_MASK         = 0xFFFF0000,
1109         CM_CHIPREV_MASK         = 0x0000FF00,
1110         CM_CHIPMODE_MASK        = 0x0000000F,
1111 };
1112
1113 enum jme_chipmode_shifts {
1114         CM_FPGAVER_SHIFT        = 16,
1115         CM_CHIPREV_SHIFT        = 8,
1116 };
1117
1118 /*
1119  * Aggressive Power Mode Control
1120  */
1121 enum jme_apmc_bits {
1122         JME_APMC_PCIE_SD_EN     = 0x40000000,
1123         JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1124         JME_APMC_EPIEN          = 0x04000000,
1125         JME_APMC_EPIEN_CTRL     = 0x03000000,
1126 };
1127
1128 enum jme_apmc_values {
1129         JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1130         JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1131 };
1132
1133 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1134
1135 #ifdef REG_DEBUG
1136 static char *MAC_REG_NAME[] = {
1137         "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1138         "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1139         "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1140         "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1141         "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1142         "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1143         "JME_PMCS"};
1144
1145 static char *PE_REG_NAME[] = {
1146         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1147         "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1148         "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1149         "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1150         "JME_SMBCSR",   "JME_SMBINTF"};
1151
1152 static char *MISC_REG_NAME[] = {
1153         "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1154         "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1155         "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1156         "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1157         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1158         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1159         "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1160         "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1161         "JME_PCCSRX0"};
1162
1163 static inline void reg_dbg(const struct jme_adapter *jme,
1164                 const char *msg, u32 val, u32 reg)
1165 {
1166         const char *regname;
1167         switch (reg & 0xF00) {
1168         case 0x000:
1169                 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1170                 break;
1171         case 0x400:
1172                 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1173                 break;
1174         case 0x800:
1175                 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1176                 break;
1177         default:
1178                 regname = PE_REG_NAME[0];
1179         }
1180         printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1181                         msg, val, regname);
1182 }
1183 #else
1184 static inline void reg_dbg(const struct jme_adapter *jme,
1185                 const char *msg, u32 val, u32 reg) {}
1186 #endif
1187
1188 /*
1189  * Read/Write MMaped I/O Registers
1190  */
1191 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1192 {
1193         return readl(jme->regs + reg);
1194 }
1195
1196 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1197 {
1198         reg_dbg(jme, "REG WRITE", val, reg);
1199         writel(val, jme->regs + reg);
1200         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1201 }
1202
1203 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1204 {
1205         /*
1206          * Read after write should cause flush
1207          */
1208         reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1209         writel(val, jme->regs + reg);
1210         readl(jme->regs + reg);
1211         reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1212 }
1213
1214 /*
1215  * PHY Regs
1216  */
1217 enum jme_phy_reg17_bit_masks {
1218         PREG17_SPEED            = 0xC000,
1219         PREG17_DUPLEX           = 0x2000,
1220         PREG17_SPDRSV           = 0x0800,
1221         PREG17_LNKUP            = 0x0400,
1222         PREG17_MDI              = 0x0040,
1223 };
1224
1225 enum jme_phy_reg17_vals {
1226         PREG17_SPEED_10M        = 0x0000,
1227         PREG17_SPEED_100M       = 0x4000,
1228         PREG17_SPEED_1000M      = 0x8000,
1229 };
1230
1231 #define BMSR_ANCOMP               0x0020
1232
1233 /*
1234  * Workaround
1235  */
1236 static inline int is_buggy250(unsigned short device, u8 chiprev)
1237 {
1238         return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1239 }
1240
1241 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1242 {
1243         return chip_main_rev >= 5;
1244 }
1245
1246 /*
1247  * Function prototypes
1248  */
1249 static int jme_set_settings(struct net_device *netdev,
1250                                 struct ethtool_cmd *ecmd);
1251 static void jme_set_multi(struct net_device *netdev);
1252
1253 #endif