2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/version.h>
26 #define DRV_NAME "jme"
27 #define DRV_VERSION "0.9d"
28 #define PFX DRV_NAME ": "
30 #define JME_GE_DEVICE 0x250
31 #define JME_FE_DEVICE 0x260
34 #define dprintk(devname, fmt, args...) \
35 printk(KERN_DEBUG "%s: " fmt, devname, ## args)
37 #define dprintk(devname, fmt, args...)
41 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
43 #define tx_dbg(args...)
47 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
49 #define rx_dbg(args...)
53 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
55 #define queue_dbg(args...)
59 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
61 #define csum_dbg(args...)
65 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
67 #define vlan_dbg(args...)
70 #define jprintk(devname, fmt, args...) \
71 printk(KERN_INFO "%s: " fmt, devname, ## args)
73 #define jeprintk(devname, fmt, args...) \
74 printk(KERN_ERR "%s: " fmt, devname, ## args)
76 #define DEFAULT_MSG_ENABLE \
84 #define PCI_CONF_DCSR_MRRS 0x59
85 #define PCI_CONF_DCSR_MRRS_MASK 0x70
86 enum pci_conf_dcsr_mrrs_vals {
95 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
96 #define MIN_ETHERNET_PACKET_SIZE 60
98 enum dynamic_pcc_values {
115 unsigned long last_bytes;
116 unsigned long last_pkts;
117 unsigned long intr_cnt;
119 unsigned char attempt;
122 #define PCC_INTERVAL_US 100000
123 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
124 #define PCC_P3_THRESHOLD 2*1024*1024
125 #define PCC_P2_THRESHOLD 800
126 #define PCC_INTR_THRESHOLD 800
127 #define PCC_TX_TO 333
133 * TX/RX Ring DESC Count Must be multiple of 16
134 * RX Ring DESC Count Must be <= 1024
136 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
138 #define TX_DESC_SIZE 16
140 #define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
199 enum jme_txdesc_flags_bits {
209 #define TXDESC_MSS_SHIFT 2
210 enum jme_rxdescwb_flags_bits {
213 TXWBFLAG_TMOUT = 0x20,
214 TXWBFLAG_TRYOUT = 0x10,
217 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
223 #define RX_DESC_SIZE 16
225 #define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
227 #define RX_BUF_DMA_ALIGN 8
228 #define RX_PREPAD_SIZE 10
229 #define ETH_CRC_LEN 2
230 #define RX_VLANHDR_LEN 2
231 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
277 enum jme_rxdesc_flags_bits {
282 enum jme_rxwbdesc_flags_bits {
283 RXWBFLAG_OWN = 0x8000,
284 RXWBFLAG_INT = 0x4000,
285 RXWBFLAG_MF = 0x2000,
286 RXWBFLAG_64BIT = 0x2000,
287 RXWBFLAG_TCPON = 0x1000,
288 RXWBFLAG_UDPON = 0x0800,
289 RXWBFLAG_IPCS = 0x0400,
290 RXWBFLAG_TCPCS = 0x0200,
291 RXWBFLAG_UDPCS = 0x0100,
292 RXWBFLAG_TAGON = 0x0080,
293 RXWBFLAG_IPV4 = 0x0040,
294 RXWBFLAG_IPV6 = 0x0020,
295 RXWBFLAG_PAUSE = 0x0010,
296 RXWBFLAG_MAGIC = 0x0008,
297 RXWBFLAG_WAKEUP = 0x0004,
298 RXWBFLAG_DEST = 0x0003,
299 RXWBFLAG_DEST_UNI = 0x0001,
300 RXWBFLAG_DEST_MUL = 0x0002,
301 RXWBFLAG_DEST_BRO = 0x0003,
303 enum jme_rxwbdesc_desccnt_mask {
304 RXWBDCNT_WBCPL = 0x80,
305 RXWBDCNT_DCNT = 0x7F,
307 enum jme_rxwbdesc_errstat_bits {
308 RXWBERR_LIMIT = 0x80,
309 RXWBERR_MIIER = 0x40,
310 RXWBERR_NIBON = 0x20,
311 RXWBERR_COLON = 0x10,
312 RXWBERR_ABORT = 0x08,
313 RXWBERR_SHORT = 0x04,
314 RXWBERR_OVERUN = 0x02,
315 RXWBERR_CRCERR = 0x01,
316 RXWBERR_ALLERR = 0xFF,
319 struct jme_buffer_info {
324 unsigned long start_xmit;
327 #define MAX_RING_DESC_NR 1024
329 void* alloc; /* pointer to allocated memory */
330 volatile void* desc; /* pointer to ring memory */
331 dma_addr_t dmaalloc; /* phys address of ring alloc */
332 dma_addr_t dma; /* phys address for ring dma */
334 /* Buffer information corresponding to each descriptor */
335 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
338 atomic_t next_to_clean;
342 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
343 #define NET_STAT(priv) priv->stats
344 #define NETDEV_GET_STATS(netdev, fun_ptr) \
345 netdev->get_stats = fun_ptr
346 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
348 #define NET_STAT(priv) priv->dev->stats
349 #define NETDEV_GET_STATS(netdev, fun_ptr)
350 #define DECLARE_NET_DEVICE_STATS
353 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
354 #define DECLARE_NAPI_STRUCT
355 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
356 dev->poll = pollfn; \
358 #define JME_NAPI_HOLDER(holder) struct net_device *holder
359 #define JME_NAPI_WEIGHT(w) int *w
360 #define JME_NAPI_WEIGHT_VAL(w) *w
361 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
362 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
363 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
364 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
365 #define JME_RX_SCHEDULE_PREP(priv) \
366 netif_rx_schedule_prep(priv->dev)
367 #define JME_RX_SCHEDULE(priv) \
368 __netif_rx_schedule(priv->dev);
370 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
371 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
372 netif_napi_add(dev, napis, pollfn, q);
373 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
374 #define JME_NAPI_WEIGHT(w) int w
375 #define JME_NAPI_WEIGHT_VAL(w) w
376 #define JME_NAPI_WEIGHT_SET(w, r)
377 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
378 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
379 #define JME_NAPI_DISABLE(priv) \
380 if(!napi_disable_pending(&priv->napi)) \
381 napi_disable(&priv->napi);
382 #define JME_RX_SCHEDULE_PREP(priv) \
383 netif_rx_schedule_prep(priv->dev, &priv->napi)
384 #define JME_RX_SCHEDULE(priv) \
385 __netif_rx_schedule(priv->dev, &priv->napi);
389 * Jmac Adapter Private data
391 #define SHADOW_REG_NR 8
393 struct pci_dev *pdev;
394 struct net_device *dev;
396 dma_addr_t shadow_dma;
398 struct mii_if_info mii_if;
399 struct jme_ring rxring[RX_RING_NR];
400 struct jme_ring txring[TX_RING_NR];
402 spinlock_t macaddr_lock;
403 spinlock_t rxmcs_lock;
404 struct tasklet_struct rxempty_task;
405 struct tasklet_struct rxclean_task;
406 struct tasklet_struct txclean_task;
407 struct tasklet_struct linkch_task;
408 struct tasklet_struct pcc_task;
419 __u32 tx_wake_threshold;
425 struct ethtool_cmd old_ecmd;
426 unsigned int old_mtu;
427 struct vlan_group* vlgrp;
428 struct dynpcc_info dpi;
430 atomic_t link_changing;
431 atomic_t tx_cleaning;
432 atomic_t rx_cleaning;
434 int (*jme_rx)(struct sk_buff *skb);
435 int (*jme_vlan_rx)(struct sk_buff *skb,
436 struct vlan_group *grp,
437 unsigned short vlan_tag);
439 DECLARE_NET_DEVICE_STATS
441 enum shadow_reg_val {
444 enum jme_flags_bits {
445 JME_FLAG_MSI = 0x00000001,
446 JME_FLAG_SSET = 0x00000002,
447 JME_FLAG_TXCSUM = 0x00000004,
448 JME_FLAG_TSO = 0x00000008,
449 JME_FLAG_POLL = 0x00000010,
451 #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
452 #define TX_TIMEOUT (5*HZ)
453 #define JME_REG_LEN 0x500
455 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
456 __always_inline static struct jme_adapter*
457 jme_napi_priv(struct net_device *holder)
459 struct jme_adapter* jme;
460 jme = netdev_priv(holder);
464 __always_inline static struct jme_adapter*
465 jme_napi_priv(struct napi_struct *napi)
467 struct jme_adapter* jme;
468 jme = container_of(napi, struct jme_adapter, napi);
476 enum jme_iomap_offsets {
483 enum jme_iomap_lens {
490 enum jme_iomap_regs {
491 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
492 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
493 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
494 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
495 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
496 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
497 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
498 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
500 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
501 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
502 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
503 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
504 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
505 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
506 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
507 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
508 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
509 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
510 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
511 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
513 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
514 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
515 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
518 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
519 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
520 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
521 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
524 JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */
525 JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */
526 JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */
527 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
528 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
529 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
530 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
531 JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
532 JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */
533 JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */
534 JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */
535 JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */
536 JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */
540 * TX Control/Status Bits
543 TXCS_QUEUE7S = 0x00008000,
544 TXCS_QUEUE6S = 0x00004000,
545 TXCS_QUEUE5S = 0x00002000,
546 TXCS_QUEUE4S = 0x00001000,
547 TXCS_QUEUE3S = 0x00000800,
548 TXCS_QUEUE2S = 0x00000400,
549 TXCS_QUEUE1S = 0x00000200,
550 TXCS_QUEUE0S = 0x00000100,
551 TXCS_FIFOTH = 0x000000C0,
552 TXCS_DMASIZE = 0x00000030,
553 TXCS_BURST = 0x00000004,
554 TXCS_ENABLE = 0x00000001,
556 enum jme_txcs_value {
557 TXCS_FIFOTH_16QW = 0x000000C0,
558 TXCS_FIFOTH_12QW = 0x00000080,
559 TXCS_FIFOTH_8QW = 0x00000040,
560 TXCS_FIFOTH_4QW = 0x00000000,
562 TXCS_DMASIZE_64B = 0x00000000,
563 TXCS_DMASIZE_128B = 0x00000010,
564 TXCS_DMASIZE_256B = 0x00000020,
565 TXCS_DMASIZE_512B = 0x00000030,
567 TXCS_SELECT_QUEUE0 = 0x00000000,
568 TXCS_SELECT_QUEUE1 = 0x00010000,
569 TXCS_SELECT_QUEUE2 = 0x00020000,
570 TXCS_SELECT_QUEUE3 = 0x00030000,
571 TXCS_SELECT_QUEUE4 = 0x00040000,
572 TXCS_SELECT_QUEUE5 = 0x00050000,
573 TXCS_SELECT_QUEUE6 = 0x00060000,
574 TXCS_SELECT_QUEUE7 = 0x00070000,
576 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
579 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
582 * TX MAC Control/Status Bits
584 enum jme_txmcs_bit_masks {
585 TXMCS_IFG2 = 0xC0000000,
586 TXMCS_IFG1 = 0x30000000,
587 TXMCS_TTHOLD = 0x00000300,
588 TXMCS_FBURST = 0x00000080,
589 TXMCS_CARRIEREXT = 0x00000040,
590 TXMCS_DEFER = 0x00000020,
591 TXMCS_BACKOFF = 0x00000010,
592 TXMCS_CARRIERSENSE = 0x00000008,
593 TXMCS_COLLISION = 0x00000004,
594 TXMCS_CRC = 0x00000002,
595 TXMCS_PADDING = 0x00000001,
597 enum jme_txmcs_values {
598 TXMCS_IFG2_6_4 = 0x00000000,
599 TXMCS_IFG2_8_5 = 0x40000000,
600 TXMCS_IFG2_10_6 = 0x80000000,
601 TXMCS_IFG2_12_7 = 0xC0000000,
603 TXMCS_IFG1_8_4 = 0x00000000,
604 TXMCS_IFG1_12_6 = 0x10000000,
605 TXMCS_IFG1_16_8 = 0x20000000,
606 TXMCS_IFG1_20_10 = 0x30000000,
608 TXMCS_TTHOLD_1_8 = 0x00000000,
609 TXMCS_TTHOLD_1_4 = 0x00000100,
610 TXMCS_TTHOLD_1_2 = 0x00000200,
611 TXMCS_TTHOLD_FULL = 0x00000300,
613 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
621 enum jme_txpfc_bits_masks {
622 TXPFC_VLAN_TAG = 0xFFFF0000,
623 TXPFC_VLAN_EN = 0x00008000,
624 TXPFC_PF_EN = 0x00000001,
627 enum jme_txtrhd_bits_masks {
628 TXTRHD_TXPEN = 0x80000000,
629 TXTRHD_TXP = 0x7FFFFF00,
630 TXTRHD_TXREN = 0x00000080,
631 TXTRHD_TXRL = 0x0000007F,
633 enum jme_txtrhd_shifts {
634 TXTRHD_TXP_SHIFT = 8,
635 TXTRHD_TXRL_SHIFT = 0,
640 * RX Control/Status Bits
642 enum jme_rxcs_bit_masks {
643 /* FIFO full threshold for transmitting Tx Pause Packet */
644 RXCS_FIFOTHTP = 0x30000000,
645 /* FIFO threshold for processing next packet */
646 RXCS_FIFOTHNP = 0x0C000000,
647 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
648 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
649 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
650 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
651 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
652 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
653 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
654 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
655 RXCS_QST = 0x00000004, /* Receive queue start */
656 RXCS_SUSPEND = 0x00000002,
657 RXCS_ENABLE = 0x00000001,
659 enum jme_rxcs_values {
660 RXCS_FIFOTHTP_16T = 0x00000000,
661 RXCS_FIFOTHTP_32T = 0x10000000,
662 RXCS_FIFOTHTP_64T = 0x20000000,
663 RXCS_FIFOTHTP_128T = 0x30000000,
665 RXCS_FIFOTHNP_16QW = 0x00000000,
666 RXCS_FIFOTHNP_32QW = 0x04000000,
667 RXCS_FIFOTHNP_64QW = 0x08000000,
668 RXCS_FIFOTHNP_128QW = 0x0C000000,
670 RXCS_DMAREQSZ_16B = 0x00000000,
671 RXCS_DMAREQSZ_32B = 0x01000000,
672 RXCS_DMAREQSZ_64B = 0x02000000,
673 RXCS_DMAREQSZ_128B = 0x03000000,
675 RXCS_QUEUESEL_Q0 = 0x00000000,
676 RXCS_QUEUESEL_Q1 = 0x00010000,
677 RXCS_QUEUESEL_Q2 = 0x00020000,
678 RXCS_QUEUESEL_Q3 = 0x00030000,
680 RXCS_RETRYGAP_256ns = 0x00000000,
681 RXCS_RETRYGAP_512ns = 0x00001000,
682 RXCS_RETRYGAP_1024ns = 0x00002000,
683 RXCS_RETRYGAP_2048ns = 0x00003000,
684 RXCS_RETRYGAP_4096ns = 0x00004000,
685 RXCS_RETRYGAP_8192ns = 0x00005000,
686 RXCS_RETRYGAP_16384ns = 0x00006000,
687 RXCS_RETRYGAP_32768ns = 0x00007000,
689 RXCS_RETRYCNT_0 = 0x00000000,
690 RXCS_RETRYCNT_4 = 0x00000100,
691 RXCS_RETRYCNT_8 = 0x00000200,
692 RXCS_RETRYCNT_12 = 0x00000300,
693 RXCS_RETRYCNT_16 = 0x00000400,
694 RXCS_RETRYCNT_20 = 0x00000500,
695 RXCS_RETRYCNT_24 = 0x00000600,
696 RXCS_RETRYCNT_28 = 0x00000700,
697 RXCS_RETRYCNT_32 = 0x00000800,
698 RXCS_RETRYCNT_36 = 0x00000900,
699 RXCS_RETRYCNT_40 = 0x00000A00,
700 RXCS_RETRYCNT_44 = 0x00000B00,
701 RXCS_RETRYCNT_48 = 0x00000C00,
702 RXCS_RETRYCNT_52 = 0x00000D00,
703 RXCS_RETRYCNT_56 = 0x00000E00,
704 RXCS_RETRYCNT_60 = 0x00000F00,
706 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
707 RXCS_FIFOTHNP_128QW |
709 RXCS_RETRYGAP_256ns |
712 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
715 * RX MAC Control/Status Bits
717 enum jme_rxmcs_bits {
718 RXMCS_ALLFRAME = 0x00000800,
719 RXMCS_BRDFRAME = 0x00000400,
720 RXMCS_MULFRAME = 0x00000200,
721 RXMCS_UNIFRAME = 0x00000100,
722 RXMCS_ALLMULFRAME = 0x00000080,
723 RXMCS_MULFILTERED = 0x00000040,
724 RXMCS_RXCOLLDEC = 0x00000020,
725 RXMCS_FLOWCTRL = 0x00000008,
726 RXMCS_VTAGRM = 0x00000004,
727 RXMCS_PREPAD = 0x00000002,
728 RXMCS_CHECKSUM = 0x00000001,
730 RXMCS_DEFAULT = RXMCS_VTAGRM |
737 * Wakeup Frame setup interface registers
739 #define WAKEUP_FRAME_NR 8
740 #define WAKEUP_FRAME_MASK_DWNR 4
741 enum jme_wfoi_bit_masks {
742 WFOI_MASK_SEL = 0x00000070,
743 WFOI_CRC_SEL = 0x00000008,
744 WFOI_FRAME_SEL = 0x00000007,
746 enum jme_wfoi_shifts {
751 * SMI Related definitions
753 enum jme_smi_bit_mask
755 SMI_DATA_MASK = 0xFFFF0000,
756 SMI_REG_ADDR_MASK = 0x0000F800,
757 SMI_PHY_ADDR_MASK = 0x000007C0,
758 SMI_OP_WRITE = 0x00000020,
759 /* Set to 1, after req done it'll be cleared to 0 */
760 SMI_OP_REQ = 0x00000010,
761 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
762 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
763 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
764 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
766 enum jme_smi_bit_shift
769 SMI_REG_ADDR_SHIFT = 11,
770 SMI_PHY_ADDR_SHIFT = 6,
772 __always_inline __u32 smi_reg_addr(int x)
774 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
776 __always_inline __u32 smi_phy_addr(int x)
778 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
780 #define JME_PHY_TIMEOUT 100 /* 100 msec */
781 #define JME_PHY_REG_NR 32
784 * Global Host Control
786 enum jme_ghc_bit_mask {
787 GHC_SWRST = 0x40000000,
788 GHC_DPX = 0x00000040,
789 GHC_SPEED = 0x00000030,
790 GHC_LINK_POLL = 0x00000001,
792 enum jme_ghc_speed_val {
793 GHC_SPEED_10M = 0x00000010,
794 GHC_SPEED_100M = 0x00000020,
795 GHC_SPEED_1000M = 0x00000030,
799 * Power management control and status register
801 enum jme_pmcs_bit_masks {
802 PMCS_WF7DET = 0x80000000,
803 PMCS_WF6DET = 0x40000000,
804 PMCS_WF5DET = 0x20000000,
805 PMCS_WF4DET = 0x10000000,
806 PMCS_WF3DET = 0x08000000,
807 PMCS_WF2DET = 0x04000000,
808 PMCS_WF1DET = 0x02000000,
809 PMCS_WF0DET = 0x01000000,
810 PMCS_LFDET = 0x00040000,
811 PMCS_LRDET = 0x00020000,
812 PMCS_MFDET = 0x00010000,
813 PMCS_WF7EN = 0x00008000,
814 PMCS_WF6EN = 0x00004000,
815 PMCS_WF5EN = 0x00002000,
816 PMCS_WF4EN = 0x00001000,
817 PMCS_WF3EN = 0x00000800,
818 PMCS_WF2EN = 0x00000400,
819 PMCS_WF1EN = 0x00000200,
820 PMCS_WF0EN = 0x00000100,
821 PMCS_LFEN = 0x00000004,
822 PMCS_LREN = 0x00000002,
823 PMCS_MFEN = 0x00000001,
827 * Giga PHY Status Registers
829 enum jme_phy_link_bit_mask {
830 PHY_LINK_SPEED_MASK = 0x0000C000,
831 PHY_LINK_DUPLEX = 0x00002000,
832 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
833 PHY_LINK_UP = 0x00000400,
834 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
835 PHY_LINK_MDI_STAT = 0x00000040,
837 enum jme_phy_link_speed_val {
838 PHY_LINK_SPEED_10M = 0x00000000,
839 PHY_LINK_SPEED_100M = 0x00004000,
840 PHY_LINK_SPEED_1000M = 0x00008000,
842 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
845 * SMB Control and Status
847 enum jme_smbcsr_bit_mask {
848 SMBCSR_CNACK = 0x00020000,
849 SMBCSR_RELOAD = 0x00010000,
850 SMBCSR_EEPROMD = 0x00000020,
851 SMBCSR_INITDONE = 0x00000010,
852 SMBCSR_BUSY = 0x0000000F,
854 enum jme_smbintf_bit_mask {
855 SMBINTF_HWDATR = 0xFF000000,
856 SMBINTF_HWDATW = 0x00FF0000,
857 SMBINTF_HWADDR = 0x0000FF00,
858 SMBINTF_HWRWN = 0x00000020,
859 SMBINTF_HWCMD = 0x00000010,
860 SMBINTF_FASTM = 0x00000008,
861 SMBINTF_GPIOSCL = 0x00000004,
862 SMBINTF_GPIOSDA = 0x00000002,
863 SMBINTF_GPIOEN = 0x00000001,
865 enum jme_smbintf_vals {
866 SMBINTF_HWRWN_READ = 0x00000020,
867 SMBINTF_HWRWN_WRITE = 0x00000000,
869 enum jme_smbintf_shifts {
870 SMBINTF_HWDATR_SHIFT = 24,
871 SMBINTF_HWDATW_SHIFT = 16,
872 SMBINTF_HWADDR_SHIFT = 8,
874 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
875 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
876 #define JME_SMB_LEN 256
877 #define JME_EEPROM_MAGIC 0x250
880 * Timer Control/Status Register
882 enum jme_tmcsr_bit_masks {
883 TMCSR_SWIT = 0x80000000,
884 TMCSR_EN = 0x01000000,
885 TMCSR_CNT = 0x00FFFFFF,
890 * General Purpost REG-0
892 enum jme_gpreg0_masks {
893 GPREG0_DISSH = 0xFF000000,
894 GPREG0_PCIRLMT = 0x00300000,
895 GPREG0_PCCNOMUTCLR = 0x00040000,
896 GPREG0_LNKINTPOLL = 0x00001000,
897 GPREG0_PCCTMR = 0x00000300,
898 GPREG0_PHYADDR = 0x0000001F,
900 enum jme_gpreg0_vals {
901 GPREG0_DISSH_DW7 = 0x80000000,
902 GPREG0_DISSH_DW6 = 0x40000000,
903 GPREG0_DISSH_DW5 = 0x20000000,
904 GPREG0_DISSH_DW4 = 0x10000000,
905 GPREG0_DISSH_DW3 = 0x08000000,
906 GPREG0_DISSH_DW2 = 0x04000000,
907 GPREG0_DISSH_DW1 = 0x02000000,
908 GPREG0_DISSH_DW0 = 0x01000000,
909 GPREG0_DISSH_ALL = 0xFF000000,
911 GPREG0_PCIRLMT_8 = 0x00000000,
912 GPREG0_PCIRLMT_6 = 0x00100000,
913 GPREG0_PCIRLMT_5 = 0x00200000,
914 GPREG0_PCIRLMT_4 = 0x00300000,
916 GPREG0_PCCTMR_16ns = 0x00000000,
917 GPREG0_PCCTMR_256ns = 0x00000100,
918 GPREG0_PCCTMR_1us = 0x00000200,
919 GPREG0_PCCTMR_1ms = 0x00000300,
921 GPREG0_PHYADDR_1 = 0x00000001,
923 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
930 * Interrupt Status Bits
932 enum jme_interrupt_bits
934 INTR_SWINTR = 0x80000000,
935 INTR_TMINTR = 0x40000000,
936 INTR_LINKCH = 0x20000000,
937 INTR_PAUSERCV = 0x10000000,
938 INTR_MAGICRCV = 0x08000000,
939 INTR_WAKERCV = 0x04000000,
940 INTR_PCCRX0TO = 0x02000000,
941 INTR_PCCRX1TO = 0x01000000,
942 INTR_PCCRX2TO = 0x00800000,
943 INTR_PCCRX3TO = 0x00400000,
944 INTR_PCCTXTO = 0x00200000,
945 INTR_PCCRX0 = 0x00100000,
946 INTR_PCCRX1 = 0x00080000,
947 INTR_PCCRX2 = 0x00040000,
948 INTR_PCCRX3 = 0x00020000,
949 INTR_PCCTX = 0x00010000,
950 INTR_RX3EMP = 0x00008000,
951 INTR_RX2EMP = 0x00004000,
952 INTR_RX1EMP = 0x00002000,
953 INTR_RX0EMP = 0x00001000,
954 INTR_RX3 = 0x00000800,
955 INTR_RX2 = 0x00000400,
956 INTR_RX1 = 0x00000200,
957 INTR_RX0 = 0x00000100,
958 INTR_TX7 = 0x00000080,
959 INTR_TX6 = 0x00000040,
960 INTR_TX5 = 0x00000020,
961 INTR_TX4 = 0x00000010,
962 INTR_TX3 = 0x00000008,
963 INTR_TX2 = 0x00000004,
964 INTR_TX1 = 0x00000002,
965 INTR_TX0 = 0x00000001,
967 static const __u32 INTR_ENABLE = INTR_SWINTR |
977 * PCC Control Registers
979 enum jme_pccrx_masks {
980 PCCRXTO_MASK = 0xFFFF0000,
981 PCCRX_MASK = 0x0000FF00,
983 enum jme_pcctx_masks {
984 PCCTXTO_MASK = 0xFFFF0000,
985 PCCTX_MASK = 0x0000FF00,
986 PCCTX_QS_MASK = 0x000000FF,
988 enum jme_pccrx_shifts {
992 enum jme_pcctx_shifts {
996 enum jme_pcctx_bits {
997 PCCTXQ0_EN = 0x00000001,
998 PCCTXQ1_EN = 0x00000002,
999 PCCTXQ2_EN = 0x00000004,
1000 PCCTXQ3_EN = 0x00000008,
1001 PCCTXQ4_EN = 0x00000010,
1002 PCCTXQ5_EN = 0x00000020,
1003 PCCTXQ6_EN = 0x00000040,
1004 PCCTXQ7_EN = 0x00000080,
1008 * Chip Mode Register
1010 enum jme_chipmode_bit_masks {
1011 CM_FPGAVER_MASK = 0xFFFF0000,
1012 CM_CHIPVER_MASK = 0x0000FF00,
1013 CM_CHIPMODE_MASK = 0x0000000F,
1015 enum jme_chipmode_shifts {
1016 CM_FPGAVER_SHIFT = 16,
1017 CM_CHIPVER_SHIFT = 8,
1021 * Shadow base address register bits
1023 enum jme_shadow_base_address_bits {
1028 * Read/Write MMaped I/O Registers
1030 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
1032 return le32_to_cpu(readl((__u8*)jme->regs + reg));
1034 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
1036 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1038 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
1041 * Read after write should cause flush
1043 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1044 readl((__u8*)jme->regs + reg);
1050 enum jme_phy_reg17_bit_masks {
1051 PREG17_SPEED = 0xC000,
1052 PREG17_DUPLEX = 0x2000,
1053 PREG17_SPDRSV = 0x0800,
1054 PREG17_LNKUP = 0x0400,
1055 PREG17_MDI = 0x0040,
1057 enum jme_phy_reg17_vals {
1058 PREG17_SPEED_10M = 0x0000,
1059 PREG17_SPEED_100M = 0x4000,
1060 PREG17_SPEED_1000M = 0x8000,
1062 #define BMSR_ANCOMP 0x0020
1065 * Function prototypes for ethtool
1067 static void jme_get_drvinfo(struct net_device *netdev,
1068 struct ethtool_drvinfo *info);
1069 static int jme_get_settings(struct net_device *netdev,
1070 struct ethtool_cmd *ecmd);
1071 static int jme_set_settings(struct net_device *netdev,
1072 struct ethtool_cmd *ecmd);
1073 static u32 jme_get_link(struct net_device *netdev);
1077 * Function prototypes for netdev
1079 static int jme_open(struct net_device *netdev);
1080 static int jme_close(struct net_device *netdev);
1081 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
1082 static int jme_set_macaddr(struct net_device *netdev, void *p);
1083 static void jme_set_multi(struct net_device *netdev);