Import jme 0.8 source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/version.h>
25
26 #define DRV_NAME        "jme"
27 #define DRV_VERSION     "0.8"
28 #define PFX DRV_NAME    ": "
29
30 #ifdef DEBUG
31 #define dprintk(devname, fmt, args...) \
32         printk(KERN_DEBUG "%s: " fmt, devname, ## args)
33 #else
34 #define dprintk(devname, fmt, args...)
35 #endif
36
37 #ifdef TX_DEBUG
38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
39 #else
40 #define tx_dbg(args...)
41 #endif
42
43 #ifdef RX_DEBUG
44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
45 #else
46 #define rx_dbg(args...)
47 #endif
48
49 #ifdef QUEUE_DEBUG
50 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
51 #else
52 #define queue_dbg(args...)
53 #endif
54
55 #ifdef CSUM_DEBUG
56 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
57 #else
58 #define csum_dbg(args...)
59 #endif
60
61 #define jprintk(devname, fmt, args...) \
62         printk(KERN_INFO "%s: " fmt, devname, ## args)
63
64 #define jeprintk(devname, fmt, args...) \
65         printk(KERN_ERR "%s: " fmt, devname, ## args)
66
67 #define DEFAULT_MSG_ENABLE        \
68         (NETIF_MSG_DRV          | \
69          NETIF_MSG_PROBE        | \
70          NETIF_MSG_LINK         | \
71          NETIF_MSG_TIMER        | \
72          NETIF_MSG_RX_ERR       | \
73          NETIF_MSG_TX_ERR)
74
75 #define PCI_CONF_DCSR_MRRS      0x59
76 #define PCI_CONF_DCSR_MRRS_MASK 0x70
77 enum pci_conf_dcsr_mrrs_vals {
78         MRRS_128B       = 0x00,
79         MRRS_256B       = 0x10,
80         MRRS_512B       = 0x20,
81         MRRS_1024B      = 0x30,
82         MRRS_2048B      = 0x40,
83         MRRS_4096B      = 0x50,
84 };
85
86 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
87 #define MIN_ETHERNET_PACKET_SIZE 60
88
89 enum dynamic_pcc_values {
90         PCC_P1          = 1,
91         PCC_P2          = 2,
92         PCC_P3          = 3,
93
94         PCC_P1_TO       = 1,
95         PCC_P2_TO       = 250,
96         PCC_P3_TO       = 1000,
97
98         PCC_P1_CNT      = 1,
99         PCC_P2_CNT      = 64,
100         PCC_P3_CNT      = 255,
101 };
102 struct dynpcc_info {
103         unsigned long   last_bytes;
104         unsigned long   last_pkts;
105         unsigned long   intr_cnt;
106         unsigned char   cur;
107         unsigned char   attempt;
108         unsigned char   cnt;
109 };
110 #define PCC_INTERVAL_US 100000
111 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
112 #define PCC_P3_THRESHOLD 3*1024*1024
113 #define PCC_P2_THRESHOLD 800
114 #define PCC_INTR_THRESHOLD 800
115 #define PCC_TX_TO 100
116 #define PCC_TX_CNT 16
117
118 /*
119  * TX/RX Descriptors
120  *
121  * TX/RX Ring DESC Count Must be multiple of 16
122  * RX Ring DESC Count Must be <= 1024
123  */
124 #define RING_DESC_NR            512     /* Must be power of 2 */
125 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
126
127 #define TX_DESC_SIZE            16
128 #define TX_RING_NR              8
129 #define TX_RING_ALLOC_SIZE      (RING_DESC_NR * TX_DESC_SIZE) + TX_DESC_SIZE
130 #define TX_RING_SIZE            (RING_DESC_NR * TX_DESC_SIZE)
131
132 struct txdesc {
133         union {
134                 __u8  all[16];
135                 __u32 dw[4];
136                 struct {
137                         /* DW0 */
138                         __u16 vlan;
139                         __u8 rsv1;
140                         __u8 flags;
141
142                         /* DW1 */
143                         __u16 datalen;
144                         __u16 mss;
145
146                         /* DW2 */
147                         __u16 pktsize;
148                         __u16 rsv2;
149
150                         /* DW3 */
151                         __u32 bufaddr;
152                 } desc1;
153                 struct {
154                         /* DW0 */
155                         __u16 rsv1;
156                         __u8 rsv2;
157                         __u8 flags;
158
159                         /* DW1 */
160                         __u16 datalen;
161                         __u16 rsv3;
162
163                         /* DW2 */
164                         __u32 bufaddrh;
165
166                         /* DW3 */
167                         __u32 bufaddrl;
168                 } desc2;
169                 struct {
170                         /* DW0 */
171                         __u8 ehdrsz;
172                         __u8 rsv1;
173                         __u8 rsv2;
174                         __u8 flags;
175
176                         /* DW1 */
177                         __u16 trycnt;
178                         __u16 segcnt;
179
180                         /* DW2 */
181                         __u16 pktsz;
182                         __u16 rsv3;
183
184                         /* DW3 */
185                         __u32 bufaddrl;
186                 } descwb;
187         };
188 };
189 enum jme_txdesc_flags_bits {
190         TXFLAG_OWN      = 0x80,
191         TXFLAG_INT      = 0x40,
192         TXFLAG_64BIT    = 0x20,
193         TXFLAG_TCPCS    = 0x10,
194         TXFLAG_UDPCS    = 0x08,
195         TXFLAG_IPCS     = 0x04,
196         TXFLAG_LSEN     = 0x02,
197         TXFLAG_TAGON    = 0x01,
198 };
199 enum jme_rxdescwb_flags_bits {
200         TXWBFLAG_OWN    = 0x80,
201         TXWBFLAG_INT    = 0x40,
202         TXWBFLAG_TMOUT  = 0x20,
203         TXWBFLAG_TRYOUT = 0x10,
204         TXWBFLAG_COL    = 0x08,
205
206         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
207                           TXWBFLAG_TRYOUT |
208                           TXWBFLAG_COL,
209 };
210
211
212 #define RX_DESC_SIZE            16
213 #define RX_RING_NR              4
214 #define RX_RING_ALLOC_SIZE      (RING_DESC_NR * RX_DESC_SIZE) + RX_DESC_SIZE
215 #define RX_RING_SIZE            (RING_DESC_NR * RX_DESC_SIZE)
216
217 #define RX_BUF_DMA_ALIGN        8
218 #define RX_PREPAD_SIZE          10
219 #define ETH_CRC_LEN             2
220 #define RX_VLANHDR_LEN          2
221 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
222                                 ETH_HLEN + \
223                                 ETH_CRC_LEN + \
224                                 RX_VLANHDR_LEN + \
225                                 RX_BUF_DMA_ALIGN)
226
227 struct rxdesc {
228         union {
229                 __u8   all[16];
230                 __le32 dw[4];
231                 struct {
232                         /* DW0 */
233                         __le16 rsv2;
234                         __u8 rsv1;
235                         __u8 flags;
236
237                         /* DW1 */
238                         __le16 datalen;
239                         __le16 wbcpl;
240
241                         /* DW2 */
242                         __le32 bufaddrh;
243
244                         /* DW3 */
245                         __le32 bufaddrl;
246                 } desc1;
247                 struct {
248                         /* DW0 */
249                         __le16 vlan;
250                         __le16 flags;
251
252                         /* DW1 */
253                         __le16 framesize;
254                         __u8 errstat;
255                         __u8 desccnt;
256
257                         /* DW2 */
258                         __le32 rsshash;
259
260                         /* DW3 */
261                         __u8   hashfun;
262                         __u8   hashtype;
263                         __le16 resrv;
264                 } descwb;
265         };
266 };
267 enum jme_rxdesc_flags_bits {
268         RXFLAG_OWN      = 0x80,
269         RXFLAG_INT      = 0x40,
270         RXFLAG_64BIT    = 0x20,
271 };
272 enum jme_rxwbdesc_flags_bits {
273         RXWBFLAG_OWN            = 0x8000,
274         RXWBFLAG_INT            = 0x4000,
275         RXWBFLAG_MF             = 0x2000,
276         RXWBFLAG_64BIT          = 0x2000,
277         RXWBFLAG_TCPON          = 0x1000,
278         RXWBFLAG_UDPON          = 0x0800,
279         RXWBFLAG_IPCS           = 0x0400,
280         RXWBFLAG_TCPCS          = 0x0200,
281         RXWBFLAG_UDPCS          = 0x0100,
282         RXWBFLAG_TAGON          = 0x0080,
283         RXWBFLAG_IPV4           = 0x0040,
284         RXWBFLAG_IPV6           = 0x0020,
285         RXWBFLAG_PAUSE          = 0x0010,
286         RXWBFLAG_MAGIC          = 0x0008,
287         RXWBFLAG_WAKEUP         = 0x0004,
288         RXWBFLAG_DEST           = 0x0003,
289         RXWBFLAG_DEST_UNI       = 0x0001,
290         RXWBFLAG_DEST_MUL       = 0x0002,
291         RXWBFLAG_DEST_BRO       = 0x0003,
292 };
293 enum jme_rxwbdesc_desccnt_mask {
294         RXWBDCNT_WBCPL  = 0x80,
295         RXWBDCNT_DCNT   = 0x7F,
296 };
297 enum jme_rxwbdesc_errstat_bits {
298         RXWBERR_LIMIT   = 0x80,
299         RXWBERR_MIIER   = 0x40,
300         RXWBERR_NIBON   = 0x20,
301         RXWBERR_COLON   = 0x10,
302         RXWBERR_ABORT   = 0x08,
303         RXWBERR_SHORT   = 0x04,
304         RXWBERR_OVERUN  = 0x02,
305         RXWBERR_CRCERR  = 0x01,
306         RXWBERR_ALLERR  = 0xFF,
307 };
308
309 struct jme_buffer_info {
310         struct sk_buff *skb;
311         dma_addr_t mapping;
312         int len;
313         int nr_desc;
314 };
315
316 struct jme_ring {
317         void* alloc;            /* pointer to allocated memory */
318         volatile void* desc;    /* pointer to ring memory  */
319         dma_addr_t dmaalloc;    /* phys address of ring alloc */
320         dma_addr_t dma;         /* phys address for ring dma */
321
322         /* Buffer information corresponding to each descriptor */
323         struct jme_buffer_info bufinf[RING_DESC_NR];
324
325         u16 next_to_use;
326         u16 next_to_clean;
327
328         atomic_t nr_free;
329 };
330
331 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
332 #define NET_STAT(priv) priv->stats
333 #define NETDEV_GET_STATS(netdev, fun_ptr) \
334         netdev->get_stats = fun_ptr
335 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
336 #else
337 #define NET_STAT(priv) priv->dev->stats
338 #define NETDEV_GET_STATS(netdev, fun_ptr)
339 #define DECLARE_NET_DEVICE_STATS
340 #endif
341
342 /*
343  * Jmac Adapter Private data
344  */
345 #define SHADOW_REG_NR 8
346 struct jme_adapter {
347         struct pci_dev          *pdev;
348         struct net_device       *dev;
349         void __iomem            *regs;
350         dma_addr_t              shadow_dma;
351         __u32                   *shadow_regs;
352         struct mii_if_info      mii_if;
353         struct jme_ring         rxring[RX_RING_NR];
354         struct jme_ring         txring[TX_RING_NR];
355         spinlock_t              phy_lock;
356         spinlock_t              macaddr_lock;
357         spinlock_t              rxmcs_lock;
358         struct tasklet_struct   rxempty_task;
359         struct tasklet_struct   rxclean_task;
360         struct tasklet_struct   txclean_task;
361         struct tasklet_struct   linkch_task;
362         struct tasklet_struct   pcc_task;
363         __u32                   flags;
364         __u32                   reg_txcs;
365         __u32                   reg_txpfc;
366         __u32                   reg_rxcs;
367         __u32                   reg_rxmcs;
368         __u32                   reg_ghc;
369         __u32                   reg_pmcs;
370         __u32                   phylink;
371         __u8                    mrrs;
372         struct ethtool_cmd      old_ecmd;
373         unsigned int            old_mtu;
374         struct vlan_group*      vlgrp;
375         struct dynpcc_info      dpi;
376         atomic_t                intr_sem;
377         atomic_t                link_changing;
378         atomic_t                tx_cleaning;
379         atomic_t                rx_cleaning;
380         DECLARE_NET_DEVICE_STATS
381 };
382 enum shadow_reg_val {
383         SHADOW_IEVE = 0,
384 };
385 enum jme_flags_bits {
386         JME_FLAG_MSI            = 0x00000001,
387         JME_FLAG_SSET           = 0x00000002,
388 };
389 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
390 #define TX_TIMEOUT              (5*HZ)
391
392
393 /*
394  * MMaped I/O Resters
395  */
396 enum jme_iomap_offsets {
397         JME_MAC         = 0x0000,
398         JME_PHY         = 0x0400,
399         JME_MISC        = 0x0800,
400         JME_RSS         = 0x0C00,
401 };
402
403 enum jme_iomap_lens {
404         JME_MAC_LEN     = 0x80,
405         JME_PHY_LEN     = 0x58,
406         JME_MISC_LEN    = 0x98,
407         JME_RSS_LEN     = 0xFF,
408 };
409
410 enum jme_iomap_regs {
411         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
412         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
413         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
414         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
415         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
416         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
417         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
418         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
419
420         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
421         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
422         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
423         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
424         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
425         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
426         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
427         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
428         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
429         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
430         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
431         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
432
433         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
434         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
435         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
436
437
438         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
439         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
440         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
441
442
443         JME_TMCSR       = JME_MISC| 0x00, /* Timer Control/Status Register */
444         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
445         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
446         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
447         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
448         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
449         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
450         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
451         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
452         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
453         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
454         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
455 };
456
457 /*
458  * TX Control/Status Bits
459  */
460 enum jme_txcs_bits {
461         TXCS_QUEUE7S    = 0x00008000,
462         TXCS_QUEUE6S    = 0x00004000,
463         TXCS_QUEUE5S    = 0x00002000,
464         TXCS_QUEUE4S    = 0x00001000,
465         TXCS_QUEUE3S    = 0x00000800,
466         TXCS_QUEUE2S    = 0x00000400,
467         TXCS_QUEUE1S    = 0x00000200,
468         TXCS_QUEUE0S    = 0x00000100,
469         TXCS_FIFOTH     = 0x000000C0,
470         TXCS_DMASIZE    = 0x00000030,
471         TXCS_BURST      = 0x00000004,
472         TXCS_ENABLE     = 0x00000001,
473 };
474 enum jme_txcs_value {
475         TXCS_FIFOTH_16QW        = 0x000000C0,
476         TXCS_FIFOTH_12QW        = 0x00000080,
477         TXCS_FIFOTH_8QW         = 0x00000040,
478         TXCS_FIFOTH_4QW         = 0x00000000,
479
480         TXCS_DMASIZE_64B        = 0x00000000,
481         TXCS_DMASIZE_128B       = 0x00000010,
482         TXCS_DMASIZE_256B       = 0x00000020,
483         TXCS_DMASIZE_512B       = 0x00000030,
484
485         TXCS_SELECT_QUEUE0      = 0x00000000,
486         TXCS_SELECT_QUEUE1      = 0x00010000,
487         TXCS_SELECT_QUEUE2      = 0x00020000,
488         TXCS_SELECT_QUEUE3      = 0x00030000,
489         TXCS_SELECT_QUEUE4      = 0x00040000,
490         TXCS_SELECT_QUEUE5      = 0x00050000,
491         TXCS_SELECT_QUEUE6      = 0x00060000,
492         TXCS_SELECT_QUEUE7      = 0x00070000,
493
494         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
495                                   TXCS_BURST,
496 };
497 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
498
499 /*
500  * TX MAC Control/Status Bits
501  */
502 enum jme_txmcs_bit_masks {
503         TXMCS_IFG2              = 0xC0000000,
504         TXMCS_IFG1              = 0x30000000,
505         TXMCS_TTHOLD            = 0x00000300,
506         TXMCS_FBURST            = 0x00000080,
507         TXMCS_CARRIEREXT        = 0x00000040,
508         TXMCS_DEFER             = 0x00000020,
509         TXMCS_BACKOFF           = 0x00000010,
510         TXMCS_CARRIERSENSE      = 0x00000008,
511         TXMCS_COLLISION         = 0x00000004,
512         TXMCS_CRC               = 0x00000002,
513         TXMCS_PADDING           = 0x00000001,
514 };
515 enum jme_txmcs_values {
516         TXMCS_IFG2_6_4          = 0x00000000,
517         TXMCS_IFG2_8_5          = 0x40000000,
518         TXMCS_IFG2_10_6         = 0x80000000,
519         TXMCS_IFG2_12_7         = 0xC0000000,
520
521         TXMCS_IFG1_8_4          = 0x00000000,
522         TXMCS_IFG1_12_6         = 0x10000000,
523         TXMCS_IFG1_16_8         = 0x20000000,
524         TXMCS_IFG1_20_10        = 0x30000000,
525
526         TXMCS_TTHOLD_1_8        = 0x00000000,
527         TXMCS_TTHOLD_1_4        = 0x00000100,
528         TXMCS_TTHOLD_1_2        = 0x00000200,
529         TXMCS_TTHOLD_FULL       = 0x00000300,
530
531         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
532                                   TXMCS_IFG1_16_8 |
533                                   TXMCS_TTHOLD_FULL |
534                                   TXMCS_DEFER |
535                                   TXMCS_CRC |
536                                   TXMCS_PADDING,
537 };
538
539 enum jme_txpfc_bits_masks {
540         TXPFC_VLAN_TAG          = 0xFFFF0000,
541         TXPFC_VLAN_EN           = 0x00008000,
542         TXPFC_PF_EN             = 0x00000001,
543 };
544
545 enum jme_txtrhd_bits_masks {
546         TXTRHD_TXPEN            = 0x80000000,
547         TXTRHD_TXP              = 0x7FFFFF00,
548         TXTRHD_TXREN            = 0x00000080,
549         TXTRHD_TXRL             = 0x0000007F,
550 };
551 enum jme_txtrhd_shifts {
552         TXTRHD_TXP_SHIFT        = 8,
553         TXTRHD_TXRL_SHIFT       = 0,
554 };
555
556
557 /*
558  * RX Control/Status Bits
559  */
560 enum jme_rxcs_bit_masks {
561         /* FIFO full threshold for transmitting Tx Pause Packet */
562         RXCS_FIFOTHTP   = 0x30000000,
563         /* FIFO threshold for processing next packet */
564         RXCS_FIFOTHNP   = 0x0C000000,
565         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
566         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
567         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
568         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
569         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
570         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
571         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
572         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
573         RXCS_QST        = 0x00000004, /* Receive queue start */
574         RXCS_SUSPEND    = 0x00000002,
575         RXCS_ENABLE     = 0x00000001,
576 };
577 enum jme_rxcs_values {
578         RXCS_FIFOTHTP_16T       = 0x00000000,
579         RXCS_FIFOTHTP_32T       = 0x10000000,
580         RXCS_FIFOTHTP_64T       = 0x20000000,
581         RXCS_FIFOTHTP_128T      = 0x30000000,
582
583         RXCS_FIFOTHNP_16QW      = 0x00000000,
584         RXCS_FIFOTHNP_32QW      = 0x04000000,
585         RXCS_FIFOTHNP_64QW      = 0x08000000,
586         RXCS_FIFOTHNP_128QW     = 0x0C000000,
587
588         RXCS_DMAREQSZ_16B       = 0x00000000,
589         RXCS_DMAREQSZ_32B       = 0x01000000,
590         RXCS_DMAREQSZ_64B       = 0x02000000,
591         RXCS_DMAREQSZ_128B      = 0x03000000,
592
593         RXCS_QUEUESEL_Q0        = 0x00000000,
594         RXCS_QUEUESEL_Q1        = 0x00010000,
595         RXCS_QUEUESEL_Q2        = 0x00020000,
596         RXCS_QUEUESEL_Q3        = 0x00030000,
597
598         RXCS_RETRYGAP_256ns     = 0x00000000,
599         RXCS_RETRYGAP_512ns     = 0x00001000,
600         RXCS_RETRYGAP_1024ns    = 0x00002000,
601         RXCS_RETRYGAP_2048ns    = 0x00003000,
602         RXCS_RETRYGAP_4096ns    = 0x00004000,
603         RXCS_RETRYGAP_8192ns    = 0x00005000,
604         RXCS_RETRYGAP_16384ns   = 0x00006000,
605         RXCS_RETRYGAP_32768ns   = 0x00007000,
606
607         RXCS_RETRYCNT_0         = 0x00000000,
608         RXCS_RETRYCNT_4         = 0x00000100,
609         RXCS_RETRYCNT_8         = 0x00000200,
610         RXCS_RETRYCNT_12        = 0x00000300,
611         RXCS_RETRYCNT_16        = 0x00000400,
612         RXCS_RETRYCNT_20        = 0x00000500,
613         RXCS_RETRYCNT_24        = 0x00000600,
614         RXCS_RETRYCNT_28        = 0x00000700,
615         RXCS_RETRYCNT_32        = 0x00000800,
616         RXCS_RETRYCNT_36        = 0x00000900,
617         RXCS_RETRYCNT_40        = 0x00000A00,
618         RXCS_RETRYCNT_44        = 0x00000B00,
619         RXCS_RETRYCNT_48        = 0x00000C00,
620         RXCS_RETRYCNT_52        = 0x00000D00,
621         RXCS_RETRYCNT_56        = 0x00000E00,
622         RXCS_RETRYCNT_60        = 0x00000F00,
623
624         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
625                                   RXCS_FIFOTHNP_128QW |
626                                   RXCS_DMAREQSZ_128B |
627                                   RXCS_RETRYGAP_256ns |
628                                   RXCS_RETRYCNT_32,
629 };
630 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
631
632 /*
633  * RX MAC Control/Status Bits
634  */
635 enum jme_rxmcs_bits {
636         RXMCS_ALLFRAME          = 0x00000800,
637         RXMCS_BRDFRAME          = 0x00000400,
638         RXMCS_MULFRAME          = 0x00000200,
639         RXMCS_UNIFRAME          = 0x00000100,
640         RXMCS_ALLMULFRAME       = 0x00000080,
641         RXMCS_MULFILTERED       = 0x00000040,
642         RXMCS_RXCOLLDEC         = 0x00000020,
643         RXMCS_FLOWCTRL          = 0x00000008,
644         RXMCS_VTAGRM            = 0x00000004,
645         RXMCS_PREPAD            = 0x00000002,
646         RXMCS_CHECKSUM          = 0x00000001,
647         
648         RXMCS_DEFAULT           = RXMCS_VTAGRM |
649                                   RXMCS_PREPAD |
650                                   RXMCS_FLOWCTRL |
651                                   RXMCS_CHECKSUM,
652 };
653
654 /*
655  * SMI Related definitions
656  */
657 enum jme_smi_bit_mask
658 {
659         SMI_DATA_MASK           = 0xFFFF0000,
660         SMI_REG_ADDR_MASK       = 0x0000F800,
661         SMI_PHY_ADDR_MASK       = 0x000007C0,
662         SMI_OP_WRITE            = 0x00000020,
663         /* Set to 1, after req done it'll be cleared to 0 */
664         SMI_OP_REQ              = 0x00000010,
665         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
666         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
667         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
668         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
669 };
670 enum jme_smi_bit_shift
671 {
672         SMI_DATA_SHIFT          = 16,
673         SMI_REG_ADDR_SHIFT      = 11,
674         SMI_PHY_ADDR_SHIFT      = 6,
675 };
676 __always_inline __u32 smi_reg_addr(int x)
677 {
678         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
679 }
680 __always_inline __u32 smi_phy_addr(int x)
681 {
682         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
683 }
684 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
685
686 /*
687  * Global Host Control
688  */
689 enum jme_ghc_bit_mask {
690         GHC_SWRST       = 0x40000000,
691         GHC_DPX         = 0x00000040,
692         GHC_SPEED       = 0x00000030,
693         GHC_LINK_POLL   = 0x00000001,
694 };
695 enum jme_ghc_speed_val {
696         GHC_SPEED_10M   = 0x00000010,
697         GHC_SPEED_100M  = 0x00000020,
698         GHC_SPEED_1000M = 0x00000030,
699 };
700
701 /*
702  * Power management control and status register
703  */
704 enum jme_pmcs_bit_masks {
705         PMCS_WF7DET     = 0x80000000,
706         PMCS_WF6DET     = 0x40000000,
707         PMCS_WF5DET     = 0x20000000,
708         PMCS_WF4DET     = 0x10000000,
709         PMCS_WF3DET     = 0x08000000,
710         PMCS_WF2DET     = 0x04000000,
711         PMCS_WF1DET     = 0x02000000,
712         PMCS_WF0DET     = 0x01000000,
713         PMCS_LFDET      = 0x00040000,
714         PMCS_LRDET      = 0x00020000,
715         PMCS_MFDET      = 0x00010000,
716         PMCS_WF7EN      = 0x00008000,
717         PMCS_WF6EN      = 0x00004000,
718         PMCS_WF5EN      = 0x00002000,
719         PMCS_WF4EN      = 0x00001000,
720         PMCS_WF3EN      = 0x00000800,
721         PMCS_WF2EN      = 0x00000400,
722         PMCS_WF1EN      = 0x00000200,
723         PMCS_WF0EN      = 0x00000100,
724         PMCS_LFEN       = 0x00000004,
725         PMCS_LREN       = 0x00000002,
726         PMCS_MFEN       = 0x00000001,
727 };
728
729 /*
730  * Giga PHY Status Registers
731  */
732 enum jme_phy_link_bit_mask {
733         PHY_LINK_SPEED_MASK             = 0x0000C000,
734         PHY_LINK_DUPLEX                 = 0x00002000,
735         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
736         PHY_LINK_UP                     = 0x00000400,
737         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
738         PHY_LINK_MDI_STAT               = 0x00000040,
739 };
740 enum jme_phy_link_speed_val {
741         PHY_LINK_SPEED_10M              = 0x00000000,
742         PHY_LINK_SPEED_100M             = 0x00004000,
743         PHY_LINK_SPEED_1000M            = 0x00008000,
744 };
745 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
746
747 /*
748  * SMB Control and Status
749  */
750 enum jme_smbcsr_bit_mask {
751         SMBCSR_CNACK    = 0x00020000,
752         SMBCSR_RELOAD   = 0x00010000,
753         SMBCSR_EEPROMD  = 0x00000020,
754 };
755 #define JME_SMB_TIMEOUT 10 /* 10 msec */
756
757 /*
758  * Timer Control/Status Register
759  */
760 enum jme_tmcsr_bit_masks {
761         TMCSR_SWIT      = 0x80000000,
762         TMCSR_EN        = 0x01000000,
763         TMCSR_CNT       = 0x00FFFFFF,
764 };
765
766
767 /*
768  * General Purpost REG-0
769  */
770 enum jme_gpreg0_masks {
771         GPREG0_DISSH            = 0xFF000000,
772         GPREG0_PCIRLMT          = 0x00300000,
773         GPREG0_PCCNOMUTCLR      = 0x00040000,
774         GPREG0_PCCTMR           = 0x00000300,
775         GPREG0_PHYADDR          = 0x0000001F,
776 };
777 enum jme_gpreg0_vals {
778         GPREG0_DISSH_DW7        = 0x80000000,
779         GPREG0_DISSH_DW6        = 0x40000000,
780         GPREG0_DISSH_DW5        = 0x20000000,
781         GPREG0_DISSH_DW4        = 0x10000000,
782         GPREG0_DISSH_DW3        = 0x08000000,
783         GPREG0_DISSH_DW2        = 0x04000000,
784         GPREG0_DISSH_DW1        = 0x02000000,
785         GPREG0_DISSH_DW0        = 0x01000000,
786         GPREG0_DISSH_ALL        = 0xFF000000,
787
788         GPREG0_PCIRLMT_8        = 0x00000000,
789         GPREG0_PCIRLMT_6        = 0x00100000,
790         GPREG0_PCIRLMT_5        = 0x00200000,
791         GPREG0_PCIRLMT_4        = 0x00300000,
792
793         GPREG0_PCCTMR_16ns      = 0x00000000,
794         GPREG0_PCCTMR_256ns     = 0x00000100,
795         GPREG0_PCCTMR_1us       = 0x00000200,
796         GPREG0_PCCTMR_1ms       = 0x00000300,
797
798         GPREG0_PHYADDR_1        = 0x00000001,
799
800         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
801                                   GPREG0_PCCNOMUTCLR |
802                                   GPREG0_PCCTMR_1us |
803                                   GPREG0_PHYADDR_1,
804 };
805
806 /*
807  * Interrupt Status Bits
808  */
809 enum jme_interrupt_bits
810 {
811         INTR_SWINTR     = 0x80000000,
812         INTR_TMINTR     = 0x40000000,
813         INTR_LINKCH     = 0x20000000,
814         INTR_PAUSERCV   = 0x10000000,
815         INTR_MAGICRCV   = 0x08000000,
816         INTR_WAKERCV    = 0x04000000,
817         INTR_PCCRX0TO   = 0x02000000,
818         INTR_PCCRX1TO   = 0x01000000,
819         INTR_PCCRX2TO   = 0x00800000,
820         INTR_PCCRX3TO   = 0x00400000,
821         INTR_PCCTXTO    = 0x00200000,
822         INTR_PCCRX0     = 0x00100000,
823         INTR_PCCRX1     = 0x00080000,
824         INTR_PCCRX2     = 0x00040000,
825         INTR_PCCRX3     = 0x00020000,
826         INTR_PCCTX      = 0x00010000,
827         INTR_RX3EMP     = 0x00008000,
828         INTR_RX2EMP     = 0x00004000,
829         INTR_RX1EMP     = 0x00002000,
830         INTR_RX0EMP     = 0x00001000,
831         INTR_RX3        = 0x00000800,
832         INTR_RX2        = 0x00000400,
833         INTR_RX1        = 0x00000200,
834         INTR_RX0        = 0x00000100,
835         INTR_TX7        = 0x00000080,
836         INTR_TX6        = 0x00000040,
837         INTR_TX5        = 0x00000020,
838         INTR_TX4        = 0x00000010,
839         INTR_TX3        = 0x00000008,
840         INTR_TX2        = 0x00000004,
841         INTR_TX1        = 0x00000002,
842         INTR_TX0        = 0x00000001,
843 };
844 static const __u32 INTR_ENABLE = INTR_SWINTR |
845                                  INTR_TMINTR |
846                                  INTR_LINKCH |
847                                  INTR_RX0EMP |
848                                  INTR_PCCRX0TO |
849                                  INTR_PCCRX0 |
850                                  INTR_PCCTXTO |
851                                  INTR_PCCTX;
852
853 /*
854  * PCC Control Registers
855  */
856 enum jme_pccrx_masks {
857         PCCRXTO_MASK    = 0xFFFF0000,
858         PCCRX_MASK      = 0x0000FF00,
859 };
860 enum jme_pcctx_masks {
861         PCCTXTO_MASK    = 0xFFFF0000,
862         PCCTX_MASK      = 0x0000FF00,
863         PCCTX_QS_MASK   = 0x000000FF,
864 };
865 enum jme_pccrx_shifts {
866         PCCRXTO_SHIFT   = 16,
867         PCCRX_SHIFT     = 8,
868 };
869 enum jme_pcctx_shifts {
870         PCCTXTO_SHIFT   = 16,
871         PCCTX_SHIFT     = 8,
872 };
873 enum jme_pcctx_bits {
874         PCCTXQ0_EN      = 0x00000001,
875         PCCTXQ1_EN      = 0x00000002,
876         PCCTXQ2_EN      = 0x00000004,
877         PCCTXQ3_EN      = 0x00000008,
878         PCCTXQ4_EN      = 0x00000010,
879         PCCTXQ5_EN      = 0x00000020,
880         PCCTXQ6_EN      = 0x00000040,
881         PCCTXQ7_EN      = 0x00000080,
882 };
883
884
885 /*
886  * Shadow base address register bits
887  */
888 enum jme_shadow_base_address_bits {
889         SHBA_POSTEN     = 0x1,
890 };
891
892 /*
893  * Read/Write MMaped I/O Registers
894  */
895 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
896 {
897         return le32_to_cpu(readl((__u8*)jme->regs + reg));
898 }
899 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
900 {
901         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
902 }
903 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
904 {
905         /*
906          * Read after write should cause flush
907          */
908         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
909         readl((__u8*)jme->regs + reg);
910 }
911
912 /*
913  * Function prototypes for ethtool
914  */
915 static void jme_get_drvinfo(struct net_device *netdev,
916                              struct ethtool_drvinfo *info);
917 static int jme_get_settings(struct net_device *netdev,
918                              struct ethtool_cmd *ecmd);
919 static int jme_set_settings(struct net_device *netdev,
920                              struct ethtool_cmd *ecmd);
921 static u32 jme_get_link(struct net_device *netdev);
922
923
924 /*
925  * Function prototypes for netdev
926  */
927 static int jme_open(struct net_device *netdev);
928 static int jme_close(struct net_device *netdev);
929 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
930 static int jme_set_macaddr(struct net_device *netdev, void *p);
931 static void jme_set_multi(struct net_device *netdev);
932
933