2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #ifndef __JME_H_INCLUDED__
25 #define __JME_H_INCLUDED__
27 #define DRV_NAME "jme"
28 #define DRV_VERSION "1.0.4"
29 #define PFX DRV_NAME ": "
31 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
32 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35 * Message related definitions
37 #define JME_DEF_MSG_ENABLE \
44 #define jeprintk(pdev, fmt, args...) \
45 printk(KERN_ERR PFX fmt, ## args)
48 #define tx_dbg(priv, fmt, args...) \
49 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ## args)
51 #define tx_dbg(priv, fmt, args...)
54 #define jme_msg(msglvl, type, priv, fmt, args...) \
55 if (netif_msg_##type(priv)) \
56 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
58 #define msg_probe(priv, fmt, args...) \
59 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
61 #define msg_link(priv, fmt, args...) \
62 jme_msg(KERN_INFO, link, priv, fmt, ## args)
64 #define msg_intr(priv, fmt, args...) \
65 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
67 #define msg_rx_err(priv, fmt, args...) \
68 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
70 #define msg_rx_status(priv, fmt, args...) \
71 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
73 #define msg_tx_err(priv, fmt, args...) \
74 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
76 #define msg_tx_done(priv, fmt, args...) \
77 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
79 #define msg_tx_queued(priv, fmt, args...) \
80 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
82 #define msg_hw(priv, fmt, args...) \
83 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
86 * Extra PCI Configuration space interface
88 #define PCI_DCSR_MRRS 0x59
89 #define PCI_DCSR_MRRS_MASK 0x70
91 enum pci_dcsr_mrrs_vals {
113 __u8 wn; /* Number of write actions */
114 __u8 rn; /* Number of read actions */
115 __u8 bitn; /* Number of bits per action */
116 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
117 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
119 /* Internal use only */
123 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
126 enum jme_spi_op_bits {
127 SPI_MODE_CPHA = 0x01,
128 SPI_MODE_CPOL = 0x02,
132 #define HALF_US 500 /* 500 ns */
133 #define JMESPIIOCTL SIOCDEVPRIVATE
136 * Dynamic(adaptive)/Static PCC values
138 enum dynamic_pcc_values {
155 unsigned long last_bytes;
156 unsigned long last_pkts;
157 unsigned long intr_cnt;
159 unsigned char attempt;
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 1000
173 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
175 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
176 #define TX_DESC_SIZE 16
178 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
238 enum jme_txdesc_flags_bits {
249 #define TXDESC_MSS_SHIFT 2
250 enum jme_rxdescwb_flags_bits {
253 TXWBFLAG_TMOUT = 0x20,
254 TXWBFLAG_TRYOUT = 0x10,
257 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
262 #define RX_DESC_SIZE 16
264 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
265 #define RX_BUF_DMA_ALIGN 8
266 #define RX_PREPAD_SIZE 10
267 #define ETH_CRC_LEN 2
268 #define RX_VLANHDR_LEN 2
269 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
316 enum jme_rxdesc_flags_bits {
322 enum jme_rxwbdesc_flags_bits {
323 RXWBFLAG_OWN = 0x8000,
324 RXWBFLAG_INT = 0x4000,
325 RXWBFLAG_MF = 0x2000,
326 RXWBFLAG_64BIT = 0x2000,
327 RXWBFLAG_TCPON = 0x1000,
328 RXWBFLAG_UDPON = 0x0800,
329 RXWBFLAG_IPCS = 0x0400,
330 RXWBFLAG_TCPCS = 0x0200,
331 RXWBFLAG_UDPCS = 0x0100,
332 RXWBFLAG_TAGON = 0x0080,
333 RXWBFLAG_IPV4 = 0x0040,
334 RXWBFLAG_IPV6 = 0x0020,
335 RXWBFLAG_PAUSE = 0x0010,
336 RXWBFLAG_MAGIC = 0x0008,
337 RXWBFLAG_WAKEUP = 0x0004,
338 RXWBFLAG_DEST = 0x0003,
339 RXWBFLAG_DEST_UNI = 0x0001,
340 RXWBFLAG_DEST_MUL = 0x0002,
341 RXWBFLAG_DEST_BRO = 0x0003,
344 enum jme_rxwbdesc_desccnt_mask {
345 RXWBDCNT_WBCPL = 0x80,
346 RXWBDCNT_DCNT = 0x7F,
349 enum jme_rxwbdesc_errstat_bits {
350 RXWBERR_LIMIT = 0x80,
351 RXWBERR_MIIER = 0x40,
352 RXWBERR_NIBON = 0x20,
353 RXWBERR_COLON = 0x10,
354 RXWBERR_ABORT = 0x08,
355 RXWBERR_SHORT = 0x04,
356 RXWBERR_OVERUN = 0x02,
357 RXWBERR_CRCERR = 0x01,
358 RXWBERR_ALLERR = 0xFF,
362 * Buffer information corresponding to ring descriptors.
364 struct jme_buffer_info {
369 unsigned long start_xmit;
373 * The structure holding buffer information and ring descriptors all together.
375 #include <linux/version.h>
376 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
377 #define MAX_RING_DESC_NR 512
379 #define MAX_RING_DESC_NR 1024
383 void *alloc; /* pointer to allocated memory */
384 void *desc; /* pointer to ring memory */
385 dma_addr_t dmaalloc; /* phys address of ring alloc */
386 dma_addr_t dma; /* phys address for ring dma */
388 /* Buffer information corresponding to each descriptor */
389 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
392 atomic_t next_to_clean;
396 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
399 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
400 #define PCI_VENDOR_ID_JMICRON 0x197B
403 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
404 #define PCI_VDEVICE(vendor, device) \
405 PCI_VENDOR_ID_##vendor, (device), \
406 PCI_ANY_ID, PCI_ANY_ID, 0, 0
409 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
410 #define NET_STAT(priv) priv->stats
411 #define NETDEV_GET_STATS(netdev, fun_ptr) \
412 netdev->get_stats = fun_ptr
413 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
414 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
419 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
421 return skb->nh.ipv6h;
424 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
429 #define NET_STAT(priv) priv->dev->stats
430 #define NETDEV_GET_STATS(netdev, fun_ptr)
431 #define DECLARE_NET_DEVICE_STATS
434 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
435 #define DECLARE_NAPI_STRUCT
436 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
437 dev->poll = pollfn; \
439 #define JME_NAPI_HOLDER(holder) struct net_device *holder
440 #define JME_NAPI_WEIGHT(w) int *w
441 #define JME_NAPI_WEIGHT_VAL(w) *w
442 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
443 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
444 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
445 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
446 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
447 #define JME_RX_SCHEDULE_PREP(priv) \
448 netif_rx_schedule_prep(priv->dev)
449 #define JME_RX_SCHEDULE(priv) \
450 __netif_rx_schedule(priv->dev);
451 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,28)
452 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
453 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
454 netif_napi_add(dev, napis, pollfn, q);
455 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
456 #define JME_NAPI_WEIGHT(w) int w
457 #define JME_NAPI_WEIGHT_VAL(w) w
458 #define JME_NAPI_WEIGHT_SET(w, r)
459 #define DECLARE_NETDEV
460 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
461 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
462 #define JME_NAPI_DISABLE(priv) \
463 if (!napi_disable_pending(&priv->napi)) \
464 napi_disable(&priv->napi);
465 #define JME_RX_SCHEDULE_PREP(priv) \
466 napi_schedule_prep(&priv->napi)
467 #define JME_RX_SCHEDULE(priv) \
468 __napi_schedule(&priv->napi);
470 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
471 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
472 netif_napi_add(dev, napis, pollfn, q);
473 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
474 #define JME_NAPI_WEIGHT(w) int w
475 #define JME_NAPI_WEIGHT_VAL(w) w
476 #define JME_NAPI_WEIGHT_SET(w, r)
477 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
478 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
479 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
480 #define JME_NAPI_DISABLE(priv) \
481 if (!napi_disable_pending(&priv->napi)) \
482 napi_disable(&priv->napi);
483 #define JME_RX_SCHEDULE_PREP(priv) \
484 netif_rx_schedule_prep(priv->dev, &priv->napi)
485 #define JME_RX_SCHEDULE(priv) \
486 __netif_rx_schedule(priv->dev, &priv->napi);
490 * Jmac Adapter Private data
492 #define SHADOW_REG_NR 8
494 struct pci_dev *pdev;
495 struct net_device *dev;
497 dma_addr_t shadow_dma;
499 struct mii_if_info mii_if;
500 struct jme_ring rxring[RX_RING_NR];
501 struct jme_ring txring[TX_RING_NR];
503 spinlock_t macaddr_lock;
504 spinlock_t rxmcs_lock;
505 struct tasklet_struct rxempty_task;
506 struct tasklet_struct rxclean_task;
507 struct tasklet_struct txclean_task;
508 struct tasklet_struct linkch_task;
509 struct tasklet_struct pcc_task;
520 u32 tx_wake_threshold;
524 unsigned int fpgaver;
525 unsigned int chiprev;
528 struct ethtool_cmd old_ecmd;
529 unsigned int old_mtu;
530 struct vlan_group *vlgrp;
531 struct dynpcc_info dpi;
533 atomic_t link_changing;
534 atomic_t tx_cleaning;
535 atomic_t rx_cleaning;
537 int (*jme_rx)(struct sk_buff *skb);
538 int (*jme_vlan_rx)(struct sk_buff *skb,
539 struct vlan_group *grp,
540 unsigned short vlan_tag);
542 DECLARE_NET_DEVICE_STATS
545 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
546 static struct net_device_stats *
547 jme_get_stats(struct net_device *netdev)
549 struct jme_adapter *jme = netdev_priv(netdev);
554 enum shadow_reg_val {
558 enum jme_flags_bits {
564 JME_FLAG_SHUTDOWN = 6,
567 #define TX_TIMEOUT (5 * HZ)
568 #define JME_REG_LEN 0x500
569 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
571 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
572 static inline struct jme_adapter*
573 jme_napi_priv(struct net_device *holder)
575 struct jme_adapter *jme;
576 jme = netdev_priv(holder);
580 static inline struct jme_adapter*
581 jme_napi_priv(struct napi_struct *napi)
583 struct jme_adapter *jme;
584 jme = container_of(napi, struct jme_adapter, napi);
592 enum jme_iomap_offsets {
599 enum jme_iomap_lens {
606 enum jme_iomap_regs {
607 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
608 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
609 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
610 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
611 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
612 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
613 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
614 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
616 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
617 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
618 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
619 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
620 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
621 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
622 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
623 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
624 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
625 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
626 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
627 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
629 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
630 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
631 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
634 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
635 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
636 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
637 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
640 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
641 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
642 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
643 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
644 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
645 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
646 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
647 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
648 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
649 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
650 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
651 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
652 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
653 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
654 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
655 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
659 * TX Control/Status Bits
662 TXCS_QUEUE7S = 0x00008000,
663 TXCS_QUEUE6S = 0x00004000,
664 TXCS_QUEUE5S = 0x00002000,
665 TXCS_QUEUE4S = 0x00001000,
666 TXCS_QUEUE3S = 0x00000800,
667 TXCS_QUEUE2S = 0x00000400,
668 TXCS_QUEUE1S = 0x00000200,
669 TXCS_QUEUE0S = 0x00000100,
670 TXCS_FIFOTH = 0x000000C0,
671 TXCS_DMASIZE = 0x00000030,
672 TXCS_BURST = 0x00000004,
673 TXCS_ENABLE = 0x00000001,
676 enum jme_txcs_value {
677 TXCS_FIFOTH_16QW = 0x000000C0,
678 TXCS_FIFOTH_12QW = 0x00000080,
679 TXCS_FIFOTH_8QW = 0x00000040,
680 TXCS_FIFOTH_4QW = 0x00000000,
682 TXCS_DMASIZE_64B = 0x00000000,
683 TXCS_DMASIZE_128B = 0x00000010,
684 TXCS_DMASIZE_256B = 0x00000020,
685 TXCS_DMASIZE_512B = 0x00000030,
687 TXCS_SELECT_QUEUE0 = 0x00000000,
688 TXCS_SELECT_QUEUE1 = 0x00010000,
689 TXCS_SELECT_QUEUE2 = 0x00020000,
690 TXCS_SELECT_QUEUE3 = 0x00030000,
691 TXCS_SELECT_QUEUE4 = 0x00040000,
692 TXCS_SELECT_QUEUE5 = 0x00050000,
693 TXCS_SELECT_QUEUE6 = 0x00060000,
694 TXCS_SELECT_QUEUE7 = 0x00070000,
696 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
700 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
703 * TX MAC Control/Status Bits
705 enum jme_txmcs_bit_masks {
706 TXMCS_IFG2 = 0xC0000000,
707 TXMCS_IFG1 = 0x30000000,
708 TXMCS_TTHOLD = 0x00000300,
709 TXMCS_FBURST = 0x00000080,
710 TXMCS_CARRIEREXT = 0x00000040,
711 TXMCS_DEFER = 0x00000020,
712 TXMCS_BACKOFF = 0x00000010,
713 TXMCS_CARRIERSENSE = 0x00000008,
714 TXMCS_COLLISION = 0x00000004,
715 TXMCS_CRC = 0x00000002,
716 TXMCS_PADDING = 0x00000001,
719 enum jme_txmcs_values {
720 TXMCS_IFG2_6_4 = 0x00000000,
721 TXMCS_IFG2_8_5 = 0x40000000,
722 TXMCS_IFG2_10_6 = 0x80000000,
723 TXMCS_IFG2_12_7 = 0xC0000000,
725 TXMCS_IFG1_8_4 = 0x00000000,
726 TXMCS_IFG1_12_6 = 0x10000000,
727 TXMCS_IFG1_16_8 = 0x20000000,
728 TXMCS_IFG1_20_10 = 0x30000000,
730 TXMCS_TTHOLD_1_8 = 0x00000000,
731 TXMCS_TTHOLD_1_4 = 0x00000100,
732 TXMCS_TTHOLD_1_2 = 0x00000200,
733 TXMCS_TTHOLD_FULL = 0x00000300,
735 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
743 enum jme_txpfc_bits_masks {
744 TXPFC_VLAN_TAG = 0xFFFF0000,
745 TXPFC_VLAN_EN = 0x00008000,
746 TXPFC_PF_EN = 0x00000001,
749 enum jme_txtrhd_bits_masks {
750 TXTRHD_TXPEN = 0x80000000,
751 TXTRHD_TXP = 0x7FFFFF00,
752 TXTRHD_TXREN = 0x00000080,
753 TXTRHD_TXRL = 0x0000007F,
756 enum jme_txtrhd_shifts {
757 TXTRHD_TXP_SHIFT = 8,
758 TXTRHD_TXRL_SHIFT = 0,
762 * RX Control/Status Bits
764 enum jme_rxcs_bit_masks {
765 /* FIFO full threshold for transmitting Tx Pause Packet */
766 RXCS_FIFOTHTP = 0x30000000,
767 /* FIFO threshold for processing next packet */
768 RXCS_FIFOTHNP = 0x0C000000,
769 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
770 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
771 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
772 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
773 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
774 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
775 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
776 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
777 RXCS_QST = 0x00000004, /* Receive queue start */
778 RXCS_SUSPEND = 0x00000002,
779 RXCS_ENABLE = 0x00000001,
782 enum jme_rxcs_values {
783 RXCS_FIFOTHTP_16T = 0x00000000,
784 RXCS_FIFOTHTP_32T = 0x10000000,
785 RXCS_FIFOTHTP_64T = 0x20000000,
786 RXCS_FIFOTHTP_128T = 0x30000000,
788 RXCS_FIFOTHNP_16QW = 0x00000000,
789 RXCS_FIFOTHNP_32QW = 0x04000000,
790 RXCS_FIFOTHNP_64QW = 0x08000000,
791 RXCS_FIFOTHNP_128QW = 0x0C000000,
793 RXCS_DMAREQSZ_16B = 0x00000000,
794 RXCS_DMAREQSZ_32B = 0x01000000,
795 RXCS_DMAREQSZ_64B = 0x02000000,
796 RXCS_DMAREQSZ_128B = 0x03000000,
798 RXCS_QUEUESEL_Q0 = 0x00000000,
799 RXCS_QUEUESEL_Q1 = 0x00010000,
800 RXCS_QUEUESEL_Q2 = 0x00020000,
801 RXCS_QUEUESEL_Q3 = 0x00030000,
803 RXCS_RETRYGAP_256ns = 0x00000000,
804 RXCS_RETRYGAP_512ns = 0x00001000,
805 RXCS_RETRYGAP_1024ns = 0x00002000,
806 RXCS_RETRYGAP_2048ns = 0x00003000,
807 RXCS_RETRYGAP_4096ns = 0x00004000,
808 RXCS_RETRYGAP_8192ns = 0x00005000,
809 RXCS_RETRYGAP_16384ns = 0x00006000,
810 RXCS_RETRYGAP_32768ns = 0x00007000,
812 RXCS_RETRYCNT_0 = 0x00000000,
813 RXCS_RETRYCNT_4 = 0x00000100,
814 RXCS_RETRYCNT_8 = 0x00000200,
815 RXCS_RETRYCNT_12 = 0x00000300,
816 RXCS_RETRYCNT_16 = 0x00000400,
817 RXCS_RETRYCNT_20 = 0x00000500,
818 RXCS_RETRYCNT_24 = 0x00000600,
819 RXCS_RETRYCNT_28 = 0x00000700,
820 RXCS_RETRYCNT_32 = 0x00000800,
821 RXCS_RETRYCNT_36 = 0x00000900,
822 RXCS_RETRYCNT_40 = 0x00000A00,
823 RXCS_RETRYCNT_44 = 0x00000B00,
824 RXCS_RETRYCNT_48 = 0x00000C00,
825 RXCS_RETRYCNT_52 = 0x00000D00,
826 RXCS_RETRYCNT_56 = 0x00000E00,
827 RXCS_RETRYCNT_60 = 0x00000F00,
829 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
830 RXCS_FIFOTHNP_128QW |
832 RXCS_RETRYGAP_256ns |
836 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
839 * RX MAC Control/Status Bits
841 enum jme_rxmcs_bits {
842 RXMCS_ALLFRAME = 0x00000800,
843 RXMCS_BRDFRAME = 0x00000400,
844 RXMCS_MULFRAME = 0x00000200,
845 RXMCS_UNIFRAME = 0x00000100,
846 RXMCS_ALLMULFRAME = 0x00000080,
847 RXMCS_MULFILTERED = 0x00000040,
848 RXMCS_RXCOLLDEC = 0x00000020,
849 RXMCS_FLOWCTRL = 0x00000008,
850 RXMCS_VTAGRM = 0x00000004,
851 RXMCS_PREPAD = 0x00000002,
852 RXMCS_CHECKSUM = 0x00000001,
854 RXMCS_DEFAULT = RXMCS_VTAGRM |
861 * Wakeup Frame setup interface registers
863 #define WAKEUP_FRAME_NR 8
864 #define WAKEUP_FRAME_MASK_DWNR 4
866 enum jme_wfoi_bit_masks {
867 WFOI_MASK_SEL = 0x00000070,
868 WFOI_CRC_SEL = 0x00000008,
869 WFOI_FRAME_SEL = 0x00000007,
872 enum jme_wfoi_shifts {
877 * SMI Related definitions
879 enum jme_smi_bit_mask {
880 SMI_DATA_MASK = 0xFFFF0000,
881 SMI_REG_ADDR_MASK = 0x0000F800,
882 SMI_PHY_ADDR_MASK = 0x000007C0,
883 SMI_OP_WRITE = 0x00000020,
884 /* Set to 1, after req done it'll be cleared to 0 */
885 SMI_OP_REQ = 0x00000010,
886 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
887 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
888 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
889 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
892 enum jme_smi_bit_shift {
894 SMI_REG_ADDR_SHIFT = 11,
895 SMI_PHY_ADDR_SHIFT = 6,
898 static inline u32 smi_reg_addr(int x)
900 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
903 static inline u32 smi_phy_addr(int x)
905 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
908 #define JME_PHY_TIMEOUT 100 /* 100 msec */
909 #define JME_PHY_REG_NR 32
912 * Global Host Control
914 enum jme_ghc_bit_mask {
915 GHC_SWRST = 0x40000000,
916 GHC_DPX = 0x00000040,
917 GHC_SPEED = 0x00000030,
918 GHC_LINK_POLL = 0x00000001,
921 enum jme_ghc_speed_val {
922 GHC_SPEED_10M = 0x00000010,
923 GHC_SPEED_100M = 0x00000020,
924 GHC_SPEED_1000M = 0x00000030,
927 enum jme_ghc_to_clk {
928 GHC_TO_CLK_OFF = 0x00000000,
929 GHC_TO_CLK_GPHY = 0x00400000,
930 GHC_TO_CLK_PCIE = 0x00800000,
931 GHC_TO_CLK_INVALID = 0x00C00000,
934 enum jme_ghc_txmac_clk {
935 GHC_TXMAC_CLK_OFF = 0x00000000,
936 GHC_TXMAC_CLK_GPHY = 0x00100000,
937 GHC_TXMAC_CLK_PCIE = 0x00200000,
938 GHC_TXMAC_CLK_INVALID = 0x00300000,
942 * Power management control and status register
944 enum jme_pmcs_bit_masks {
945 PMCS_WF7DET = 0x80000000,
946 PMCS_WF6DET = 0x40000000,
947 PMCS_WF5DET = 0x20000000,
948 PMCS_WF4DET = 0x10000000,
949 PMCS_WF3DET = 0x08000000,
950 PMCS_WF2DET = 0x04000000,
951 PMCS_WF1DET = 0x02000000,
952 PMCS_WF0DET = 0x01000000,
953 PMCS_LFDET = 0x00040000,
954 PMCS_LRDET = 0x00020000,
955 PMCS_MFDET = 0x00010000,
956 PMCS_WF7EN = 0x00008000,
957 PMCS_WF6EN = 0x00004000,
958 PMCS_WF5EN = 0x00002000,
959 PMCS_WF4EN = 0x00001000,
960 PMCS_WF3EN = 0x00000800,
961 PMCS_WF2EN = 0x00000400,
962 PMCS_WF1EN = 0x00000200,
963 PMCS_WF0EN = 0x00000100,
964 PMCS_LFEN = 0x00000004,
965 PMCS_LREN = 0x00000002,
966 PMCS_MFEN = 0x00000001,
970 * Giga PHY Status Registers
972 enum jme_phy_link_bit_mask {
973 PHY_LINK_SPEED_MASK = 0x0000C000,
974 PHY_LINK_DUPLEX = 0x00002000,
975 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
976 PHY_LINK_UP = 0x00000400,
977 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
978 PHY_LINK_MDI_STAT = 0x00000040,
981 enum jme_phy_link_speed_val {
982 PHY_LINK_SPEED_10M = 0x00000000,
983 PHY_LINK_SPEED_100M = 0x00004000,
984 PHY_LINK_SPEED_1000M = 0x00008000,
987 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
990 * SMB Control and Status
992 enum jme_smbcsr_bit_mask {
993 SMBCSR_CNACK = 0x00020000,
994 SMBCSR_RELOAD = 0x00010000,
995 SMBCSR_EEPROMD = 0x00000020,
996 SMBCSR_INITDONE = 0x00000010,
997 SMBCSR_BUSY = 0x0000000F,
1000 enum jme_smbintf_bit_mask {
1001 SMBINTF_HWDATR = 0xFF000000,
1002 SMBINTF_HWDATW = 0x00FF0000,
1003 SMBINTF_HWADDR = 0x0000FF00,
1004 SMBINTF_HWRWN = 0x00000020,
1005 SMBINTF_HWCMD = 0x00000010,
1006 SMBINTF_FASTM = 0x00000008,
1007 SMBINTF_GPIOSCL = 0x00000004,
1008 SMBINTF_GPIOSDA = 0x00000002,
1009 SMBINTF_GPIOEN = 0x00000001,
1012 enum jme_smbintf_vals {
1013 SMBINTF_HWRWN_READ = 0x00000020,
1014 SMBINTF_HWRWN_WRITE = 0x00000000,
1017 enum jme_smbintf_shifts {
1018 SMBINTF_HWDATR_SHIFT = 24,
1019 SMBINTF_HWDATW_SHIFT = 16,
1020 SMBINTF_HWADDR_SHIFT = 8,
1023 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1024 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1025 #define JME_SMB_LEN 256
1026 #define JME_EEPROM_MAGIC 0x250
1029 * Timer Control/Status Register
1031 enum jme_tmcsr_bit_masks {
1032 TMCSR_SWIT = 0x80000000,
1033 TMCSR_EN = 0x01000000,
1034 TMCSR_CNT = 0x00FFFFFF,
1038 * General Purpose REG-0
1040 enum jme_gpreg0_masks {
1041 GPREG0_DISSH = 0xFF000000,
1042 GPREG0_PCIRLMT = 0x00300000,
1043 GPREG0_PCCNOMUTCLR = 0x00040000,
1044 GPREG0_LNKINTPOLL = 0x00001000,
1045 GPREG0_PCCTMR = 0x00000300,
1046 GPREG0_PHYADDR = 0x0000001F,
1049 enum jme_gpreg0_vals {
1050 GPREG0_DISSH_DW7 = 0x80000000,
1051 GPREG0_DISSH_DW6 = 0x40000000,
1052 GPREG0_DISSH_DW5 = 0x20000000,
1053 GPREG0_DISSH_DW4 = 0x10000000,
1054 GPREG0_DISSH_DW3 = 0x08000000,
1055 GPREG0_DISSH_DW2 = 0x04000000,
1056 GPREG0_DISSH_DW1 = 0x02000000,
1057 GPREG0_DISSH_DW0 = 0x01000000,
1058 GPREG0_DISSH_ALL = 0xFF000000,
1060 GPREG0_PCIRLMT_8 = 0x00000000,
1061 GPREG0_PCIRLMT_6 = 0x00100000,
1062 GPREG0_PCIRLMT_5 = 0x00200000,
1063 GPREG0_PCIRLMT_4 = 0x00300000,
1065 GPREG0_PCCTMR_16ns = 0x00000000,
1066 GPREG0_PCCTMR_256ns = 0x00000100,
1067 GPREG0_PCCTMR_1us = 0x00000200,
1068 GPREG0_PCCTMR_1ms = 0x00000300,
1070 GPREG0_PHYADDR_1 = 0x00000001,
1072 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1078 * General Purpose REG-1
1079 * Note: All theses bits defined here are for
1080 * Chip mode revision 0x11 only
1082 enum jme_gpreg1_masks {
1083 GPREG1_INTRDELAYUNIT = 0x00000018,
1084 GPREG1_INTRDELAYENABLE = 0x00000007,
1087 enum jme_gpreg1_vals {
1088 GPREG1_RSSPATCH = 0x00000040,
1089 GPREG1_HALFMODEPATCH = 0x00000020,
1091 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1092 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1093 GPREG1_INTDLYUNIT_1US = 0x00000010,
1094 GPREG1_INTDLYUNIT_16US = 0x00000018,
1096 GPREG1_INTDLYEN_1U = 0x00000001,
1097 GPREG1_INTDLYEN_2U = 0x00000002,
1098 GPREG1_INTDLYEN_3U = 0x00000003,
1099 GPREG1_INTDLYEN_4U = 0x00000004,
1100 GPREG1_INTDLYEN_5U = 0x00000005,
1101 GPREG1_INTDLYEN_6U = 0x00000006,
1102 GPREG1_INTDLYEN_7U = 0x00000007,
1104 GPREG1_DEFAULT = 0x00000000,
1108 * Interrupt Status Bits
1110 enum jme_interrupt_bits {
1111 INTR_SWINTR = 0x80000000,
1112 INTR_TMINTR = 0x40000000,
1113 INTR_LINKCH = 0x20000000,
1114 INTR_PAUSERCV = 0x10000000,
1115 INTR_MAGICRCV = 0x08000000,
1116 INTR_WAKERCV = 0x04000000,
1117 INTR_PCCRX0TO = 0x02000000,
1118 INTR_PCCRX1TO = 0x01000000,
1119 INTR_PCCRX2TO = 0x00800000,
1120 INTR_PCCRX3TO = 0x00400000,
1121 INTR_PCCTXTO = 0x00200000,
1122 INTR_PCCRX0 = 0x00100000,
1123 INTR_PCCRX1 = 0x00080000,
1124 INTR_PCCRX2 = 0x00040000,
1125 INTR_PCCRX3 = 0x00020000,
1126 INTR_PCCTX = 0x00010000,
1127 INTR_RX3EMP = 0x00008000,
1128 INTR_RX2EMP = 0x00004000,
1129 INTR_RX1EMP = 0x00002000,
1130 INTR_RX0EMP = 0x00001000,
1131 INTR_RX3 = 0x00000800,
1132 INTR_RX2 = 0x00000400,
1133 INTR_RX1 = 0x00000200,
1134 INTR_RX0 = 0x00000100,
1135 INTR_TX7 = 0x00000080,
1136 INTR_TX6 = 0x00000040,
1137 INTR_TX5 = 0x00000020,
1138 INTR_TX4 = 0x00000010,
1139 INTR_TX3 = 0x00000008,
1140 INTR_TX2 = 0x00000004,
1141 INTR_TX1 = 0x00000002,
1142 INTR_TX0 = 0x00000001,
1145 static const u32 INTR_ENABLE = INTR_SWINTR |
1155 * PCC Control Registers
1157 enum jme_pccrx_masks {
1158 PCCRXTO_MASK = 0xFFFF0000,
1159 PCCRX_MASK = 0x0000FF00,
1162 enum jme_pcctx_masks {
1163 PCCTXTO_MASK = 0xFFFF0000,
1164 PCCTX_MASK = 0x0000FF00,
1165 PCCTX_QS_MASK = 0x000000FF,
1168 enum jme_pccrx_shifts {
1173 enum jme_pcctx_shifts {
1178 enum jme_pcctx_bits {
1179 PCCTXQ0_EN = 0x00000001,
1180 PCCTXQ1_EN = 0x00000002,
1181 PCCTXQ2_EN = 0x00000004,
1182 PCCTXQ3_EN = 0x00000008,
1183 PCCTXQ4_EN = 0x00000010,
1184 PCCTXQ5_EN = 0x00000020,
1185 PCCTXQ6_EN = 0x00000040,
1186 PCCTXQ7_EN = 0x00000080,
1190 * Chip Mode Register
1192 enum jme_chipmode_bit_masks {
1193 CM_FPGAVER_MASK = 0xFFFF0000,
1194 CM_CHIPREV_MASK = 0x0000FF00,
1195 CM_CHIPMODE_MASK = 0x0000000F,
1198 enum jme_chipmode_shifts {
1199 CM_FPGAVER_SHIFT = 16,
1200 CM_CHIPREV_SHIFT = 8,
1204 * Shadow base address register bits
1206 enum jme_shadow_base_address_bits {
1211 * Aggressive Power Mode Control
1213 enum jme_apmc_bits {
1214 JME_APMC_PCIE_SD_EN = 0x40000000,
1215 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1216 JME_APMC_EPIEN = 0x04000000,
1217 JME_APMC_EPIEN_CTRL = 0x03000000,
1220 enum jme_apmc_values {
1221 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1222 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1225 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1228 static char *MAC_REG_NAME[] = {
1229 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1230 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1231 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1232 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1233 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1234 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1237 static char *PE_REG_NAME[] = {
1238 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1239 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1240 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1241 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1242 "JME_SMBCSR", "JME_SMBINTF"};
1244 static char *MISC_REG_NAME[] = {
1245 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1246 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1247 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1248 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1249 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1250 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1251 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1252 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1255 static inline void reg_dbg(const struct jme_adapter *jme,
1256 const char *msg, u32 val, u32 reg)
1258 const char *regname;
1259 switch (reg & 0xF00) {
1261 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1264 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1267 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1270 regname = PE_REG_NAME[0];
1272 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1276 static inline void reg_dbg(const struct jme_adapter *jme,
1277 const char *msg, u32 val, u32 reg) {}
1281 * Read/Write MMaped I/O Registers
1283 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1285 return readl(jme->regs + reg);
1288 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1290 reg_dbg(jme, "REG WRITE", val, reg);
1291 writel(val, jme->regs + reg);
1292 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1295 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1298 * Read after write should cause flush
1300 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1301 writel(val, jme->regs + reg);
1302 readl(jme->regs + reg);
1303 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1309 enum jme_phy_reg17_bit_masks {
1310 PREG17_SPEED = 0xC000,
1311 PREG17_DUPLEX = 0x2000,
1312 PREG17_SPDRSV = 0x0800,
1313 PREG17_LNKUP = 0x0400,
1314 PREG17_MDI = 0x0040,
1317 enum jme_phy_reg17_vals {
1318 PREG17_SPEED_10M = 0x0000,
1319 PREG17_SPEED_100M = 0x4000,
1320 PREG17_SPEED_1000M = 0x8000,
1323 #define BMSR_ANCOMP 0x0020
1328 static inline int is_buggy250(unsigned short device, unsigned int chiprev)
1330 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1334 * Function prototypes
1336 static int jme_set_settings(struct net_device *netdev,
1337 struct ethtool_cmd *ecmd);
1338 static void jme_set_multi(struct net_device *netdev);