jme.h

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #include <linux/version.h>
  25
  26 #define DRV_NAME        "jme"
  27 #define DRV_VERSION     "0.9"
  28 #define PFX DRV_NAME    ": "
  29
  30 #ifdef DEBUG
  31 #define dprintk(devname, fmt, args...) \
  32         printk(KERN_DEBUG "%s: " fmt, devname, ## args)
  33 #else
  34 #define dprintk(devname, fmt, args...)
  35 #endif
  36
  37 #ifdef TX_DEBUG
  38 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  39 #else
  40 #define tx_dbg(args...)
  41 #endif
  42
  43 #ifdef RX_DEBUG
  44 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  45 #else
  46 #define rx_dbg(args...)
  47 #endif
  48
  49 #ifdef QUEUE_DEBUG
  50 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  51 #else
  52 #define queue_dbg(args...)
  53 #endif
  54
  55 #ifdef CSUM_DEBUG
  56 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  57 #else
  58 #define csum_dbg(args...)
  59 #endif
  60
  61 #ifdef VLAN_DEBUG
  62 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
  63 #else
  64 #define vlan_dbg(args...)
  65 #endif
  66
  67 #define jprintk(devname, fmt, args...) \
  68         printk(KERN_INFO "%s: " fmt, devname, ## args)
  69
  70 #define jeprintk(devname, fmt, args...) \
  71         printk(KERN_ERR "%s: " fmt, devname, ## args)
  72
  73 #define DEFAULT_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_RX_ERR       | \
  79          NETIF_MSG_TX_ERR)
  80
  81 #define PCI_CONF_DCSR_MRRS      0x59
  82 #define PCI_CONF_DCSR_MRRS_MASK 0x70
  83 enum pci_conf_dcsr_mrrs_vals {
  84         MRRS_128B       = 0x00,
  85         MRRS_256B       = 0x10,
  86         MRRS_512B       = 0x20,
  87         MRRS_1024B      = 0x30,
  88         MRRS_2048B      = 0x40,
  89         MRRS_4096B      = 0x50,
  90 };
  91
  92 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
  93 #define MIN_ETHERNET_PACKET_SIZE 60
  94
  95 enum dynamic_pcc_values {
  96         PCC_P1          = 1,
  97         PCC_P2          = 2,
  98         PCC_P3          = 3,
  99
 100         PCC_P1_TO       = 1,
 101         PCC_P2_TO       = 250,
 102         PCC_P3_TO       = 1000,
 103
 104         PCC_P1_CNT      = 1,
 105         PCC_P2_CNT      = 64,
 106         PCC_P3_CNT      = 255,
 107 };
 108 struct dynpcc_info {
 109         unsigned long   last_bytes;
 110         unsigned long   last_pkts;
 111         unsigned long   intr_cnt;
 112         unsigned char   cur;
 113         unsigned char   attempt;
 114         unsigned char   cnt;
 115 };
 116 #define PCC_INTERVAL_US 100000
 117 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
 118 #define PCC_P3_THRESHOLD 3*1024*1024
 119 #define PCC_P2_THRESHOLD 800
 120 #define PCC_INTR_THRESHOLD 800
 121 #define PCC_TX_TO 333
 122 #define PCC_TX_CNT 8
 123
 124 /*
 125  * TX/RX Descriptors
 126  *
 127  * TX/RX Ring DESC Count Must be multiple of 16
 128  * RX Ring DESC Count Must be <= 1024
 129  */
 130 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
 131
 132 #define TX_DESC_SIZE            16
 133 #define TX_RING_NR              8
 134 #define TX_RING_ALLOC_SIZE(s)   (s * TX_DESC_SIZE) + RING_DESC_ALIGN
 135
 136 struct txdesc {
 137         union {
 138                 __u8  all[16];
 139                 __u32 dw[4];
 140                 struct {
 141                         /* DW0 */
 142                         __u16 vlan;
 143                         __u8 rsv1;
 144                         __u8 flags;
 145
 146                         /* DW1 */
 147                         __u16 datalen;
 148                         __u16 mss;
 149
 150                         /* DW2 */
 151                         __u16 pktsize;
 152                         __u16 rsv2;
 153
 154                         /* DW3 */
 155                         __u32 bufaddr;
 156                 } desc1;
 157                 struct {
 158                         /* DW0 */
 159                         __u16 rsv1;
 160                         __u8 rsv2;
 161                         __u8 flags;
 162
 163                         /* DW1 */
 164                         __u16 datalen;
 165                         __u16 rsv3;
 166
 167                         /* DW2 */
 168                         __u32 bufaddrh;
 169
 170                         /* DW3 */
 171                         __u32 bufaddrl;
 172                 } desc2;
 173                 struct {
 174                         /* DW0 */
 175                         __u8 ehdrsz;
 176                         __u8 rsv1;
 177                         __u8 rsv2;
 178                         __u8 flags;
 179
 180                         /* DW1 */
 181                         __u16 trycnt;
 182                         __u16 segcnt;
 183
 184                         /* DW2 */
 185                         __u16 pktsz;
 186                         __u16 rsv3;
 187
 188                         /* DW3 */
 189                         __u32 bufaddrl;
 190                 } descwb;
 191         };
 192 };
 193 enum jme_txdesc_flags_bits {
 194         TXFLAG_OWN      = 0x80,
 195         TXFLAG_INT      = 0x40,
 196         TXFLAG_64BIT    = 0x20,
 197         TXFLAG_TCPCS    = 0x10,
 198         TXFLAG_UDPCS    = 0x08,
 199         TXFLAG_IPCS     = 0x04,
 200         TXFLAG_LSEN     = 0x02,
 201         TXFLAG_TAGON    = 0x01,
 202 };
 203 #define TXDESC_MSS_SHIFT        2
 204 enum jme_rxdescwb_flags_bits {
 205         TXWBFLAG_OWN    = 0x80,
 206         TXWBFLAG_INT    = 0x40,
 207         TXWBFLAG_TMOUT  = 0x20,
 208         TXWBFLAG_TRYOUT = 0x10,
 209         TXWBFLAG_COL    = 0x08,
 210
 211         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
 212                           TXWBFLAG_TRYOUT |
 213                           TXWBFLAG_COL,
 214 };
 215
 216
 217 #define RX_DESC_SIZE            16
 218 #define RX_RING_NR              4
 219 #define RX_RING_ALLOC_SIZE(s)   (s * RX_DESC_SIZE) + RING_DESC_ALIGN
 220
 221 #define RX_BUF_DMA_ALIGN        8
 222 #define RX_PREPAD_SIZE          10
 223 #define ETH_CRC_LEN             2
 224 #define RX_VLANHDR_LEN          2
 225 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
 226                                 ETH_HLEN + \
 227                                 ETH_CRC_LEN + \
 228                                 RX_VLANHDR_LEN + \
 229                                 RX_BUF_DMA_ALIGN)
 230
 231 struct rxdesc {
 232         union {
 233                 __u8   all[16];
 234                 __le32 dw[4];
 235                 struct {
 236                         /* DW0 */
 237                         __le16 rsv2;
 238                         __u8 rsv1;
 239                         __u8 flags;
 240
 241                         /* DW1 */
 242                         __le16 datalen;
 243                         __le16 wbcpl;
 244
 245                         /* DW2 */
 246                         __le32 bufaddrh;
 247
 248                         /* DW3 */
 249                         __le32 bufaddrl;
 250                 } desc1;
 251                 struct {
 252                         /* DW0 */
 253                         __le16 vlan;
 254                         __le16 flags;
 255
 256                         /* DW1 */
 257                         __le16 framesize;
 258                         __u8 errstat;
 259                         __u8 desccnt;
 260
 261                         /* DW2 */
 262                         __le32 rsshash;
 263
 264                         /* DW3 */
 265                         __u8   hashfun;
 266                         __u8   hashtype;
 267                         __le16 resrv;
 268                 } descwb;
 269         };
 270 };
 271 enum jme_rxdesc_flags_bits {
 272         RXFLAG_OWN      = 0x80,
 273         RXFLAG_INT      = 0x40,
 274         RXFLAG_64BIT    = 0x20,
 275 };
 276 enum jme_rxwbdesc_flags_bits {
 277         RXWBFLAG_OWN            = 0x8000,
 278         RXWBFLAG_INT            = 0x4000,
 279         RXWBFLAG_MF             = 0x2000,
 280         RXWBFLAG_64BIT          = 0x2000,
 281         RXWBFLAG_TCPON          = 0x1000,
 282         RXWBFLAG_UDPON          = 0x0800,
 283         RXWBFLAG_IPCS           = 0x0400,
 284         RXWBFLAG_TCPCS          = 0x0200,
 285         RXWBFLAG_UDPCS          = 0x0100,
 286         RXWBFLAG_TAGON          = 0x0080,
 287         RXWBFLAG_IPV4           = 0x0040,
 288         RXWBFLAG_IPV6           = 0x0020,
 289         RXWBFLAG_PAUSE          = 0x0010,
 290         RXWBFLAG_MAGIC          = 0x0008,
 291         RXWBFLAG_WAKEUP         = 0x0004,
 292         RXWBFLAG_DEST           = 0x0003,
 293         RXWBFLAG_DEST_UNI       = 0x0001,
 294         RXWBFLAG_DEST_MUL       = 0x0002,
 295         RXWBFLAG_DEST_BRO       = 0x0003,
 296 };
 297 enum jme_rxwbdesc_desccnt_mask {
 298         RXWBDCNT_WBCPL  = 0x80,
 299         RXWBDCNT_DCNT   = 0x7F,
 300 };
 301 enum jme_rxwbdesc_errstat_bits {
 302         RXWBERR_LIMIT   = 0x80,
 303         RXWBERR_MIIER   = 0x40,
 304         RXWBERR_NIBON   = 0x20,
 305         RXWBERR_COLON   = 0x10,
 306         RXWBERR_ABORT   = 0x08,
 307         RXWBERR_SHORT   = 0x04,
 308         RXWBERR_OVERUN  = 0x02,
 309         RXWBERR_CRCERR  = 0x01,
 310         RXWBERR_ALLERR  = 0xFF,
 311 };
 312
 313 struct jme_buffer_info {
 314         struct sk_buff *skb;
 315         dma_addr_t mapping;
 316         int len;
 317         int nr_desc;
 318 };
 319
 320 #define MAX_RING_DESC_NR        1024
 321 struct jme_ring {
 322         void* alloc;            /* pointer to allocated memory */
 323         volatile void* desc;    /* pointer to ring memory  */
 324         dma_addr_t dmaalloc;    /* phys address of ring alloc */
 325         dma_addr_t dma;         /* phys address for ring dma */
 326
 327         /* Buffer information corresponding to each descriptor */
 328         struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
 329
 330         int next_to_use;
 331         int next_to_clean;
 332
 333         atomic_t nr_free;
 334 };
 335
 336 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
 337 #define NET_STAT(priv) priv->stats
 338 #define NETDEV_GET_STATS(netdev, fun_ptr) \
 339         netdev->get_stats = fun_ptr
 340 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
 341 #else
 342 #define NET_STAT(priv) priv->dev->stats
 343 #define NETDEV_GET_STATS(netdev, fun_ptr)
 344 #define DECLARE_NET_DEVICE_STATS
 345 #endif
 346
 347 /*
 348  * Jmac Adapter Private data
 349  */
 350 #define SHADOW_REG_NR 8
 351 struct jme_adapter {
 352         struct pci_dev          *pdev;
 353         struct net_device       *dev;
 354         void __iomem            *regs;
 355         dma_addr_t              shadow_dma;
 356         __u32                   *shadow_regs;
 357         struct mii_if_info      mii_if;
 358         struct jme_ring         rxring[RX_RING_NR];
 359         struct jme_ring         txring[TX_RING_NR];
 360         spinlock_t              phy_lock;
 361         spinlock_t              macaddr_lock;
 362         spinlock_t              rxmcs_lock;
 363         struct tasklet_struct   rxempty_task;
 364         struct tasklet_struct   rxclean_task;
 365         struct tasklet_struct   txclean_task;
 366         struct tasklet_struct   linkch_task;
 367         struct tasklet_struct   pcc_task;
 368         __u32                   flags;
 369         __u32                   reg_txcs;
 370         __u32                   reg_txpfc;
 371         __u32                   reg_rxcs;
 372         __u32                   reg_rxmcs;
 373         __u32                   reg_ghc;
 374         __u32                   reg_pmcs;
 375         __u32                   phylink;
 376         __u32                   tx_ring_size;
 377         __u32                   tx_ring_mask;
 378         __u32                   tx_wake_threshold;
 379         __u32                   rx_ring_size;
 380         __u32                   rx_ring_mask;
 381         __u8                    mrrs;
 382         struct ethtool_cmd      old_ecmd;
 383         unsigned int            old_mtu;
 384         struct vlan_group*      vlgrp;
 385         struct dynpcc_info      dpi;
 386         atomic_t                intr_sem;
 387         atomic_t                link_changing;
 388         atomic_t                tx_cleaning;
 389         atomic_t                rx_cleaning;
 390         DECLARE_NET_DEVICE_STATS
 391 };
 392 enum shadow_reg_val {
 393         SHADOW_IEVE = 0,
 394 };
 395 enum jme_flags_bits {
 396         JME_FLAG_MSI            = 0x00000001,
 397         JME_FLAG_SSET           = 0x00000002,
 398         JME_FLAG_TXCSUM         = 0x00000004,
 399         JME_FLAG_TSO            = 0x00000008,
 400 };
 401 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
 402 #define TX_TIMEOUT              (5*HZ)
 403
 404
 405 /*
 406  * MMaped I/O Resters
 407  */
 408 enum jme_iomap_offsets {
 409         JME_MAC         = 0x0000,
 410         JME_PHY         = 0x0400,
 411         JME_MISC        = 0x0800,
 412         JME_RSS         = 0x0C00,
 413 };
 414
 415 enum jme_iomap_lens {
 416         JME_MAC_LEN     = 0x80,
 417         JME_PHY_LEN     = 0x58,
 418         JME_MISC_LEN    = 0x98,
 419         JME_RSS_LEN     = 0xFF,
 420 };
 421
 422 enum jme_iomap_regs {
 423         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
 424         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
 425         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
 426         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
 427         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
 428         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
 429         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
 430         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
 431
 432         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
 433         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
 434         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
 435         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
 436         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
 437         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
 438         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
 439         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
 440         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
 441         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
 442         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
 443         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
 444
 445         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
 446         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
 447         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
 448
 449
 450         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
 451         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
 452         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
 453
 454
 455         JME_TMCSR       = JME_MISC| 0x00, /* Timer Control/Status Register */
 456         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
 457         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
 458         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
 459         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
 460         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
 461         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
 462         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
 463         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
 464         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
 465         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
 466         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
 467 };
 468
 469 /*
 470  * TX Control/Status Bits
 471  */
 472 enum jme_txcs_bits {
 473         TXCS_QUEUE7S    = 0x00008000,
 474         TXCS_QUEUE6S    = 0x00004000,
 475         TXCS_QUEUE5S    = 0x00002000,
 476         TXCS_QUEUE4S    = 0x00001000,
 477         TXCS_QUEUE3S    = 0x00000800,
 478         TXCS_QUEUE2S    = 0x00000400,
 479         TXCS_QUEUE1S    = 0x00000200,
 480         TXCS_QUEUE0S    = 0x00000100,
 481         TXCS_FIFOTH     = 0x000000C0,
 482         TXCS_DMASIZE    = 0x00000030,
 483         TXCS_BURST      = 0x00000004,
 484         TXCS_ENABLE     = 0x00000001,
 485 };
 486 enum jme_txcs_value {
 487         TXCS_FIFOTH_16QW        = 0x000000C0,
 488         TXCS_FIFOTH_12QW        = 0x00000080,
 489         TXCS_FIFOTH_8QW         = 0x00000040,
 490         TXCS_FIFOTH_4QW         = 0x00000000,
 491
 492         TXCS_DMASIZE_64B        = 0x00000000,
 493         TXCS_DMASIZE_128B       = 0x00000010,
 494         TXCS_DMASIZE_256B       = 0x00000020,
 495         TXCS_DMASIZE_512B       = 0x00000030,
 496
 497         TXCS_SELECT_QUEUE0      = 0x00000000,
 498         TXCS_SELECT_QUEUE1      = 0x00010000,
 499         TXCS_SELECT_QUEUE2      = 0x00020000,
 500         TXCS_SELECT_QUEUE3      = 0x00030000,
 501         TXCS_SELECT_QUEUE4      = 0x00040000,
 502         TXCS_SELECT_QUEUE5      = 0x00050000,
 503         TXCS_SELECT_QUEUE6      = 0x00060000,
 504         TXCS_SELECT_QUEUE7      = 0x00070000,
 505
 506         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
 507                                   TXCS_BURST,
 508 };
 509 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
 510
 511 /*
 512  * TX MAC Control/Status Bits
 513  */
 514 enum jme_txmcs_bit_masks {
 515         TXMCS_IFG2              = 0xC0000000,
 516         TXMCS_IFG1              = 0x30000000,
 517         TXMCS_TTHOLD            = 0x00000300,
 518         TXMCS_FBURST            = 0x00000080,
 519         TXMCS_CARRIEREXT        = 0x00000040,
 520         TXMCS_DEFER             = 0x00000020,
 521         TXMCS_BACKOFF           = 0x00000010,
 522         TXMCS_CARRIERSENSE      = 0x00000008,
 523         TXMCS_COLLISION         = 0x00000004,
 524         TXMCS_CRC               = 0x00000002,
 525         TXMCS_PADDING           = 0x00000001,
 526 };
 527 enum jme_txmcs_values {
 528         TXMCS_IFG2_6_4          = 0x00000000,
 529         TXMCS_IFG2_8_5          = 0x40000000,
 530         TXMCS_IFG2_10_6         = 0x80000000,
 531         TXMCS_IFG2_12_7         = 0xC0000000,
 532
 533         TXMCS_IFG1_8_4          = 0x00000000,
 534         TXMCS_IFG1_12_6         = 0x10000000,
 535         TXMCS_IFG1_16_8         = 0x20000000,
 536         TXMCS_IFG1_20_10        = 0x30000000,
 537
 538         TXMCS_TTHOLD_1_8        = 0x00000000,
 539         TXMCS_TTHOLD_1_4        = 0x00000100,
 540         TXMCS_TTHOLD_1_2        = 0x00000200,
 541         TXMCS_TTHOLD_FULL       = 0x00000300,
 542
 543         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
 544                                   TXMCS_IFG1_16_8 |
 545                                   TXMCS_TTHOLD_FULL |
 546                                   TXMCS_DEFER |
 547                                   TXMCS_CRC |
 548                                   TXMCS_PADDING,
 549 };
 550
 551 enum jme_txpfc_bits_masks {
 552         TXPFC_VLAN_TAG          = 0xFFFF0000,
 553         TXPFC_VLAN_EN           = 0x00008000,
 554         TXPFC_PF_EN             = 0x00000001,
 555 };
 556
 557 enum jme_txtrhd_bits_masks {
 558         TXTRHD_TXPEN            = 0x80000000,
 559         TXTRHD_TXP              = 0x7FFFFF00,
 560         TXTRHD_TXREN            = 0x00000080,
 561         TXTRHD_TXRL             = 0x0000007F,
 562 };
 563 enum jme_txtrhd_shifts {
 564         TXTRHD_TXP_SHIFT        = 8,
 565         TXTRHD_TXRL_SHIFT       = 0,
 566 };
 567
 568
 569 /*
 570  * RX Control/Status Bits
 571  */
 572 enum jme_rxcs_bit_masks {
 573         /* FIFO full threshold for transmitting Tx Pause Packet */
 574         RXCS_FIFOTHTP   = 0x30000000,
 575         /* FIFO threshold for processing next packet */
 576         RXCS_FIFOTHNP   = 0x0C000000,
 577         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
 578         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
 579         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
 580         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
 581         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
 582         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
 583         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
 584         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
 585         RXCS_QST        = 0x00000004, /* Receive queue start */
 586         RXCS_SUSPEND    = 0x00000002,
 587         RXCS_ENABLE     = 0x00000001,
 588 };
 589 enum jme_rxcs_values {
 590         RXCS_FIFOTHTP_16T       = 0x00000000,
 591         RXCS_FIFOTHTP_32T       = 0x10000000,
 592         RXCS_FIFOTHTP_64T       = 0x20000000,
 593         RXCS_FIFOTHTP_128T      = 0x30000000,
 594
 595         RXCS_FIFOTHNP_16QW      = 0x00000000,
 596         RXCS_FIFOTHNP_32QW      = 0x04000000,
 597         RXCS_FIFOTHNP_64QW      = 0x08000000,
 598         RXCS_FIFOTHNP_128QW     = 0x0C000000,
 599
 600         RXCS_DMAREQSZ_16B       = 0x00000000,
 601         RXCS_DMAREQSZ_32B       = 0x01000000,
 602         RXCS_DMAREQSZ_64B       = 0x02000000,
 603         RXCS_DMAREQSZ_128B      = 0x03000000,
 604
 605         RXCS_QUEUESEL_Q0        = 0x00000000,
 606         RXCS_QUEUESEL_Q1        = 0x00010000,
 607         RXCS_QUEUESEL_Q2        = 0x00020000,
 608         RXCS_QUEUESEL_Q3        = 0x00030000,
 609
 610         RXCS_RETRYGAP_256ns     = 0x00000000,
 611         RXCS_RETRYGAP_512ns     = 0x00001000,
 612         RXCS_RETRYGAP_1024ns    = 0x00002000,
 613         RXCS_RETRYGAP_2048ns    = 0x00003000,
 614         RXCS_RETRYGAP_4096ns    = 0x00004000,
 615         RXCS_RETRYGAP_8192ns    = 0x00005000,
 616         RXCS_RETRYGAP_16384ns   = 0x00006000,
 617         RXCS_RETRYGAP_32768ns   = 0x00007000,
 618
 619         RXCS_RETRYCNT_0         = 0x00000000,
 620         RXCS_RETRYCNT_4         = 0x00000100,
 621         RXCS_RETRYCNT_8         = 0x00000200,
 622         RXCS_RETRYCNT_12        = 0x00000300,
 623         RXCS_RETRYCNT_16        = 0x00000400,
 624         RXCS_RETRYCNT_20        = 0x00000500,
 625         RXCS_RETRYCNT_24        = 0x00000600,
 626         RXCS_RETRYCNT_28        = 0x00000700,
 627         RXCS_RETRYCNT_32        = 0x00000800,
 628         RXCS_RETRYCNT_36        = 0x00000900,
 629         RXCS_RETRYCNT_40        = 0x00000A00,
 630         RXCS_RETRYCNT_44        = 0x00000B00,
 631         RXCS_RETRYCNT_48        = 0x00000C00,
 632         RXCS_RETRYCNT_52        = 0x00000D00,
 633         RXCS_RETRYCNT_56        = 0x00000E00,
 634         RXCS_RETRYCNT_60        = 0x00000F00,
 635
 636         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
 637                                   RXCS_FIFOTHNP_128QW |
 638                                   RXCS_DMAREQSZ_128B |
 639                                   RXCS_RETRYGAP_256ns |
 640                                   RXCS_RETRYCNT_32,
 641 };
 642 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
 643
 644 /*
 645  * RX MAC Control/Status Bits
 646  */
 647 enum jme_rxmcs_bits {
 648         RXMCS_ALLFRAME          = 0x00000800,
 649         RXMCS_BRDFRAME          = 0x00000400,
 650         RXMCS_MULFRAME          = 0x00000200,
 651         RXMCS_UNIFRAME          = 0x00000100,
 652         RXMCS_ALLMULFRAME       = 0x00000080,
 653         RXMCS_MULFILTERED       = 0x00000040,
 654         RXMCS_RXCOLLDEC         = 0x00000020,
 655         RXMCS_FLOWCTRL          = 0x00000008,
 656         RXMCS_VTAGRM            = 0x00000004,
 657         RXMCS_PREPAD            = 0x00000002,
 658         RXMCS_CHECKSUM          = 0x00000001,
 659
 660         RXMCS_DEFAULT           = RXMCS_VTAGRM |
 661                                   RXMCS_PREPAD |
 662                                   RXMCS_FLOWCTRL |
 663                                   RXMCS_CHECKSUM,
 664 };
 665
 666 /*
 667  * Wakeup Frame setup interface registers
 668  */
 669 #define WAKEUP_FRAME_NR 8
 670 #define WAKEUP_FRAME_MASK_DWNR  4
 671 enum jme_wfoi_bit_masks {
 672         WFOI_MASK_SEL           = 0x00000070,
 673         WFOI_CRC_SEL            = 0x00000008,
 674         WFOI_FRAME_SEL          = 0x00000007,
 675 };
 676 enum jme_wfoi_shifts {
 677         WFOI_MASK_SHIFT         = 4,
 678 };
 679
 680 /*
 681  * SMI Related definitions
 682  */
 683 enum jme_smi_bit_mask
 684 {
 685         SMI_DATA_MASK           = 0xFFFF0000,
 686         SMI_REG_ADDR_MASK       = 0x0000F800,
 687         SMI_PHY_ADDR_MASK       = 0x000007C0,
 688         SMI_OP_WRITE            = 0x00000020,
 689         /* Set to 1, after req done it'll be cleared to 0 */
 690         SMI_OP_REQ              = 0x00000010,
 691         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
 692         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
 693         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
 694         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
 695 };
 696 enum jme_smi_bit_shift
 697 {
 698         SMI_DATA_SHIFT          = 16,
 699         SMI_REG_ADDR_SHIFT      = 11,
 700         SMI_PHY_ADDR_SHIFT      = 6,
 701 };
 702 __always_inline __u32 smi_reg_addr(int x)
 703 {
 704         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
 705 }
 706 __always_inline __u32 smi_phy_addr(int x)
 707 {
 708         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
 709 }
 710 #define JME_PHY_TIMEOUT 1000 /* 1000 usec */
 711
 712 /*
 713  * Global Host Control
 714  */
 715 enum jme_ghc_bit_mask {
 716         GHC_SWRST       = 0x40000000,
 717         GHC_DPX         = 0x00000040,
 718         GHC_SPEED       = 0x00000030,
 719         GHC_LINK_POLL   = 0x00000001,
 720 };
 721 enum jme_ghc_speed_val {
 722         GHC_SPEED_10M   = 0x00000010,
 723         GHC_SPEED_100M  = 0x00000020,
 724         GHC_SPEED_1000M = 0x00000030,
 725 };
 726
 727 /*
 728  * Power management control and status register
 729  */
 730 enum jme_pmcs_bit_masks {
 731         PMCS_WF7DET     = 0x80000000,
 732         PMCS_WF6DET     = 0x40000000,
 733         PMCS_WF5DET     = 0x20000000,
 734         PMCS_WF4DET     = 0x10000000,
 735         PMCS_WF3DET     = 0x08000000,
 736         PMCS_WF2DET     = 0x04000000,
 737         PMCS_WF1DET     = 0x02000000,
 738         PMCS_WF0DET     = 0x01000000,
 739         PMCS_LFDET      = 0x00040000,
 740         PMCS_LRDET      = 0x00020000,
 741         PMCS_MFDET      = 0x00010000,
 742         PMCS_WF7EN      = 0x00008000,
 743         PMCS_WF6EN      = 0x00004000,
 744         PMCS_WF5EN      = 0x00002000,
 745         PMCS_WF4EN      = 0x00001000,
 746         PMCS_WF3EN      = 0x00000800,
 747         PMCS_WF2EN      = 0x00000400,
 748         PMCS_WF1EN      = 0x00000200,
 749         PMCS_WF0EN      = 0x00000100,
 750         PMCS_LFEN       = 0x00000004,
 751         PMCS_LREN       = 0x00000002,
 752         PMCS_MFEN       = 0x00000001,
 753 };
 754
 755 /*
 756  * Giga PHY Status Registers
 757  */
 758 enum jme_phy_link_bit_mask {
 759         PHY_LINK_SPEED_MASK             = 0x0000C000,
 760         PHY_LINK_DUPLEX                 = 0x00002000,
 761         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
 762         PHY_LINK_UP                     = 0x00000400,
 763         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
 764         PHY_LINK_MDI_STAT               = 0x00000040,
 765 };
 766 enum jme_phy_link_speed_val {
 767         PHY_LINK_SPEED_10M              = 0x00000000,
 768         PHY_LINK_SPEED_100M             = 0x00004000,
 769         PHY_LINK_SPEED_1000M            = 0x00008000,
 770 };
 771 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
 772
 773 /*
 774  * SMB Control and Status
 775  */
 776 enum jme_smbcsr_bit_mask {
 777         SMBCSR_CNACK    = 0x00020000,
 778         SMBCSR_RELOAD   = 0x00010000,
 779         SMBCSR_EEPROMD  = 0x00000020,
 780 };
 781 #define JME_SMB_TIMEOUT 10 /* 10 msec */
 782
 783 /*
 784  * Timer Control/Status Register
 785  */
 786 enum jme_tmcsr_bit_masks {
 787         TMCSR_SWIT      = 0x80000000,
 788         TMCSR_EN        = 0x01000000,
 789         TMCSR_CNT       = 0x00FFFFFF,
 790 };
 791
 792
 793 /*
 794  * General Purpost REG-0
 795  */
 796 enum jme_gpreg0_masks {
 797         GPREG0_DISSH            = 0xFF000000,
 798         GPREG0_PCIRLMT          = 0x00300000,
 799         GPREG0_PCCNOMUTCLR      = 0x00040000,
 800         GPREG0_PCCTMR           = 0x00000300,
 801         GPREG0_PHYADDR          = 0x0000001F,
 802 };
 803 enum jme_gpreg0_vals {
 804         GPREG0_DISSH_DW7        = 0x80000000,
 805         GPREG0_DISSH_DW6        = 0x40000000,
 806         GPREG0_DISSH_DW5        = 0x20000000,
 807         GPREG0_DISSH_DW4        = 0x10000000,
 808         GPREG0_DISSH_DW3        = 0x08000000,
 809         GPREG0_DISSH_DW2        = 0x04000000,
 810         GPREG0_DISSH_DW1        = 0x02000000,
 811         GPREG0_DISSH_DW0        = 0x01000000,
 812         GPREG0_DISSH_ALL        = 0xFF000000,
 813
 814         GPREG0_PCIRLMT_8        = 0x00000000,
 815         GPREG0_PCIRLMT_6        = 0x00100000,
 816         GPREG0_PCIRLMT_5        = 0x00200000,
 817         GPREG0_PCIRLMT_4        = 0x00300000,
 818
 819         GPREG0_PCCTMR_16ns      = 0x00000000,
 820         GPREG0_PCCTMR_256ns     = 0x00000100,
 821         GPREG0_PCCTMR_1us       = 0x00000200,
 822         GPREG0_PCCTMR_1ms       = 0x00000300,
 823
 824         GPREG0_PHYADDR_1        = 0x00000001,
 825
 826         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
 827                                   GPREG0_PCCNOMUTCLR |
 828                                   GPREG0_PCCTMR_1us |
 829                                   GPREG0_PHYADDR_1,
 830 };
 831
 832 /*
 833  * Interrupt Status Bits
 834  */
 835 enum jme_interrupt_bits
 836 {
 837         INTR_SWINTR     = 0x80000000,
 838         INTR_TMINTR     = 0x40000000,
 839         INTR_LINKCH     = 0x20000000,
 840         INTR_PAUSERCV   = 0x10000000,
 841         INTR_MAGICRCV   = 0x08000000,
 842         INTR_WAKERCV    = 0x04000000,
 843         INTR_PCCRX0TO   = 0x02000000,
 844         INTR_PCCRX1TO   = 0x01000000,
 845         INTR_PCCRX2TO   = 0x00800000,
 846         INTR_PCCRX3TO   = 0x00400000,
 847         INTR_PCCTXTO    = 0x00200000,
 848         INTR_PCCRX0     = 0x00100000,
 849         INTR_PCCRX1     = 0x00080000,
 850         INTR_PCCRX2     = 0x00040000,
 851         INTR_PCCRX3     = 0x00020000,
 852         INTR_PCCTX      = 0x00010000,
 853         INTR_RX3EMP     = 0x00008000,
 854         INTR_RX2EMP     = 0x00004000,
 855         INTR_RX1EMP     = 0x00002000,
 856         INTR_RX0EMP     = 0x00001000,
 857         INTR_RX3        = 0x00000800,
 858         INTR_RX2        = 0x00000400,
 859         INTR_RX1        = 0x00000200,
 860         INTR_RX0        = 0x00000100,
 861         INTR_TX7        = 0x00000080,
 862         INTR_TX6        = 0x00000040,
 863         INTR_TX5        = 0x00000020,
 864         INTR_TX4        = 0x00000010,
 865         INTR_TX3        = 0x00000008,
 866         INTR_TX2        = 0x00000004,
 867         INTR_TX1        = 0x00000002,
 868         INTR_TX0        = 0x00000001,
 869 };
 870 static const __u32 INTR_ENABLE = INTR_SWINTR |
 871                                  INTR_TMINTR |
 872                                  INTR_LINKCH |
 873                                  INTR_RX0EMP |
 874                                  INTR_PCCRX0TO |
 875                                  INTR_PCCRX0 |
 876                                  INTR_PCCTXTO |
 877                                  INTR_PCCTX;
 878
 879 /*
 880  * PCC Control Registers
 881  */
 882 enum jme_pccrx_masks {
 883         PCCRXTO_MASK    = 0xFFFF0000,
 884         PCCRX_MASK      = 0x0000FF00,
 885 };
 886 enum jme_pcctx_masks {
 887         PCCTXTO_MASK    = 0xFFFF0000,
 888         PCCTX_MASK      = 0x0000FF00,
 889         PCCTX_QS_MASK   = 0x000000FF,
 890 };
 891 enum jme_pccrx_shifts {
 892         PCCRXTO_SHIFT   = 16,
 893         PCCRX_SHIFT     = 8,
 894 };
 895 enum jme_pcctx_shifts {
 896         PCCTXTO_SHIFT   = 16,
 897         PCCTX_SHIFT     = 8,
 898 };
 899 enum jme_pcctx_bits {
 900         PCCTXQ0_EN      = 0x00000001,
 901         PCCTXQ1_EN      = 0x00000002,
 902         PCCTXQ2_EN      = 0x00000004,
 903         PCCTXQ3_EN      = 0x00000008,
 904         PCCTXQ4_EN      = 0x00000010,
 905         PCCTXQ5_EN      = 0x00000020,
 906         PCCTXQ6_EN      = 0x00000040,
 907         PCCTXQ7_EN      = 0x00000080,
 908 };
 909
 910
 911 /*
 912  * Shadow base address register bits
 913  */
 914 enum jme_shadow_base_address_bits {
 915         SHBA_POSTEN     = 0x1,
 916 };
 917
 918 /*
 919  * Read/Write MMaped I/O Registers
 920  */
 921 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
 922 {
 923         return le32_to_cpu(readl((__u8*)jme->regs + reg));
 924 }
 925 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
 926 {
 927         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
 928 }
 929 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
 930 {
 931         /*
 932          * Read after write should cause flush
 933          */
 934         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
 935         readl((__u8*)jme->regs + reg);
 936 }
 937
 938 /*
 939  * Function prototypes for ethtool
 940  */
 941 static void jme_get_drvinfo(struct net_device *netdev,
 942                              struct ethtool_drvinfo *info);
 943 static int jme_get_settings(struct net_device *netdev,
 944                              struct ethtool_cmd *ecmd);
 945 static int jme_set_settings(struct net_device *netdev,
 946                              struct ethtool_cmd *ecmd);
 947 static u32 jme_get_link(struct net_device *netdev);
 948
 949
 950 /*
 951  * Function prototypes for netdev
 952  */
 953 static int jme_open(struct net_device *netdev);
 954 static int jme_close(struct net_device *netdev);
 955 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
 956 static int jme_set_macaddr(struct net_device *netdev, void *p);
 957 static void jme_set_multi(struct net_device *netdev);
 958
 959