Import jme 0.9d-msix source
[jme.git] / jme.h
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  *
7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  *
22  */
23
24 #include <linux/version.h>
25
26 #define DRV_NAME        "jme"
27 #define DRV_VERSION     "0.9d-msix"
28 #define PFX DRV_NAME    ": "
29
30 #define JME_GE_DEVICE 0x250
31 #define JME_FE_DEVICE 0x260
32
33 #ifdef DEBUG
34 #define dprintk(devname, fmt, args...) \
35         printk(KERN_DEBUG "%s: " fmt, devname, ## args)
36 #else
37 #define dprintk(devname, fmt, args...)
38 #endif
39
40 #ifdef TX_DEBUG
41 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
42 #else
43 #define tx_dbg(args...)
44 #endif
45
46 #ifdef RX_DEBUG
47 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
48 #else
49 #define rx_dbg(args...)
50 #endif
51
52 #ifdef QUEUE_DEBUG
53 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
54 #else
55 #define queue_dbg(args...)
56 #endif
57
58 #ifdef CSUM_DEBUG
59 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
60 #else
61 #define csum_dbg(args...)
62 #endif
63
64 #ifdef VLAN_DEBUG
65 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
66 #else
67 #define vlan_dbg(args...)
68 #endif
69
70 #define jprintk(devname, fmt, args...) \
71         printk(KERN_INFO "%s: " fmt, devname, ## args)
72
73 #define jeprintk(devname, fmt, args...) \
74         printk(KERN_ERR "%s: " fmt, devname, ## args)
75
76 #define PCI_CONF_DCSR_MRRS      0x59
77 #define PCI_CONF_DCSR_MRRS_MASK 0x70
78 enum pci_conf_dcsr_mrrs_vals {
79         MRRS_128B       = 0x00,
80         MRRS_256B       = 0x10,
81         MRRS_512B       = 0x20,
82         MRRS_1024B      = 0x30,
83         MRRS_2048B      = 0x40,
84         MRRS_4096B      = 0x50,
85 };
86
87 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
88 #define MIN_ETHERNET_PACKET_SIZE 60
89
90
91 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
92 #define NET_STAT(priv) priv->stats
93 #define NETDEV_GET_STATS(netdev, fun_ptr) \
94         netdev->get_stats = fun_ptr
95 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
96 #else
97 #define NET_STAT(priv) priv->dev->stats
98 #define NETDEV_GET_STATS(netdev, fun_ptr)
99 #define DECLARE_NET_DEVICE_STATS
100 #endif
101
102 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
103 #define DECLARE_NAPI_STRUCT
104 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
105         dev->poll = pollfn; \
106         dev->weight = q;
107 #define JME_NAPI_HOLDER(holder) struct net_device *holder
108 #define JME_NAPI_WEIGHT(w) int *w
109 #define JME_NAPI_WEIGHT_VAL(w) *w
110 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
111 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
112 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
113 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
114 #define JME_RX_SCHEDULE_PREP(priv) \
115         netif_rx_schedule_prep(priv->dev)
116 #define JME_RX_SCHEDULE(priv) \
117         __netif_rx_schedule(priv->dev);
118 #else
119 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
120 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
121         netif_napi_add(dev, napis, pollfn, q);
122 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
123 #define JME_NAPI_WEIGHT(w) int w
124 #define JME_NAPI_WEIGHT_VAL(w) w
125 #define JME_NAPI_WEIGHT_SET(w, r)
126 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
127 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
128 #define JME_NAPI_DISABLE(priv) \
129         if(!napi_disable_pending(&priv->napi)) \
130                 napi_disable(&priv->napi);
131 #define JME_RX_SCHEDULE_PREP(priv) \
132         netif_rx_schedule_prep(priv->dev, &priv->napi)
133 #define JME_RX_SCHEDULE(priv) \
134         __netif_rx_schedule(priv->dev, &priv->napi);
135 #endif
136
137
138 enum dynamic_pcc_values {
139         PCC_OFF         = 0,
140         PCC_P1          = 1,
141         PCC_P2          = 2,
142         PCC_P3          = 3,
143
144         PCC_OFF_TO      = 0,
145         PCC_P1_TO       = 1,
146         PCC_P2_TO       = 64,
147         PCC_P3_TO       = 128,
148
149         PCC_OFF_CNT     = 0,
150         PCC_P1_CNT      = 1,
151         PCC_P2_CNT      = 16,
152         PCC_P3_CNT      = 32,
153 };
154 struct dynpcc_info {
155         unsigned long   last_bytes;
156         unsigned long   last_pkts;
157         unsigned long   intr_cnt;
158         unsigned char   cur;
159         unsigned char   attempt;
160         unsigned char   cnt;
161 };
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD 2*1024*1024
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 333
168 #define PCC_TX_CNT 8
169
170 /*
171  * TX/RX Descriptors
172  *
173  * TX/RX Ring DESC Count Must be multiple of 16
174  * RX Ring DESC Count Must be <= 1024
175  */
176 #define RING_DESC_ALIGN         16      /* Descriptor alignment */
177
178 #define TX_DESC_SIZE            16
179 #define TX_RING_NR              8
180 #define TX_RING_ALLOC_SIZE(s)   (s * TX_DESC_SIZE) + RING_DESC_ALIGN
181
182 struct txdesc {
183         union {
184                 __u8  all[16];
185                 __u32 dw[4];
186                 struct {
187                         /* DW0 */
188                         __u16 vlan;
189                         __u8 rsv1;
190                         __u8 flags;
191
192                         /* DW1 */
193                         __u16 datalen;
194                         __u16 mss;
195
196                         /* DW2 */
197                         __u16 pktsize;
198                         __u16 rsv2;
199
200                         /* DW3 */
201                         __u32 bufaddr;
202                 } desc1;
203                 struct {
204                         /* DW0 */
205                         __u16 rsv1;
206                         __u8 rsv2;
207                         __u8 flags;
208
209                         /* DW1 */
210                         __u16 datalen;
211                         __u16 rsv3;
212
213                         /* DW2 */
214                         __u32 bufaddrh;
215
216                         /* DW3 */
217                         __u32 bufaddrl;
218                 } desc2;
219                 struct {
220                         /* DW0 */
221                         __u8 ehdrsz;
222                         __u8 rsv1;
223                         __u8 rsv2;
224                         __u8 flags;
225
226                         /* DW1 */
227                         __u16 trycnt;
228                         __u16 segcnt;
229
230                         /* DW2 */
231                         __u16 pktsz;
232                         __u16 rsv3;
233
234                         /* DW3 */
235                         __u32 bufaddrl;
236                 } descwb;
237         };
238 };
239 enum jme_txdesc_flags_bits {
240         TXFLAG_OWN      = 0x80,
241         TXFLAG_INT      = 0x40,
242         TXFLAG_64BIT    = 0x20,
243         TXFLAG_TCPCS    = 0x10,
244         TXFLAG_UDPCS    = 0x08,
245         TXFLAG_IPCS     = 0x04,
246         TXFLAG_LSEN     = 0x02,
247         TXFLAG_TAGON    = 0x01,
248 };
249 #define TXDESC_MSS_SHIFT        2
250 enum jme_rxdescwb_flags_bits {
251         TXWBFLAG_OWN    = 0x80,
252         TXWBFLAG_INT    = 0x40,
253         TXWBFLAG_TMOUT  = 0x20,
254         TXWBFLAG_TRYOUT = 0x10,
255         TXWBFLAG_COL    = 0x08,
256
257         TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
258                           TXWBFLAG_TRYOUT |
259                           TXWBFLAG_COL,
260 };
261
262
263 #define RX_DESC_SIZE            16
264 #define RX_RING_NR              4
265 #define RX_RING_ALLOC_SIZE(s)   (s * RX_DESC_SIZE) + RING_DESC_ALIGN
266
267 #define RX_BUF_DMA_ALIGN        8
268 #define RX_PREPAD_SIZE          10
269 #define ETH_CRC_LEN             2
270 #define RX_VLANHDR_LEN          2
271 #define RX_EXTRA_LEN            (RX_PREPAD_SIZE + \
272                                 ETH_HLEN + \
273                                 ETH_CRC_LEN + \
274                                 RX_VLANHDR_LEN + \
275                                 RX_BUF_DMA_ALIGN)
276
277 struct rxdesc {
278         union {
279                 __u8   all[16];
280                 __le32 dw[4];
281                 struct {
282                         /* DW0 */
283                         __le16 rsv2;
284                         __u8 rsv1;
285                         __u8 flags;
286
287                         /* DW1 */
288                         __le16 datalen;
289                         __le16 wbcpl;
290
291                         /* DW2 */
292                         __le32 bufaddrh;
293
294                         /* DW3 */
295                         __le32 bufaddrl;
296                 } desc1;
297                 struct {
298                         /* DW0 */
299                         __le16 vlan;
300                         __le16 flags;
301
302                         /* DW1 */
303                         __le16 framesize;
304                         __u8 errstat;
305                         __u8 desccnt;
306
307                         /* DW2 */
308                         __le32 rsshash;
309
310                         /* DW3 */
311                         __u8   hashfun;
312                         __u8   hashtype;
313                         __le16 resrv;
314                 } descwb;
315         };
316 };
317 enum jme_rxdesc_flags_bits {
318         RXFLAG_OWN      = 0x80,
319         RXFLAG_INT      = 0x40,
320         RXFLAG_64BIT    = 0x20,
321 };
322 enum jme_rxwbdesc_flags_bits {
323         RXWBFLAG_OWN            = 0x8000,
324         RXWBFLAG_INT            = 0x4000,
325         RXWBFLAG_MF             = 0x2000,
326         RXWBFLAG_64BIT          = 0x2000,
327         RXWBFLAG_TCPON          = 0x1000,
328         RXWBFLAG_UDPON          = 0x0800,
329         RXWBFLAG_IPCS           = 0x0400,
330         RXWBFLAG_TCPCS          = 0x0200,
331         RXWBFLAG_UDPCS          = 0x0100,
332         RXWBFLAG_TAGON          = 0x0080,
333         RXWBFLAG_IPV4           = 0x0040,
334         RXWBFLAG_IPV6           = 0x0020,
335         RXWBFLAG_PAUSE          = 0x0010,
336         RXWBFLAG_MAGIC          = 0x0008,
337         RXWBFLAG_WAKEUP         = 0x0004,
338         RXWBFLAG_DEST           = 0x0003,
339         RXWBFLAG_DEST_UNI       = 0x0001,
340         RXWBFLAG_DEST_MUL       = 0x0002,
341         RXWBFLAG_DEST_BRO       = 0x0003,
342 };
343 enum jme_rxwbdesc_desccnt_mask {
344         RXWBDCNT_WBCPL  = 0x80,
345         RXWBDCNT_DCNT   = 0x7F,
346 };
347 enum jme_rxwbdesc_errstat_bits {
348         RXWBERR_LIMIT   = 0x80,
349         RXWBERR_MIIER   = 0x40,
350         RXWBERR_NIBON   = 0x20,
351         RXWBERR_COLON   = 0x10,
352         RXWBERR_ABORT   = 0x08,
353         RXWBERR_SHORT   = 0x04,
354         RXWBERR_OVERUN  = 0x02,
355         RXWBERR_CRCERR  = 0x01,
356         RXWBERR_ALLERR  = 0xFF,
357 };
358
359 struct jme_buffer_info {
360         struct sk_buff *skb;
361         dma_addr_t mapping;
362         int len;
363         int nr_desc;
364         unsigned long start_xmit;
365 };
366
367 #define MAX_RING_DESC_NR        1024
368 struct jme_ring {
369         void* alloc;            /* pointer to allocated memory */
370         volatile void* desc;    /* pointer to ring memory  */
371         dma_addr_t dmaalloc;    /* phys address of ring alloc */
372         dma_addr_t dma;         /* phys address for ring dma */
373
374         /* Buffer information corresponding to each descriptor */
375         struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
376
377         int next_to_use;
378         atomic_t next_to_clean;
379         atomic_t nr_free;
380 };
381
382 #define JME_MSIX_VEC_NR         3
383 struct jme_msix_info {
384         irq_handler_t   handler;
385         __u16           vector;
386         __u8            requested;
387         char            name[16];
388 };
389
390 /*
391  * Jmac Adapter Private data
392  */
393 #define SHADOW_REG_NR 8
394 struct jme_adapter {
395         struct pci_dev          *pdev;
396         struct net_device       *dev;
397         void __iomem            *regs;
398         dma_addr_t              shadow_dma;
399         __u32                   *shadow_regs;
400         struct mii_if_info      mii_if;
401         struct jme_ring         rxring[RX_RING_NR];
402         struct jme_ring         txring[TX_RING_NR];
403         spinlock_t              phy_lock;
404         spinlock_t              macaddr_lock;
405         spinlock_t              rxmcs_lock;
406         struct tasklet_struct   rxempty_task;
407         struct tasklet_struct   rxclean_task;
408         struct tasklet_struct   txclean_task;
409         struct tasklet_struct   linkch_task;
410         struct tasklet_struct   pcc_task;
411         struct jme_msix_info    msix[JME_MSIX_VEC_NR];
412         __u32                   flags;
413         __u32                   reg_txcs;
414         __u32                   reg_txpfc;
415         __u32                   reg_rxcs;
416         __u32                   reg_rxmcs;
417         __u32                   reg_ghc;
418         __u32                   reg_pmcs;
419         __u32                   phylink;
420         __u32                   tx_ring_size;
421         __u32                   tx_ring_mask;
422         __u32                   tx_wake_threshold;
423         __u32                   rx_ring_size;
424         __u32                   rx_ring_mask;
425         __u8                    mrrs;
426         __u32                   fpgaver;
427         __u32                   chipver;
428         struct ethtool_cmd      old_ecmd;
429         unsigned int            old_mtu;
430         struct vlan_group*      vlgrp;
431         struct dynpcc_info      dpi;
432         atomic_t                intr_sem;
433         atomic_t                link_changing;
434         atomic_t                tx_cleaning;
435         atomic_t                rx_cleaning;
436         atomic_t                rx_empty;
437         int                     (*jme_rx)(struct sk_buff *skb);
438         int                     (*jme_vlan_rx)(struct sk_buff *skb,
439                                           struct vlan_group *grp,
440                                           unsigned short vlan_tag);
441         DECLARE_NAPI_STRUCT
442         DECLARE_NET_DEVICE_STATS
443 };
444 enum shadow_reg_val {
445         SHADOW_IEVE = 0,
446 };
447 enum jme_flags_bits {
448         JME_FLAG_MSI            = 0x00000001,
449         JME_FLAG_MSIX           = 0x00000002,
450         JME_FLAG_SSET           = 0x00000004,
451         JME_FLAG_TXCSUM         = 0x00000008,
452         JME_FLAG_TSO            = 0x00000010,
453         JME_FLAG_POLL           = 0x00000020,
454 };
455 #define WAIT_TASKLET_TIMEOUT    500 /* 500 ms */
456 #define TX_TIMEOUT              (5*HZ)
457 #define JME_REG_LEN             0x500
458
459 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
460 __always_inline static struct jme_adapter*
461 jme_napi_priv(struct net_device *holder)
462 {
463         struct jme_adapter* jme;
464         jme = netdev_priv(holder);
465         return jme;
466 }
467 #else
468 __always_inline static struct jme_adapter*
469 jme_napi_priv(struct napi_struct *napi)
470 {
471         struct jme_adapter* jme;
472         jme = container_of(napi, struct jme_adapter, napi);
473         return jme;
474 }
475 #endif
476
477 /*
478  * MMaped I/O Resters
479  */
480 enum jme_iomap_offsets {
481         JME_MAC         = 0x0000,
482         JME_PHY         = 0x0400,
483         JME_MISC        = 0x0800,
484         JME_RSS         = 0x0C00,
485 };
486
487 enum jme_iomap_lens {
488         JME_MAC_LEN     = 0x80,
489         JME_PHY_LEN     = 0x58,
490         JME_MISC_LEN    = 0x98,
491         JME_RSS_LEN     = 0xFF,
492 };
493
494 enum jme_iomap_regs {
495         JME_TXCS        = JME_MAC | 0x00, /* Transmit Control and Status */
496         JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
497         JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
498         JME_TXQDC       = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
499         JME_TXNDA       = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
500         JME_TXMCS       = JME_MAC | 0x14, /* Transmit MAC Control Status */
501         JME_TXPFC       = JME_MAC | 0x18, /* Transmit Pause Frame Control */
502         JME_TXTRHD      = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
503
504         JME_RXCS        = JME_MAC | 0x20, /* Receive Control and Status */
505         JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
506         JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
507         JME_RXQDC       = JME_MAC | 0x2C, /* Receive Queue Desc Count */
508         JME_RXNDA       = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
509         JME_RXMCS       = JME_MAC | 0x34, /* Receive MAC Control Status */
510         JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
511         JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
512         JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
513         JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
514         JME_WFODP       = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
515         JME_WFOI        = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
516
517         JME_SMI         = JME_MAC | 0x50, /* Station Management Interface */
518         JME_GHC         = JME_MAC | 0x54, /* Global Host Control */
519         JME_PMCS        = JME_MAC | 0x60, /* Power Management Control/Stat */
520
521
522         JME_PHY_CS      = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
523         JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
524         JME_SMBCSR      = JME_PHY | 0x40, /* SMB Control and Status */
525         JME_SMBINTF     = JME_PHY | 0x44, /* SMB Interface */
526
527
528         JME_TMCSR       = JME_MISC| 0x00, /* Timer Control/Status Register */
529         JME_GPREG0      = JME_MISC| 0x08, /* General purpose REG-0 */
530         JME_GPREG1      = JME_MISC| 0x0C, /* General purpose REG-1 */
531         JME_MSIX_ENT    = JME_MISC| 0x10, /* MSIX Entry table */
532         JME_IEVE        = JME_MISC| 0x20, /* Interrupt Event Status */
533         JME_IREQ        = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
534         JME_IENS        = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
535         JME_IENC        = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
536         JME_PCCRX0      = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
537         JME_PCCTX       = JME_MISC| 0x40, /* PCC Control for TX Queues */
538         JME_CHIPMODE    = JME_MISC| 0x44, /* Identify FPGA Version */
539         JME_SHBA_HI     = JME_MISC| 0x48, /* Shadow Register Base HI */
540         JME_SHBA_LO     = JME_MISC| 0x4C, /* Shadow Register Base LO */
541         JME_PCCSRX0     = JME_MISC| 0x80, /* PCC Status of RX0 */
542 };
543
544 /*
545  * TX Control/Status Bits
546  */
547 enum jme_txcs_bits {
548         TXCS_QUEUE7S    = 0x00008000,
549         TXCS_QUEUE6S    = 0x00004000,
550         TXCS_QUEUE5S    = 0x00002000,
551         TXCS_QUEUE4S    = 0x00001000,
552         TXCS_QUEUE3S    = 0x00000800,
553         TXCS_QUEUE2S    = 0x00000400,
554         TXCS_QUEUE1S    = 0x00000200,
555         TXCS_QUEUE0S    = 0x00000100,
556         TXCS_FIFOTH     = 0x000000C0,
557         TXCS_DMASIZE    = 0x00000030,
558         TXCS_BURST      = 0x00000004,
559         TXCS_ENABLE     = 0x00000001,
560 };
561 enum jme_txcs_value {
562         TXCS_FIFOTH_16QW        = 0x000000C0,
563         TXCS_FIFOTH_12QW        = 0x00000080,
564         TXCS_FIFOTH_8QW         = 0x00000040,
565         TXCS_FIFOTH_4QW         = 0x00000000,
566
567         TXCS_DMASIZE_64B        = 0x00000000,
568         TXCS_DMASIZE_128B       = 0x00000010,
569         TXCS_DMASIZE_256B       = 0x00000020,
570         TXCS_DMASIZE_512B       = 0x00000030,
571
572         TXCS_SELECT_QUEUE0      = 0x00000000,
573         TXCS_SELECT_QUEUE1      = 0x00010000,
574         TXCS_SELECT_QUEUE2      = 0x00020000,
575         TXCS_SELECT_QUEUE3      = 0x00030000,
576         TXCS_SELECT_QUEUE4      = 0x00040000,
577         TXCS_SELECT_QUEUE5      = 0x00050000,
578         TXCS_SELECT_QUEUE6      = 0x00060000,
579         TXCS_SELECT_QUEUE7      = 0x00070000,
580
581         TXCS_DEFAULT            = TXCS_FIFOTH_4QW |
582                                   TXCS_BURST,
583 };
584 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
585
586 /*
587  * TX MAC Control/Status Bits
588  */
589 enum jme_txmcs_bit_masks {
590         TXMCS_IFG2              = 0xC0000000,
591         TXMCS_IFG1              = 0x30000000,
592         TXMCS_TTHOLD            = 0x00000300,
593         TXMCS_FBURST            = 0x00000080,
594         TXMCS_CARRIEREXT        = 0x00000040,
595         TXMCS_DEFER             = 0x00000020,
596         TXMCS_BACKOFF           = 0x00000010,
597         TXMCS_CARRIERSENSE      = 0x00000008,
598         TXMCS_COLLISION         = 0x00000004,
599         TXMCS_CRC               = 0x00000002,
600         TXMCS_PADDING           = 0x00000001,
601 };
602 enum jme_txmcs_values {
603         TXMCS_IFG2_6_4          = 0x00000000,
604         TXMCS_IFG2_8_5          = 0x40000000,
605         TXMCS_IFG2_10_6         = 0x80000000,
606         TXMCS_IFG2_12_7         = 0xC0000000,
607
608         TXMCS_IFG1_8_4          = 0x00000000,
609         TXMCS_IFG1_12_6         = 0x10000000,
610         TXMCS_IFG1_16_8         = 0x20000000,
611         TXMCS_IFG1_20_10        = 0x30000000,
612
613         TXMCS_TTHOLD_1_8        = 0x00000000,
614         TXMCS_TTHOLD_1_4        = 0x00000100,
615         TXMCS_TTHOLD_1_2        = 0x00000200,
616         TXMCS_TTHOLD_FULL       = 0x00000300,
617
618         TXMCS_DEFAULT           = TXMCS_IFG2_8_5 |
619                                   TXMCS_IFG1_16_8 |
620                                   TXMCS_TTHOLD_FULL |
621                                   TXMCS_DEFER |
622                                   TXMCS_CRC |
623                                   TXMCS_PADDING,
624 };
625
626 enum jme_txpfc_bits_masks {
627         TXPFC_VLAN_TAG          = 0xFFFF0000,
628         TXPFC_VLAN_EN           = 0x00008000,
629         TXPFC_PF_EN             = 0x00000001,
630 };
631
632 enum jme_txtrhd_bits_masks {
633         TXTRHD_TXPEN            = 0x80000000,
634         TXTRHD_TXP              = 0x7FFFFF00,
635         TXTRHD_TXREN            = 0x00000080,
636         TXTRHD_TXRL             = 0x0000007F,
637 };
638 enum jme_txtrhd_shifts {
639         TXTRHD_TXP_SHIFT        = 8,
640         TXTRHD_TXRL_SHIFT       = 0,
641 };
642
643
644 /*
645  * RX Control/Status Bits
646  */
647 enum jme_rxcs_bit_masks {
648         /* FIFO full threshold for transmitting Tx Pause Packet */
649         RXCS_FIFOTHTP   = 0x30000000,
650         /* FIFO threshold for processing next packet */
651         RXCS_FIFOTHNP   = 0x0C000000,
652         RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
653         RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
654         RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
655         RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
656         RXCS_WAKEUP     = 0x00000040, /* Enable receive wakeup packet */
657         RXCS_MAGIC      = 0x00000020, /* Enable receive magic packet */
658         RXCS_SHORT      = 0x00000010, /* Enable receive short packet */
659         RXCS_ABORT      = 0x00000008, /* Enable receive errorr packet */
660         RXCS_QST        = 0x00000004, /* Receive queue start */
661         RXCS_SUSPEND    = 0x00000002,
662         RXCS_ENABLE     = 0x00000001,
663 };
664 enum jme_rxcs_values {
665         RXCS_FIFOTHTP_16T       = 0x00000000,
666         RXCS_FIFOTHTP_32T       = 0x10000000,
667         RXCS_FIFOTHTP_64T       = 0x20000000,
668         RXCS_FIFOTHTP_128T      = 0x30000000,
669
670         RXCS_FIFOTHNP_16QW      = 0x00000000,
671         RXCS_FIFOTHNP_32QW      = 0x04000000,
672         RXCS_FIFOTHNP_64QW      = 0x08000000,
673         RXCS_FIFOTHNP_128QW     = 0x0C000000,
674
675         RXCS_DMAREQSZ_16B       = 0x00000000,
676         RXCS_DMAREQSZ_32B       = 0x01000000,
677         RXCS_DMAREQSZ_64B       = 0x02000000,
678         RXCS_DMAREQSZ_128B      = 0x03000000,
679
680         RXCS_QUEUESEL_Q0        = 0x00000000,
681         RXCS_QUEUESEL_Q1        = 0x00010000,
682         RXCS_QUEUESEL_Q2        = 0x00020000,
683         RXCS_QUEUESEL_Q3        = 0x00030000,
684
685         RXCS_RETRYGAP_256ns     = 0x00000000,
686         RXCS_RETRYGAP_512ns     = 0x00001000,
687         RXCS_RETRYGAP_1024ns    = 0x00002000,
688         RXCS_RETRYGAP_2048ns    = 0x00003000,
689         RXCS_RETRYGAP_4096ns    = 0x00004000,
690         RXCS_RETRYGAP_8192ns    = 0x00005000,
691         RXCS_RETRYGAP_16384ns   = 0x00006000,
692         RXCS_RETRYGAP_32768ns   = 0x00007000,
693
694         RXCS_RETRYCNT_0         = 0x00000000,
695         RXCS_RETRYCNT_4         = 0x00000100,
696         RXCS_RETRYCNT_8         = 0x00000200,
697         RXCS_RETRYCNT_12        = 0x00000300,
698         RXCS_RETRYCNT_16        = 0x00000400,
699         RXCS_RETRYCNT_20        = 0x00000500,
700         RXCS_RETRYCNT_24        = 0x00000600,
701         RXCS_RETRYCNT_28        = 0x00000700,
702         RXCS_RETRYCNT_32        = 0x00000800,
703         RXCS_RETRYCNT_36        = 0x00000900,
704         RXCS_RETRYCNT_40        = 0x00000A00,
705         RXCS_RETRYCNT_44        = 0x00000B00,
706         RXCS_RETRYCNT_48        = 0x00000C00,
707         RXCS_RETRYCNT_52        = 0x00000D00,
708         RXCS_RETRYCNT_56        = 0x00000E00,
709         RXCS_RETRYCNT_60        = 0x00000F00,
710
711         RXCS_DEFAULT            = RXCS_FIFOTHTP_128T |
712                                   RXCS_FIFOTHNP_128QW |
713                                   RXCS_DMAREQSZ_128B |
714                                   RXCS_RETRYGAP_256ns |
715                                   RXCS_RETRYCNT_32,
716 };
717 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
718
719 /*
720  * RX MAC Control/Status Bits
721  */
722 enum jme_rxmcs_bits {
723         RXMCS_ALLFRAME          = 0x00000800,
724         RXMCS_BRDFRAME          = 0x00000400,
725         RXMCS_MULFRAME          = 0x00000200,
726         RXMCS_UNIFRAME          = 0x00000100,
727         RXMCS_ALLMULFRAME       = 0x00000080,
728         RXMCS_MULFILTERED       = 0x00000040,
729         RXMCS_RXCOLLDEC         = 0x00000020,
730         RXMCS_FLOWCTRL          = 0x00000008,
731         RXMCS_VTAGRM            = 0x00000004,
732         RXMCS_PREPAD            = 0x00000002,
733         RXMCS_CHECKSUM          = 0x00000001,
734
735         RXMCS_DEFAULT           = RXMCS_VTAGRM |
736                                   RXMCS_PREPAD |
737                                   RXMCS_FLOWCTRL |
738                                   RXMCS_CHECKSUM,
739 };
740
741 /*
742  * Wakeup Frame setup interface registers
743  */
744 #define WAKEUP_FRAME_NR 8
745 #define WAKEUP_FRAME_MASK_DWNR  4
746 enum jme_wfoi_bit_masks {
747         WFOI_MASK_SEL           = 0x00000070,
748         WFOI_CRC_SEL            = 0x00000008,
749         WFOI_FRAME_SEL          = 0x00000007,
750 };
751 enum jme_wfoi_shifts {
752         WFOI_MASK_SHIFT         = 4,
753 };
754
755 /*
756  * SMI Related definitions
757  */
758 enum jme_smi_bit_mask
759 {
760         SMI_DATA_MASK           = 0xFFFF0000,
761         SMI_REG_ADDR_MASK       = 0x0000F800,
762         SMI_PHY_ADDR_MASK       = 0x000007C0,
763         SMI_OP_WRITE            = 0x00000020,
764         /* Set to 1, after req done it'll be cleared to 0 */
765         SMI_OP_REQ              = 0x00000010,
766         SMI_OP_MDIO             = 0x00000008, /* Software assess In/Out */
767         SMI_OP_MDOE             = 0x00000004, /* Software Output Enable */
768         SMI_OP_MDC              = 0x00000002, /* Software CLK Control */
769         SMI_OP_MDEN             = 0x00000001, /* Software access Enable */
770 };
771 enum jme_smi_bit_shift
772 {
773         SMI_DATA_SHIFT          = 16,
774         SMI_REG_ADDR_SHIFT      = 11,
775         SMI_PHY_ADDR_SHIFT      = 6,
776 };
777 __always_inline __u32 smi_reg_addr(int x)
778 {
779         return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
780 }
781 __always_inline __u32 smi_phy_addr(int x)
782 {
783         return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
784 }
785 #define JME_PHY_TIMEOUT 100 /* 100 msec */
786 #define JME_PHY_REG_NR 32
787
788 /*
789  * Global Host Control
790  */
791 enum jme_ghc_bit_mask {
792         GHC_SWRST       = 0x40000000,
793         GHC_DPX         = 0x00000040,
794         GHC_SPEED       = 0x00000030,
795         GHC_LINK_POLL   = 0x00000001,
796 };
797 enum jme_ghc_speed_val {
798         GHC_SPEED_10M   = 0x00000010,
799         GHC_SPEED_100M  = 0x00000020,
800         GHC_SPEED_1000M = 0x00000030,
801 };
802
803 /*
804  * Power management control and status register
805  */
806 enum jme_pmcs_bit_masks {
807         PMCS_WF7DET     = 0x80000000,
808         PMCS_WF6DET     = 0x40000000,
809         PMCS_WF5DET     = 0x20000000,
810         PMCS_WF4DET     = 0x10000000,
811         PMCS_WF3DET     = 0x08000000,
812         PMCS_WF2DET     = 0x04000000,
813         PMCS_WF1DET     = 0x02000000,
814         PMCS_WF0DET     = 0x01000000,
815         PMCS_LFDET      = 0x00040000,
816         PMCS_LRDET      = 0x00020000,
817         PMCS_MFDET      = 0x00010000,
818         PMCS_WF7EN      = 0x00008000,
819         PMCS_WF6EN      = 0x00004000,
820         PMCS_WF5EN      = 0x00002000,
821         PMCS_WF4EN      = 0x00001000,
822         PMCS_WF3EN      = 0x00000800,
823         PMCS_WF2EN      = 0x00000400,
824         PMCS_WF1EN      = 0x00000200,
825         PMCS_WF0EN      = 0x00000100,
826         PMCS_LFEN       = 0x00000004,
827         PMCS_LREN       = 0x00000002,
828         PMCS_MFEN       = 0x00000001,
829 };
830
831 /*
832  * Giga PHY Status Registers
833  */
834 enum jme_phy_link_bit_mask {
835         PHY_LINK_SPEED_MASK             = 0x0000C000,
836         PHY_LINK_DUPLEX                 = 0x00002000,
837         PHY_LINK_SPEEDDPU_RESOLVED      = 0x00000800,
838         PHY_LINK_UP                     = 0x00000400,
839         PHY_LINK_AUTONEG_COMPLETE       = 0x00000200,
840         PHY_LINK_MDI_STAT               = 0x00000040,
841 };
842 enum jme_phy_link_speed_val {
843         PHY_LINK_SPEED_10M              = 0x00000000,
844         PHY_LINK_SPEED_100M             = 0x00004000,
845         PHY_LINK_SPEED_1000M            = 0x00008000,
846 };
847 #define JME_SPDRSV_TIMEOUT      500     /* 500 us */
848
849 /*
850  * SMB Control and Status
851  */
852 enum jme_smbcsr_bit_mask {
853         SMBCSR_CNACK    = 0x00020000,
854         SMBCSR_RELOAD   = 0x00010000,
855         SMBCSR_EEPROMD  = 0x00000020,
856         SMBCSR_INITDONE = 0x00000010,
857         SMBCSR_BUSY     = 0x0000000F,
858 };
859 enum jme_smbintf_bit_mask {
860         SMBINTF_HWDATR  = 0xFF000000,
861         SMBINTF_HWDATW  = 0x00FF0000,
862         SMBINTF_HWADDR  = 0x0000FF00,
863         SMBINTF_HWRWN   = 0x00000020,
864         SMBINTF_HWCMD   = 0x00000010,
865         SMBINTF_FASTM   = 0x00000008,
866         SMBINTF_GPIOSCL = 0x00000004,
867         SMBINTF_GPIOSDA = 0x00000002,
868         SMBINTF_GPIOEN  = 0x00000001,
869 };
870 enum jme_smbintf_vals {
871         SMBINTF_HWRWN_READ      = 0x00000020,
872         SMBINTF_HWRWN_WRITE     = 0x00000000,
873 };
874 enum jme_smbintf_shifts {
875         SMBINTF_HWDATR_SHIFT    = 24,
876         SMBINTF_HWDATW_SHIFT    = 16,
877         SMBINTF_HWADDR_SHIFT    = 8,
878 };
879 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
880 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
881 #define JME_SMB_LEN 256
882 #define JME_EEPROM_MAGIC 0x250
883
884 /*
885  * Timer Control/Status Register
886  */
887 enum jme_tmcsr_bit_masks {
888         TMCSR_SWIT      = 0x80000000,
889         TMCSR_EN        = 0x01000000,
890         TMCSR_CNT       = 0x00FFFFFF,
891 };
892
893
894 /*
895  * General Purpost REG-0
896  */
897 enum jme_gpreg0_masks {
898         GPREG0_DISSH            = 0xFF000000,
899         GPREG0_PCIRLMT          = 0x00300000,
900         GPREG0_PCCNOMUTCLR      = 0x00040000,
901         GPREG0_LNKINTPOLL       = 0x00001000,
902         GPREG0_PCCTMR           = 0x00000300,
903         GPREG0_PHYADDR          = 0x0000001F,
904 };
905 enum jme_gpreg0_vals {
906         GPREG0_DISSH_DW7        = 0x80000000,
907         GPREG0_DISSH_DW6        = 0x40000000,
908         GPREG0_DISSH_DW5        = 0x20000000,
909         GPREG0_DISSH_DW4        = 0x10000000,
910         GPREG0_DISSH_DW3        = 0x08000000,
911         GPREG0_DISSH_DW2        = 0x04000000,
912         GPREG0_DISSH_DW1        = 0x02000000,
913         GPREG0_DISSH_DW0        = 0x01000000,
914         GPREG0_DISSH_ALL        = 0xFF000000,
915
916         GPREG0_PCIRLMT_8        = 0x00000000,
917         GPREG0_PCIRLMT_6        = 0x00100000,
918         GPREG0_PCIRLMT_5        = 0x00200000,
919         GPREG0_PCIRLMT_4        = 0x00300000,
920
921         GPREG0_PCCTMR_16ns      = 0x00000000,
922         GPREG0_PCCTMR_256ns     = 0x00000100,
923         GPREG0_PCCTMR_1us       = 0x00000200,
924         GPREG0_PCCTMR_1ms       = 0x00000300,
925
926         GPREG0_PHYADDR_1        = 0x00000001,
927
928         GPREG0_DEFAULT          = GPREG0_PCIRLMT_4 |
929                                   GPREG0_PCCNOMUTCLR |
930                                   GPREG0_PCCTMR_1us |
931                                   GPREG0_PHYADDR_1,
932 };
933
934 /*
935  * Interrupt Status Bits
936  */
937 enum jme_interrupt_bits {
938         INTR_SWINTR     = 0x80000000,
939         INTR_TMINTR     = 0x40000000,
940         INTR_LINKCH     = 0x20000000,
941         INTR_PAUSERCV   = 0x10000000,
942         INTR_MAGICRCV   = 0x08000000,
943         INTR_WAKERCV    = 0x04000000,
944         INTR_PCCRX0TO   = 0x02000000,
945         INTR_PCCRX1TO   = 0x01000000,
946         INTR_PCCRX2TO   = 0x00800000,
947         INTR_PCCRX3TO   = 0x00400000,
948         INTR_PCCTXTO    = 0x00200000,
949         INTR_PCCRX0     = 0x00100000,
950         INTR_PCCRX1     = 0x00080000,
951         INTR_PCCRX2     = 0x00040000,
952         INTR_PCCRX3     = 0x00020000,
953         INTR_PCCTX      = 0x00010000,
954         INTR_RX3EMP     = 0x00008000,
955         INTR_RX2EMP     = 0x00004000,
956         INTR_RX1EMP     = 0x00002000,
957         INTR_RX0EMP     = 0x00001000,
958         INTR_RX3        = 0x00000800,
959         INTR_RX2        = 0x00000400,
960         INTR_RX1        = 0x00000200,
961         INTR_RX0        = 0x00000100,
962         INTR_TX7        = 0x00000080,
963         INTR_TX6        = 0x00000040,
964         INTR_TX5        = 0x00000020,
965         INTR_TX4        = 0x00000010,
966         INTR_TX3        = 0x00000008,
967         INTR_TX2        = 0x00000004,
968         INTR_TX1        = 0x00000002,
969         INTR_TX0        = 0x00000001,
970 };
971 enum jme_interrupt_enables {
972         INTR_ENABLE =   INTR_SWINTR |
973                         INTR_TMINTR |
974                         INTR_LINKCH |
975                         INTR_PCCRX0TO |
976                         INTR_PCCRX0 |
977                         INTR_PCCTXTO |
978                         INTR_PCCTX |
979                         INTR_RX0EMP,
980
981         INTR_EN_TX =    INTR_PCCTXTO |
982                         INTR_PCCTX,
983
984         INTR_EN_RX0 =   INTR_PCCRX0TO |
985                         INTR_PCCRX0 | 
986                         INTR_RX0EMP,
987
988         INTR_EN_MISC =  INTR_ENABLE & ~(INTR_EN_TX | INTR_EN_RX0),
989 };
990
991 /*
992  * PCC Control Registers
993  */
994 enum jme_pccrx_masks {
995         PCCRXTO_MASK    = 0xFFFF0000,
996         PCCRX_MASK      = 0x0000FF00,
997 };
998 enum jme_pcctx_masks {
999         PCCTXTO_MASK    = 0xFFFF0000,
1000         PCCTX_MASK      = 0x0000FF00,
1001         PCCTX_QS_MASK   = 0x000000FF,
1002 };
1003 enum jme_pccrx_shifts {
1004         PCCRXTO_SHIFT   = 16,
1005         PCCRX_SHIFT     = 8,
1006 };
1007 enum jme_pcctx_shifts {
1008         PCCTXTO_SHIFT   = 16,
1009         PCCTX_SHIFT     = 8,
1010 };
1011 enum jme_pcctx_bits {
1012         PCCTXQ0_EN      = 0x00000001,
1013         PCCTXQ1_EN      = 0x00000002,
1014         PCCTXQ2_EN      = 0x00000004,
1015         PCCTXQ3_EN      = 0x00000008,
1016         PCCTXQ4_EN      = 0x00000010,
1017         PCCTXQ5_EN      = 0x00000020,
1018         PCCTXQ6_EN      = 0x00000040,
1019         PCCTXQ7_EN      = 0x00000080,
1020 };
1021
1022 /*
1023  * Chip Mode Register
1024  */
1025 enum jme_chipmode_bit_masks {
1026         CM_FPGAVER_MASK         = 0xFFFF0000,
1027         CM_CHIPVER_MASK         = 0x0000FF00,
1028         CM_CHIPMODE_MASK        = 0x0000000F,
1029 };
1030 enum jme_chipmode_shifts {
1031         CM_FPGAVER_SHIFT        = 16,
1032         CM_CHIPVER_SHIFT        = 8,
1033 };
1034
1035 /*
1036  * Shadow base address register bits
1037  */
1038 enum jme_shadow_base_address_bits {
1039         SHBA_POSTEN     = 0x1,
1040 };
1041
1042 /*
1043  * Read/Write MMaped I/O Registers
1044  */
1045 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
1046 {
1047         return le32_to_cpu(readl((__u8*)jme->regs + reg));
1048 }
1049 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
1050 {
1051         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1052 }
1053 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
1054 {
1055         /*
1056          * Read after write should cause flush
1057          */
1058         writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1059         readl((__u8*)jme->regs + reg);
1060 }
1061
1062 /*
1063  * PHY Regs
1064  */
1065 enum jme_phy_reg17_bit_masks {
1066         PREG17_SPEED            = 0xC000,
1067         PREG17_DUPLEX           = 0x2000,
1068         PREG17_SPDRSV           = 0x0800,
1069         PREG17_LNKUP            = 0x0400,
1070         PREG17_MDI              = 0x0040,
1071 };
1072 enum jme_phy_reg17_vals {
1073         PREG17_SPEED_10M        = 0x0000,
1074         PREG17_SPEED_100M       = 0x4000,
1075         PREG17_SPEED_1000M      = 0x8000,
1076 };
1077 #define BMSR_ANCOMP               0x0020
1078
1079 /*
1080  * Function prototypes for ethtool
1081  */
1082 static void jme_get_drvinfo(struct net_device *netdev,
1083                              struct ethtool_drvinfo *info);
1084 static int jme_get_settings(struct net_device *netdev,
1085                              struct ethtool_cmd *ecmd);
1086 static int jme_set_settings(struct net_device *netdev,
1087                              struct ethtool_cmd *ecmd);
1088 static u32 jme_get_link(struct net_device *netdev);
1089
1090
1091 /*
1092  * Function prototypes for netdev
1093  */
1094 static int jme_open(struct net_device *netdev);
1095 static int jme_close(struct net_device *netdev);
1096 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
1097 static int jme_set_macaddr(struct net_device *netdev, void *p);
1098 static void jme_set_multi(struct net_device *netdev);
1099