2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/version.h>
25 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/crc32.h>
37 #include <linux/delay.h>
38 #include <linux/spinlock.h>
41 #include <linux/ipv6.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/if_vlan.h>
45 #include <linux/slab.h>
46 #include <net/ip6_checksum.h>
49 static int force_pseudohp = -1;
50 static int no_pseudohp = -1;
51 static int no_extplug = -1;
52 module_param(force_pseudohp, int, 0);
53 MODULE_PARM_DESC(force_pseudohp,
54 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
55 module_param(no_pseudohp, int, 0);
56 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
57 module_param(no_extplug, int, 0);
58 MODULE_PARM_DESC(no_extplug,
59 "Do not use external plug signal for pseudo hot-plug.");
62 jme_mdio_read(struct net_device *netdev, int phy, int reg)
64 struct jme_adapter *jme = netdev_priv(netdev);
65 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
68 jwrite32(jme, JME_SMI, SMI_OP_REQ |
73 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 val = jread32(jme, JME_SMI);
76 if ((val & SMI_OP_REQ) == 0)
81 pr_err("phy(%d) read timeout : %d\n", phy, reg);
88 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
92 jme_mdio_write(struct net_device *netdev,
93 int phy, int reg, int val)
95 struct jme_adapter *jme = netdev_priv(netdev);
98 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
99 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
100 smi_phy_addr(phy) | smi_reg_addr(reg));
103 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
110 pr_err("phy(%d) write timeout : %d\n", phy, reg);
114 jme_reset_phy_processor(struct jme_adapter *jme)
118 jme_mdio_write(jme->dev,
120 MII_ADVERTISE, ADVERTISE_ALL |
121 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
124 jme_mdio_write(jme->dev,
127 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
129 val = jme_mdio_read(jme->dev,
133 jme_mdio_write(jme->dev,
135 MII_BMCR, val | BMCR_RESET);
139 jme_setup_wakeup_frame(struct jme_adapter *jme,
140 u32 *mask, u32 crc, int fnr)
147 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 jwrite32(jme, JME_WFODP, crc);
155 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
156 jwrite32(jme, JME_WFOI,
157 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
158 (fnr & WFOI_FRAME_SEL));
160 jwrite32(jme, JME_WFODP, mask[i]);
166 jme_reset_mac_processor(struct jme_adapter *jme)
168 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
169 u32 crc = 0xCDCDCDCD;
173 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
175 jwrite32(jme, JME_GHC, jme->reg_ghc);
177 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
178 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
179 jwrite32(jme, JME_RXQDC, 0x00000000);
180 jwrite32(jme, JME_RXNDA, 0x00000000);
181 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
182 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
183 jwrite32(jme, JME_TXQDC, 0x00000000);
184 jwrite32(jme, JME_TXNDA, 0x00000000);
186 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
187 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
188 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
189 jme_setup_wakeup_frame(jme, mask, crc, i);
191 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
193 gpreg0 = GPREG0_DEFAULT;
194 jwrite32(jme, JME_GPREG0, gpreg0);
195 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
199 jme_reset_ghc_speed(struct jme_adapter *jme)
201 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
202 jwrite32(jme, JME_GHC, jme->reg_ghc);
206 jme_clear_pm(struct jme_adapter *jme)
208 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
209 pci_set_power_state(jme->pdev, PCI_D0);
210 pci_enable_wake(jme->pdev, PCI_D0, false);
214 jme_reload_eeprom(struct jme_adapter *jme)
219 val = jread32(jme, JME_SMBCSR);
221 if (val & SMBCSR_EEPROMD) {
223 jwrite32(jme, JME_SMBCSR, val);
224 val |= SMBCSR_RELOAD;
225 jwrite32(jme, JME_SMBCSR, val);
228 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
230 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
235 pr_err("eeprom reload timeout\n");
244 jme_load_macaddr(struct net_device *netdev)
246 struct jme_adapter *jme = netdev_priv(netdev);
247 unsigned char macaddr[6];
250 spin_lock_bh(&jme->macaddr_lock);
251 val = jread32(jme, JME_RXUMA_LO);
252 macaddr[0] = (val >> 0) & 0xFF;
253 macaddr[1] = (val >> 8) & 0xFF;
254 macaddr[2] = (val >> 16) & 0xFF;
255 macaddr[3] = (val >> 24) & 0xFF;
256 val = jread32(jme, JME_RXUMA_HI);
257 macaddr[4] = (val >> 0) & 0xFF;
258 macaddr[5] = (val >> 8) & 0xFF;
259 memcpy(netdev->dev_addr, macaddr, 6);
260 spin_unlock_bh(&jme->macaddr_lock);
264 jme_set_rx_pcc(struct jme_adapter *jme, int p)
268 jwrite32(jme, JME_PCCRX0,
269 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
270 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
273 jwrite32(jme, JME_PCCRX0,
274 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
275 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
278 jwrite32(jme, JME_PCCRX0,
279 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
280 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
283 jwrite32(jme, JME_PCCRX0,
284 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
285 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
292 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
293 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
297 jme_start_irq(struct jme_adapter *jme)
299 register struct dynpcc_info *dpi = &(jme->dpi);
301 jme_set_rx_pcc(jme, PCC_P1);
303 dpi->attempt = PCC_P1;
306 jwrite32(jme, JME_PCCTX,
307 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
308 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
315 jwrite32(jme, JME_IENS, INTR_ENABLE);
319 jme_stop_irq(struct jme_adapter *jme)
324 jwrite32f(jme, JME_IENC, INTR_ENABLE);
328 jme_linkstat_from_phy(struct jme_adapter *jme)
332 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
333 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
334 if (bmsr & BMSR_ANCOMP)
335 phylink |= PHY_LINK_AUTONEG_COMPLETE;
341 jme_set_phyfifoa(struct jme_adapter *jme)
343 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
347 jme_set_phyfifob(struct jme_adapter *jme)
349 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
353 jme_check_link(struct net_device *netdev, int testonly)
355 struct jme_adapter *jme = netdev_priv(netdev);
356 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
363 phylink = jme_linkstat_from_phy(jme);
365 phylink = jread32(jme, JME_PHY_LINK);
367 if (phylink & PHY_LINK_UP) {
368 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
370 * If we did not enable AN
371 * Speed/Duplex Info should be obtained from SMI
373 phylink = PHY_LINK_UP;
375 bmcr = jme_mdio_read(jme->dev,
379 phylink |= ((bmcr & BMCR_SPEED1000) &&
380 (bmcr & BMCR_SPEED100) == 0) ?
381 PHY_LINK_SPEED_1000M :
382 (bmcr & BMCR_SPEED100) ?
383 PHY_LINK_SPEED_100M :
386 phylink |= (bmcr & BMCR_FULLDPLX) ?
389 strcat(linkmsg, "Forced: ");
392 * Keep polling for speed/duplex resolve complete
394 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
400 phylink = jme_linkstat_from_phy(jme);
402 phylink = jread32(jme, JME_PHY_LINK);
405 pr_err("Waiting speed resolve timeout\n");
407 strcat(linkmsg, "ANed: ");
410 if (jme->phylink == phylink) {
417 jme->phylink = phylink;
419 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
420 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
421 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
422 switch (phylink & PHY_LINK_SPEED_MASK) {
423 case PHY_LINK_SPEED_10M:
424 ghc |= GHC_SPEED_10M |
425 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
426 strcat(linkmsg, "10 Mbps, ");
428 case PHY_LINK_SPEED_100M:
429 ghc |= GHC_SPEED_100M |
430 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
431 strcat(linkmsg, "100 Mbps, ");
433 case PHY_LINK_SPEED_1000M:
434 ghc |= GHC_SPEED_1000M |
435 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
436 strcat(linkmsg, "1000 Mbps, ");
442 if (phylink & PHY_LINK_DUPLEX) {
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
446 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
450 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
451 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
453 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
456 gpreg1 = GPREG1_DEFAULT;
457 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
458 if (!(phylink & PHY_LINK_DUPLEX))
459 gpreg1 |= GPREG1_HALFMODEPATCH;
460 switch (phylink & PHY_LINK_SPEED_MASK) {
461 case PHY_LINK_SPEED_10M:
462 jme_set_phyfifoa(jme);
463 gpreg1 |= GPREG1_RSSPATCH;
465 case PHY_LINK_SPEED_100M:
466 jme_set_phyfifob(jme);
467 gpreg1 |= GPREG1_RSSPATCH;
469 case PHY_LINK_SPEED_1000M:
470 jme_set_phyfifoa(jme);
477 jwrite32(jme, JME_GPREG1, gpreg1);
478 jwrite32(jme, JME_GHC, ghc);
481 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
484 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
487 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
488 netif_carrier_on(netdev);
493 netif_info(jme, link, jme->dev, "Link is down\n");
495 netif_carrier_off(netdev);
503 jme_setup_tx_resources(struct jme_adapter *jme)
505 struct jme_ring *txring = &(jme->txring[0]);
507 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
508 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
518 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
520 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
521 txring->next_to_use = 0;
522 atomic_set(&txring->next_to_clean, 0);
523 atomic_set(&txring->nr_free, jme->tx_ring_size);
525 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
526 jme->tx_ring_size, GFP_ATOMIC);
527 if (unlikely(!(txring->bufinf)))
528 goto err_free_txring;
531 * Initialize Transmit Descriptors
533 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
534 memset(txring->bufinf, 0,
535 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
540 dma_free_coherent(&(jme->pdev->dev),
541 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
547 txring->dmaalloc = 0;
549 txring->bufinf = NULL;
555 jme_free_tx_resources(struct jme_adapter *jme)
558 struct jme_ring *txring = &(jme->txring[0]);
559 struct jme_buffer_info *txbi;
562 if (txring->bufinf) {
563 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
564 txbi = txring->bufinf + i;
566 dev_kfree_skb(txbi->skb);
572 txbi->start_xmit = 0;
574 kfree(txring->bufinf);
577 dma_free_coherent(&(jme->pdev->dev),
578 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
582 txring->alloc = NULL;
584 txring->dmaalloc = 0;
586 txring->bufinf = NULL;
588 txring->next_to_use = 0;
589 atomic_set(&txring->next_to_clean, 0);
590 atomic_set(&txring->nr_free, 0);
594 jme_enable_tx_engine(struct jme_adapter *jme)
599 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
603 * Setup TX Queue 0 DMA Bass Address
605 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
606 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
607 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
610 * Setup TX Descptor Count
612 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
618 jwrite32(jme, JME_TXCS, jme->reg_txcs |
625 jme_restart_tx_engine(struct jme_adapter *jme)
630 jwrite32(jme, JME_TXCS, jme->reg_txcs |
636 jme_disable_tx_engine(struct jme_adapter *jme)
644 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
647 val = jread32(jme, JME_TXCS);
648 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
650 val = jread32(jme, JME_TXCS);
655 pr_err("Disable TX engine timeout\n");
659 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
661 struct jme_ring *rxring = &(jme->rxring[0]);
662 register struct rxdesc *rxdesc = rxring->desc;
663 struct jme_buffer_info *rxbi = rxring->bufinf;
669 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
670 rxdesc->desc1.bufaddrl = cpu_to_le32(
671 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
672 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
673 if (jme->dev->features & NETIF_F_HIGHDMA)
674 rxdesc->desc1.flags = RXFLAG_64BIT;
676 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
680 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
682 struct jme_ring *rxring = &(jme->rxring[0]);
683 struct jme_buffer_info *rxbi = rxring->bufinf + i;
686 skb = netdev_alloc_skb(jme->dev,
687 jme->dev->mtu + RX_EXTRA_LEN);
690 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
695 rxbi->len = skb_tailroom(skb);
696 rxbi->mapping = pci_map_page(jme->pdev,
697 virt_to_page(skb->data),
698 offset_in_page(skb->data),
706 jme_free_rx_buf(struct jme_adapter *jme, int i)
708 struct jme_ring *rxring = &(jme->rxring[0]);
709 struct jme_buffer_info *rxbi = rxring->bufinf;
713 pci_unmap_page(jme->pdev,
717 dev_kfree_skb(rxbi->skb);
725 jme_free_rx_resources(struct jme_adapter *jme)
728 struct jme_ring *rxring = &(jme->rxring[0]);
731 if (rxring->bufinf) {
732 for (i = 0 ; i < jme->rx_ring_size ; ++i)
733 jme_free_rx_buf(jme, i);
734 kfree(rxring->bufinf);
737 dma_free_coherent(&(jme->pdev->dev),
738 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
741 rxring->alloc = NULL;
743 rxring->dmaalloc = 0;
745 rxring->bufinf = NULL;
747 rxring->next_to_use = 0;
748 atomic_set(&rxring->next_to_clean, 0);
752 jme_setup_rx_resources(struct jme_adapter *jme)
755 struct jme_ring *rxring = &(jme->rxring[0]);
757 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
758 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
767 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
769 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
770 rxring->next_to_use = 0;
771 atomic_set(&rxring->next_to_clean, 0);
773 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
774 jme->rx_ring_size, GFP_ATOMIC);
775 if (unlikely(!(rxring->bufinf)))
776 goto err_free_rxring;
779 * Initiallize Receive Descriptors
781 memset(rxring->bufinf, 0,
782 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
783 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
784 if (unlikely(jme_make_new_rx_buf(jme, i))) {
785 jme_free_rx_resources(jme);
789 jme_set_clean_rxdesc(jme, i);
795 dma_free_coherent(&(jme->pdev->dev),
796 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
801 rxring->dmaalloc = 0;
803 rxring->bufinf = NULL;
809 jme_enable_rx_engine(struct jme_adapter *jme)
814 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
819 * Setup RX DMA Bass Address
821 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
822 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
823 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
826 * Setup RX Descriptor Count
828 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
831 * Setup Unicast Filter
833 jme_set_multi(jme->dev);
839 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
846 jme_restart_rx_engine(struct jme_adapter *jme)
851 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
858 jme_disable_rx_engine(struct jme_adapter *jme)
866 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
869 val = jread32(jme, JME_RXCS);
870 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
872 val = jread32(jme, JME_RXCS);
877 pr_err("Disable RX engine timeout\n");
882 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
884 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
887 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
888 == RXWBFLAG_TCPON)) {
889 if (flags & RXWBFLAG_IPV4)
890 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
894 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
895 == RXWBFLAG_UDPON)) {
896 if (flags & RXWBFLAG_IPV4)
897 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
901 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
903 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
911 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
913 struct jme_ring *rxring = &(jme->rxring[0]);
914 struct rxdesc *rxdesc = rxring->desc;
915 struct jme_buffer_info *rxbi = rxring->bufinf;
923 pci_dma_sync_single_for_cpu(jme->pdev,
928 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
929 pci_dma_sync_single_for_device(jme->pdev,
934 ++(NET_STAT(jme).rx_dropped);
936 framesize = le16_to_cpu(rxdesc->descwb.framesize)
939 skb_reserve(skb, RX_PREPAD_SIZE);
940 skb_put(skb, framesize);
941 skb->protocol = eth_type_trans(skb, jme->dev);
943 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
944 skb->ip_summed = CHECKSUM_UNNECESSARY;
946 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
947 skb->ip_summed = CHECKSUM_NONE;
949 skb_checksum_none_assert(skb);
952 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
954 jme->jme_vlan_rx(skb, jme->vlgrp,
955 le16_to_cpu(rxdesc->descwb.vlan));
956 NET_STAT(jme).rx_bytes += 4;
964 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
965 cpu_to_le16(RXWBFLAG_DEST_MUL))
966 ++(NET_STAT(jme).multicast);
968 NET_STAT(jme).rx_bytes += framesize;
969 ++(NET_STAT(jme).rx_packets);
972 jme_set_clean_rxdesc(jme, idx);
977 jme_process_receive(struct jme_adapter *jme, int limit)
979 struct jme_ring *rxring = &(jme->rxring[0]);
980 struct rxdesc *rxdesc = rxring->desc;
981 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
983 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
986 if (unlikely(atomic_read(&jme->link_changing) != 1))
989 if (unlikely(!netif_carrier_ok(jme->dev)))
992 i = atomic_read(&rxring->next_to_clean);
994 rxdesc = rxring->desc;
997 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
998 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1002 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1004 if (unlikely(desccnt > 1 ||
1005 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1007 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1008 ++(NET_STAT(jme).rx_crc_errors);
1009 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1010 ++(NET_STAT(jme).rx_fifo_errors);
1012 ++(NET_STAT(jme).rx_errors);
1015 limit -= desccnt - 1;
1017 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1018 jme_set_clean_rxdesc(jme, j);
1019 j = (j + 1) & (mask);
1023 jme_alloc_and_feed_skb(jme, i);
1026 i = (i + desccnt) & (mask);
1030 atomic_set(&rxring->next_to_clean, i);
1033 atomic_inc(&jme->rx_cleaning);
1035 return limit > 0 ? limit : 0;
1040 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1042 if (likely(atmp == dpi->cur)) {
1047 if (dpi->attempt == atmp) {
1050 dpi->attempt = atmp;
1057 jme_dynamic_pcc(struct jme_adapter *jme)
1059 register struct dynpcc_info *dpi = &(jme->dpi);
1061 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1062 jme_attempt_pcc(dpi, PCC_P3);
1063 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1064 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1065 jme_attempt_pcc(dpi, PCC_P2);
1067 jme_attempt_pcc(dpi, PCC_P1);
1069 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1070 if (dpi->attempt < dpi->cur)
1071 tasklet_schedule(&jme->rxclean_task);
1072 jme_set_rx_pcc(jme, dpi->attempt);
1073 dpi->cur = dpi->attempt;
1079 jme_start_pcc_timer(struct jme_adapter *jme)
1081 struct dynpcc_info *dpi = &(jme->dpi);
1082 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1083 dpi->last_pkts = NET_STAT(jme).rx_packets;
1085 jwrite32(jme, JME_TMCSR,
1086 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1090 jme_stop_pcc_timer(struct jme_adapter *jme)
1092 jwrite32(jme, JME_TMCSR, 0);
1096 jme_shutdown_nic(struct jme_adapter *jme)
1100 phylink = jme_linkstat_from_phy(jme);
1102 if (!(phylink & PHY_LINK_UP)) {
1104 * Disable all interrupt before issue timer
1107 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1112 jme_pcc_tasklet(unsigned long arg)
1114 struct jme_adapter *jme = (struct jme_adapter *)arg;
1115 struct net_device *netdev = jme->dev;
1117 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1118 jme_shutdown_nic(jme);
1122 if (unlikely(!netif_carrier_ok(netdev) ||
1123 (atomic_read(&jme->link_changing) != 1)
1125 jme_stop_pcc_timer(jme);
1129 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1130 jme_dynamic_pcc(jme);
1132 jme_start_pcc_timer(jme);
1136 jme_polling_mode(struct jme_adapter *jme)
1138 jme_set_rx_pcc(jme, PCC_OFF);
1142 jme_interrupt_mode(struct jme_adapter *jme)
1144 jme_set_rx_pcc(jme, PCC_P1);
1148 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1151 apmc = jread32(jme, JME_APMC);
1152 return apmc & JME_APMC_PSEUDO_HP_EN;
1156 jme_start_shutdown_timer(struct jme_adapter *jme)
1160 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1161 apmc &= ~JME_APMC_EPIEN_CTRL;
1163 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1166 jwrite32f(jme, JME_APMC, apmc);
1168 jwrite32f(jme, JME_TIMER2, 0);
1169 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1170 jwrite32(jme, JME_TMCSR,
1171 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1175 jme_stop_shutdown_timer(struct jme_adapter *jme)
1179 jwrite32f(jme, JME_TMCSR, 0);
1180 jwrite32f(jme, JME_TIMER2, 0);
1181 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1183 apmc = jread32(jme, JME_APMC);
1184 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1185 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1187 jwrite32f(jme, JME_APMC, apmc);
1191 jme_link_change_tasklet(unsigned long arg)
1193 struct jme_adapter *jme = (struct jme_adapter *)arg;
1194 struct net_device *netdev = jme->dev;
1197 while (!atomic_dec_and_test(&jme->link_changing)) {
1198 atomic_inc(&jme->link_changing);
1199 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1200 while (atomic_read(&jme->link_changing) != 1)
1201 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1204 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1207 jme->old_mtu = netdev->mtu;
1208 netif_stop_queue(netdev);
1209 if (jme_pseudo_hotplug_enabled(jme))
1210 jme_stop_shutdown_timer(jme);
1212 jme_stop_pcc_timer(jme);
1213 tasklet_disable(&jme->txclean_task);
1214 tasklet_disable(&jme->rxclean_task);
1215 tasklet_disable(&jme->rxempty_task);
1217 if (netif_carrier_ok(netdev)) {
1218 jme_reset_ghc_speed(jme);
1219 jme_disable_rx_engine(jme);
1220 jme_disable_tx_engine(jme);
1221 jme_reset_mac_processor(jme);
1222 jme_free_rx_resources(jme);
1223 jme_free_tx_resources(jme);
1225 if (test_bit(JME_FLAG_POLL, &jme->flags))
1226 jme_polling_mode(jme);
1228 netif_carrier_off(netdev);
1231 jme_check_link(netdev, 0);
1232 if (netif_carrier_ok(netdev)) {
1233 rc = jme_setup_rx_resources(jme);
1235 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1236 goto out_enable_tasklet;
1239 rc = jme_setup_tx_resources(jme);
1241 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1242 goto err_out_free_rx_resources;
1245 jme_enable_rx_engine(jme);
1246 jme_enable_tx_engine(jme);
1248 netif_start_queue(netdev);
1250 if (test_bit(JME_FLAG_POLL, &jme->flags))
1251 jme_interrupt_mode(jme);
1253 jme_start_pcc_timer(jme);
1254 } else if (jme_pseudo_hotplug_enabled(jme)) {
1255 jme_start_shutdown_timer(jme);
1258 goto out_enable_tasklet;
1260 err_out_free_rx_resources:
1261 jme_free_rx_resources(jme);
1263 tasklet_enable(&jme->txclean_task);
1264 tasklet_hi_enable(&jme->rxclean_task);
1265 tasklet_hi_enable(&jme->rxempty_task);
1267 atomic_inc(&jme->link_changing);
1271 jme_rx_clean_tasklet(unsigned long arg)
1273 struct jme_adapter *jme = (struct jme_adapter *)arg;
1274 struct dynpcc_info *dpi = &(jme->dpi);
1276 jme_process_receive(jme, jme->rx_ring_size);
1282 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1284 struct jme_adapter *jme = jme_napi_priv(holder);
1288 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1290 while (atomic_read(&jme->rx_empty) > 0) {
1291 atomic_dec(&jme->rx_empty);
1292 ++(NET_STAT(jme).rx_dropped);
1293 jme_restart_rx_engine(jme);
1295 atomic_inc(&jme->rx_empty);
1298 JME_RX_COMPLETE(netdev, holder);
1299 jme_interrupt_mode(jme);
1302 JME_NAPI_WEIGHT_SET(budget, rest);
1303 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1307 jme_rx_empty_tasklet(unsigned long arg)
1309 struct jme_adapter *jme = (struct jme_adapter *)arg;
1311 if (unlikely(atomic_read(&jme->link_changing) != 1))
1314 if (unlikely(!netif_carrier_ok(jme->dev)))
1317 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1319 jme_rx_clean_tasklet(arg);
1321 while (atomic_read(&jme->rx_empty) > 0) {
1322 atomic_dec(&jme->rx_empty);
1323 ++(NET_STAT(jme).rx_dropped);
1324 jme_restart_rx_engine(jme);
1326 atomic_inc(&jme->rx_empty);
1330 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1332 struct jme_ring *txring = &(jme->txring[0]);
1335 if (unlikely(netif_queue_stopped(jme->dev) &&
1336 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1337 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1338 netif_wake_queue(jme->dev);
1344 jme_tx_clean_tasklet(unsigned long arg)
1346 struct jme_adapter *jme = (struct jme_adapter *)arg;
1347 struct jme_ring *txring = &(jme->txring[0]);
1348 struct txdesc *txdesc = txring->desc;
1349 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1350 int i, j, cnt = 0, max, err, mask;
1352 tx_dbg(jme, "Into txclean\n");
1354 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1357 if (unlikely(atomic_read(&jme->link_changing) != 1))
1360 if (unlikely(!netif_carrier_ok(jme->dev)))
1363 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1364 mask = jme->tx_ring_mask;
1366 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1370 if (likely(ctxbi->skb &&
1371 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1373 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1374 i, ctxbi->nr_desc, jiffies);
1376 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1378 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1379 ttxbi = txbi + ((i + j) & (mask));
1380 txdesc[(i + j) & (mask)].dw[0] = 0;
1382 pci_unmap_page(jme->pdev,
1391 dev_kfree_skb(ctxbi->skb);
1393 cnt += ctxbi->nr_desc;
1395 if (unlikely(err)) {
1396 ++(NET_STAT(jme).tx_carrier_errors);
1398 ++(NET_STAT(jme).tx_packets);
1399 NET_STAT(jme).tx_bytes += ctxbi->len;
1404 ctxbi->start_xmit = 0;
1410 i = (i + ctxbi->nr_desc) & mask;
1415 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1416 atomic_set(&txring->next_to_clean, i);
1417 atomic_add(cnt, &txring->nr_free);
1419 jme_wake_queue_if_stopped(jme);
1422 atomic_inc(&jme->tx_cleaning);
1426 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1431 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1433 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1435 * Link change event is critical
1436 * all other events are ignored
1438 jwrite32(jme, JME_IEVE, intrstat);
1439 tasklet_schedule(&jme->linkch_task);
1443 if (intrstat & INTR_TMINTR) {
1444 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1445 tasklet_schedule(&jme->pcc_task);
1448 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1449 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1450 tasklet_schedule(&jme->txclean_task);
1453 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1460 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1461 if (intrstat & INTR_RX0EMP)
1462 atomic_inc(&jme->rx_empty);
1464 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1465 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1466 jme_polling_mode(jme);
1467 JME_RX_SCHEDULE(jme);
1471 if (intrstat & INTR_RX0EMP) {
1472 atomic_inc(&jme->rx_empty);
1473 tasklet_hi_schedule(&jme->rxempty_task);
1474 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1475 tasklet_hi_schedule(&jme->rxclean_task);
1481 * Re-enable interrupt
1483 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1486 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1488 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1491 jme_intr(int irq, void *dev_id)
1494 struct net_device *netdev = dev_id;
1495 struct jme_adapter *jme = netdev_priv(netdev);
1498 intrstat = jread32(jme, JME_IEVE);
1501 * Check if it's really an interrupt for us
1503 if (unlikely((intrstat & INTR_ENABLE) == 0))
1507 * Check if the device still exist
1509 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1512 jme_intr_msi(jme, intrstat);
1517 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1519 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1522 jme_msi(int irq, void *dev_id)
1525 struct net_device *netdev = dev_id;
1526 struct jme_adapter *jme = netdev_priv(netdev);
1529 intrstat = jread32(jme, JME_IEVE);
1531 jme_intr_msi(jme, intrstat);
1537 jme_reset_link(struct jme_adapter *jme)
1539 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1543 jme_restart_an(struct jme_adapter *jme)
1547 spin_lock_bh(&jme->phy_lock);
1548 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1549 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1550 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1551 spin_unlock_bh(&jme->phy_lock);
1555 jme_request_irq(struct jme_adapter *jme)
1558 struct net_device *netdev = jme->dev;
1559 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1560 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1561 int irq_flags = SA_SHIRQ;
1563 irq_handler_t handler = jme_intr;
1564 int irq_flags = IRQF_SHARED;
1567 if (!pci_enable_msi(jme->pdev)) {
1568 set_bit(JME_FLAG_MSI, &jme->flags);
1573 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1577 "Unable to request %s interrupt (return: %d)\n",
1578 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1581 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1582 pci_disable_msi(jme->pdev);
1583 clear_bit(JME_FLAG_MSI, &jme->flags);
1586 netdev->irq = jme->pdev->irq;
1593 jme_free_irq(struct jme_adapter *jme)
1595 free_irq(jme->pdev->irq, jme->dev);
1596 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1597 pci_disable_msi(jme->pdev);
1598 clear_bit(JME_FLAG_MSI, &jme->flags);
1599 jme->dev->irq = jme->pdev->irq;
1604 jme_phy_on(struct jme_adapter *jme)
1608 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1609 bmcr &= ~BMCR_PDOWN;
1610 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1614 jme_open(struct net_device *netdev)
1616 struct jme_adapter *jme = netdev_priv(netdev);
1620 JME_NAPI_ENABLE(jme);
1622 tasklet_enable(&jme->linkch_task);
1623 tasklet_enable(&jme->txclean_task);
1624 tasklet_hi_enable(&jme->rxclean_task);
1625 tasklet_hi_enable(&jme->rxempty_task);
1627 rc = jme_request_irq(jme);
1633 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1635 jme_set_settings(netdev, &jme->old_ecmd);
1637 jme_reset_phy_processor(jme);
1640 jme_reset_link(jme);
1645 netif_stop_queue(netdev);
1646 netif_carrier_off(netdev);
1652 jme_set_100m_half(struct jme_adapter *jme)
1656 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1657 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1658 BMCR_SPEED1000 | BMCR_FULLDPLX);
1659 tmp |= BMCR_SPEED100;
1662 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1665 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1667 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1670 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1672 jme_wait_link(struct jme_adapter *jme)
1674 u32 phylink, to = JME_WAIT_LINK_TIME;
1677 phylink = jme_linkstat_from_phy(jme);
1678 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1680 phylink = jme_linkstat_from_phy(jme);
1686 jme_phy_off(struct jme_adapter *jme)
1688 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1692 jme_close(struct net_device *netdev)
1694 struct jme_adapter *jme = netdev_priv(netdev);
1696 netif_stop_queue(netdev);
1697 netif_carrier_off(netdev);
1702 JME_NAPI_DISABLE(jme);
1704 tasklet_disable(&jme->linkch_task);
1705 tasklet_disable(&jme->txclean_task);
1706 tasklet_disable(&jme->rxclean_task);
1707 tasklet_disable(&jme->rxempty_task);
1709 jme_reset_ghc_speed(jme);
1710 jme_disable_rx_engine(jme);
1711 jme_disable_tx_engine(jme);
1712 jme_reset_mac_processor(jme);
1713 jme_free_rx_resources(jme);
1714 jme_free_tx_resources(jme);
1722 jme_alloc_txdesc(struct jme_adapter *jme,
1723 struct sk_buff *skb)
1725 struct jme_ring *txring = &(jme->txring[0]);
1726 int idx, nr_alloc, mask = jme->tx_ring_mask;
1728 idx = txring->next_to_use;
1729 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1731 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1734 atomic_sub(nr_alloc, &txring->nr_free);
1736 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1742 jme_fill_tx_map(struct pci_dev *pdev,
1743 struct txdesc *txdesc,
1744 struct jme_buffer_info *txbi,
1752 dmaaddr = pci_map_page(pdev,
1758 pci_dma_sync_single_for_device(pdev,
1765 txdesc->desc2.flags = TXFLAG_OWN;
1766 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1767 txdesc->desc2.datalen = cpu_to_le16(len);
1768 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1769 txdesc->desc2.bufaddrl = cpu_to_le32(
1770 (__u64)dmaaddr & 0xFFFFFFFFUL);
1772 txbi->mapping = dmaaddr;
1777 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1779 struct jme_ring *txring = &(jme->txring[0]);
1780 struct txdesc *txdesc = txring->desc, *ctxdesc;
1781 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1782 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1783 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1784 int mask = jme->tx_ring_mask;
1785 struct skb_frag_struct *frag;
1788 for (i = 0 ; i < nr_frags ; ++i) {
1789 frag = &skb_shinfo(skb)->frags[i];
1790 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1791 ctxbi = txbi + ((idx + i + 2) & (mask));
1793 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1794 frag->page_offset, frag->size, hidma);
1797 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1798 ctxdesc = txdesc + ((idx + 1) & (mask));
1799 ctxbi = txbi + ((idx + 1) & (mask));
1800 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1801 offset_in_page(skb->data), len, hidma);
1806 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1809 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1810 skb_shinfo(skb)->tso_size
1812 skb_shinfo(skb)->gso_size
1814 && skb_header_cloned(skb) &&
1815 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1824 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1826 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1827 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1829 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1832 *flags |= TXFLAG_LSEN;
1834 if (skb->protocol == htons(ETH_P_IP)) {
1835 struct iphdr *iph = ip_hdr(skb);
1838 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1843 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1845 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1858 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1860 #ifdef CHECKSUM_PARTIAL
1861 if (skb->ip_summed == CHECKSUM_PARTIAL)
1863 if (skb->ip_summed == CHECKSUM_HW)
1868 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1869 if (skb->protocol == htons(ETH_P_IP))
1870 ip_proto = ip_hdr(skb)->protocol;
1871 else if (skb->protocol == htons(ETH_P_IPV6))
1872 ip_proto = ipv6_hdr(skb)->nexthdr;
1876 switch (skb->protocol) {
1877 case htons(ETH_P_IP):
1878 ip_proto = ip_hdr(skb)->protocol;
1880 case htons(ETH_P_IPV6):
1881 ip_proto = ipv6_hdr(skb)->nexthdr;
1891 *flags |= TXFLAG_TCPCS;
1894 *flags |= TXFLAG_UDPCS;
1897 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1904 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1906 if (vlan_tx_tag_present(skb)) {
1907 *flags |= TXFLAG_TAGON;
1908 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1913 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1915 struct jme_ring *txring = &(jme->txring[0]);
1916 struct txdesc *txdesc;
1917 struct jme_buffer_info *txbi;
1920 txdesc = (struct txdesc *)txring->desc + idx;
1921 txbi = txring->bufinf + idx;
1927 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1929 * Set OWN bit at final.
1930 * When kernel transmit faster than NIC.
1931 * And NIC trying to send this descriptor before we tell
1932 * it to start sending this TX queue.
1933 * Other fields are already filled correctly.
1936 flags = TXFLAG_OWN | TXFLAG_INT;
1938 * Set checksum flags while not tso
1940 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1941 jme_tx_csum(jme, skb, &flags);
1942 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1943 jme_map_tx_skb(jme, skb, idx);
1944 txdesc->desc1.flags = flags;
1946 * Set tx buffer info after telling NIC to send
1947 * For better tx_clean timing
1950 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1952 txbi->len = skb->len;
1953 txbi->start_xmit = jiffies;
1954 if (!txbi->start_xmit)
1955 txbi->start_xmit = (0UL-1);
1961 jme_stop_queue_if_full(struct jme_adapter *jme)
1963 struct jme_ring *txring = &(jme->txring[0]);
1964 struct jme_buffer_info *txbi = txring->bufinf;
1965 int idx = atomic_read(&txring->next_to_clean);
1970 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1971 netif_stop_queue(jme->dev);
1972 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1974 if (atomic_read(&txring->nr_free)
1975 >= (jme->tx_wake_threshold)) {
1976 netif_wake_queue(jme->dev);
1977 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1981 if (unlikely(txbi->start_xmit &&
1982 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1984 netif_stop_queue(jme->dev);
1985 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
1990 * This function is already protected by netif_tx_lock()
1993 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
1998 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2000 struct jme_adapter *jme = netdev_priv(netdev);
2003 if (unlikely(jme_expand_header(jme, skb))) {
2004 ++(NET_STAT(jme).tx_dropped);
2005 return NETDEV_TX_OK;
2008 idx = jme_alloc_txdesc(jme, skb);
2010 if (unlikely(idx < 0)) {
2011 netif_stop_queue(netdev);
2012 netif_err(jme, tx_err, jme->dev,
2013 "BUG! Tx ring full when queue awake!\n");
2015 return NETDEV_TX_BUSY;
2018 jme_fill_tx_desc(jme, skb, idx);
2020 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2021 TXCS_SELECT_QUEUE0 |
2024 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2025 netdev->trans_start = jiffies;
2028 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2029 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2030 jme_stop_queue_if_full(jme);
2032 return NETDEV_TX_OK;
2036 jme_set_macaddr(struct net_device *netdev, void *p)
2038 struct jme_adapter *jme = netdev_priv(netdev);
2039 struct sockaddr *addr = p;
2042 if (netif_running(netdev))
2045 spin_lock_bh(&jme->macaddr_lock);
2046 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2048 val = (addr->sa_data[3] & 0xff) << 24 |
2049 (addr->sa_data[2] & 0xff) << 16 |
2050 (addr->sa_data[1] & 0xff) << 8 |
2051 (addr->sa_data[0] & 0xff);
2052 jwrite32(jme, JME_RXUMA_LO, val);
2053 val = (addr->sa_data[5] & 0xff) << 8 |
2054 (addr->sa_data[4] & 0xff);
2055 jwrite32(jme, JME_RXUMA_HI, val);
2056 spin_unlock_bh(&jme->macaddr_lock);
2062 jme_set_multi(struct net_device *netdev)
2064 struct jme_adapter *jme = netdev_priv(netdev);
2065 u32 mc_hash[2] = {};
2066 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2070 spin_lock_bh(&jme->rxmcs_lock);
2072 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2074 if (netdev->flags & IFF_PROMISC) {
2075 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2076 } else if (netdev->flags & IFF_ALLMULTI) {
2077 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2078 } else if (netdev->flags & IFF_MULTICAST) {
2079 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2080 struct dev_mc_list *mclist;
2082 struct netdev_hw_addr *ha;
2086 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2087 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2088 for (i = 0, mclist = netdev->mc_list;
2089 mclist && i < netdev->mc_count;
2090 ++i, mclist = mclist->next) {
2091 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2092 netdev_for_each_mc_addr(mclist, netdev) {
2094 netdev_for_each_mc_addr(ha, netdev) {
2096 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2097 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2099 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2101 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2104 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2105 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2109 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2111 spin_unlock_bh(&jme->rxmcs_lock);
2115 jme_change_mtu(struct net_device *netdev, int new_mtu)
2117 struct jme_adapter *jme = netdev_priv(netdev);
2119 if (new_mtu == jme->old_mtu)
2122 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2123 ((new_mtu) < IPV6_MIN_MTU))
2126 if (new_mtu > 4000) {
2127 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2128 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2129 jme_restart_rx_engine(jme);
2131 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2132 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2133 jme_restart_rx_engine(jme);
2136 if (new_mtu > 1900) {
2137 netdev->features &= ~(NETIF_F_HW_CSUM |
2144 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2145 netdev->features |= NETIF_F_HW_CSUM;
2146 if (test_bit(JME_FLAG_TSO, &jme->flags))
2147 netdev->features |= NETIF_F_TSO
2154 netdev->mtu = new_mtu;
2155 jme_reset_link(jme);
2161 jme_tx_timeout(struct net_device *netdev)
2163 struct jme_adapter *jme = netdev_priv(netdev);
2166 jme_reset_phy_processor(jme);
2167 if (test_bit(JME_FLAG_SSET, &jme->flags))
2168 jme_set_settings(netdev, &jme->old_ecmd);
2171 * Force to Reset the link again
2173 jme_reset_link(jme);
2176 static inline void jme_pause_rx(struct jme_adapter *jme)
2178 atomic_dec(&jme->link_changing);
2180 jme_set_rx_pcc(jme, PCC_OFF);
2181 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2182 JME_NAPI_DISABLE(jme);
2184 tasklet_disable(&jme->rxclean_task);
2185 tasklet_disable(&jme->rxempty_task);
2189 static inline void jme_resume_rx(struct jme_adapter *jme)
2191 struct dynpcc_info *dpi = &(jme->dpi);
2193 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2194 JME_NAPI_ENABLE(jme);
2196 tasklet_hi_enable(&jme->rxclean_task);
2197 tasklet_hi_enable(&jme->rxempty_task);
2200 dpi->attempt = PCC_P1;
2202 jme_set_rx_pcc(jme, PCC_P1);
2204 atomic_inc(&jme->link_changing);
2208 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2210 struct jme_adapter *jme = netdev_priv(netdev);
2217 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2219 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2221 struct jme_adapter *jme = netdev_priv(netdev);
2225 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2226 jme->vlgrp->vlan_devices[vid] = NULL;
2228 vlan_group_set_device(jme->vlgrp, vid, NULL);
2236 jme_get_drvinfo(struct net_device *netdev,
2237 struct ethtool_drvinfo *info)
2239 struct jme_adapter *jme = netdev_priv(netdev);
2241 strcpy(info->driver, DRV_NAME);
2242 strcpy(info->version, DRV_VERSION);
2243 strcpy(info->bus_info, pci_name(jme->pdev));
2247 jme_get_regs_len(struct net_device *netdev)
2253 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2257 for (i = 0 ; i < len ; i += 4)
2258 p[i >> 2] = jread32(jme, reg + i);
2262 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2265 u16 *p16 = (u16 *)p;
2267 for (i = 0 ; i < reg_nr ; ++i)
2268 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2272 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2274 struct jme_adapter *jme = netdev_priv(netdev);
2275 u32 *p32 = (u32 *)p;
2277 memset(p, 0xFF, JME_REG_LEN);
2280 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2283 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2286 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2289 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2292 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2296 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2298 struct jme_adapter *jme = netdev_priv(netdev);
2300 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2301 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2303 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2304 ecmd->use_adaptive_rx_coalesce = false;
2305 ecmd->rx_coalesce_usecs = 0;
2306 ecmd->rx_max_coalesced_frames = 0;
2310 ecmd->use_adaptive_rx_coalesce = true;
2312 switch (jme->dpi.cur) {
2314 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2315 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2318 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2319 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2322 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2323 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2333 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2335 struct jme_adapter *jme = netdev_priv(netdev);
2336 struct dynpcc_info *dpi = &(jme->dpi);
2338 if (netif_running(netdev))
2341 if (ecmd->use_adaptive_rx_coalesce &&
2342 test_bit(JME_FLAG_POLL, &jme->flags)) {
2343 clear_bit(JME_FLAG_POLL, &jme->flags);
2344 jme->jme_rx = netif_rx;
2345 jme->jme_vlan_rx = vlan_hwaccel_rx;
2347 dpi->attempt = PCC_P1;
2349 jme_set_rx_pcc(jme, PCC_P1);
2350 jme_interrupt_mode(jme);
2351 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2352 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2353 set_bit(JME_FLAG_POLL, &jme->flags);
2354 jme->jme_rx = netif_receive_skb;
2355 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2356 jme_interrupt_mode(jme);
2363 jme_get_pauseparam(struct net_device *netdev,
2364 struct ethtool_pauseparam *ecmd)
2366 struct jme_adapter *jme = netdev_priv(netdev);
2369 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2370 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2372 spin_lock_bh(&jme->phy_lock);
2373 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2374 spin_unlock_bh(&jme->phy_lock);
2377 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2381 jme_set_pauseparam(struct net_device *netdev,
2382 struct ethtool_pauseparam *ecmd)
2384 struct jme_adapter *jme = netdev_priv(netdev);
2387 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2388 (ecmd->tx_pause != 0)) {
2391 jme->reg_txpfc |= TXPFC_PF_EN;
2393 jme->reg_txpfc &= ~TXPFC_PF_EN;
2395 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2398 spin_lock_bh(&jme->rxmcs_lock);
2399 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2400 (ecmd->rx_pause != 0)) {
2403 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2405 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2407 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2409 spin_unlock_bh(&jme->rxmcs_lock);
2411 spin_lock_bh(&jme->phy_lock);
2412 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2413 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2414 (ecmd->autoneg != 0)) {
2417 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2419 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2421 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2422 MII_ADVERTISE, val);
2424 spin_unlock_bh(&jme->phy_lock);
2430 jme_get_wol(struct net_device *netdev,
2431 struct ethtool_wolinfo *wol)
2433 struct jme_adapter *jme = netdev_priv(netdev);
2435 wol->supported = WAKE_MAGIC | WAKE_PHY;
2439 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2440 wol->wolopts |= WAKE_PHY;
2442 if (jme->reg_pmcs & PMCS_MFEN)
2443 wol->wolopts |= WAKE_MAGIC;
2448 jme_set_wol(struct net_device *netdev,
2449 struct ethtool_wolinfo *wol)
2451 struct jme_adapter *jme = netdev_priv(netdev);
2453 if (wol->wolopts & (WAKE_MAGICSECURE |
2462 if (wol->wolopts & WAKE_PHY)
2463 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2465 if (wol->wolopts & WAKE_MAGIC)
2466 jme->reg_pmcs |= PMCS_MFEN;
2468 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2474 jme_get_settings(struct net_device *netdev,
2475 struct ethtool_cmd *ecmd)
2477 struct jme_adapter *jme = netdev_priv(netdev);
2480 spin_lock_bh(&jme->phy_lock);
2481 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2482 spin_unlock_bh(&jme->phy_lock);
2487 jme_set_settings(struct net_device *netdev,
2488 struct ethtool_cmd *ecmd)
2490 struct jme_adapter *jme = netdev_priv(netdev);
2493 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2496 if (jme->mii_if.force_media &&
2497 ecmd->autoneg != AUTONEG_ENABLE &&
2498 (jme->mii_if.full_duplex != ecmd->duplex))
2501 spin_lock_bh(&jme->phy_lock);
2502 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2503 spin_unlock_bh(&jme->phy_lock);
2506 jme_reset_link(jme);
2509 set_bit(JME_FLAG_SSET, &jme->flags);
2510 jme->old_ecmd = *ecmd;
2517 jme_get_link(struct net_device *netdev)
2519 struct jme_adapter *jme = netdev_priv(netdev);
2520 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2524 jme_get_msglevel(struct net_device *netdev)
2526 struct jme_adapter *jme = netdev_priv(netdev);
2527 return jme->msg_enable;
2531 jme_set_msglevel(struct net_device *netdev, u32 value)
2533 struct jme_adapter *jme = netdev_priv(netdev);
2534 jme->msg_enable = value;
2538 jme_get_rx_csum(struct net_device *netdev)
2540 struct jme_adapter *jme = netdev_priv(netdev);
2541 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2545 jme_set_rx_csum(struct net_device *netdev, u32 on)
2547 struct jme_adapter *jme = netdev_priv(netdev);
2549 spin_lock_bh(&jme->rxmcs_lock);
2551 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2553 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2554 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2555 spin_unlock_bh(&jme->rxmcs_lock);
2561 jme_set_tx_csum(struct net_device *netdev, u32 on)
2563 struct jme_adapter *jme = netdev_priv(netdev);
2566 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2567 if (netdev->mtu <= 1900)
2568 netdev->features |= NETIF_F_HW_CSUM;
2570 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2571 netdev->features &= ~NETIF_F_HW_CSUM;
2578 jme_set_tso(struct net_device *netdev, u32 on)
2580 struct jme_adapter *jme = netdev_priv(netdev);
2583 set_bit(JME_FLAG_TSO, &jme->flags);
2584 if (netdev->mtu <= 1900)
2585 netdev->features |= NETIF_F_TSO
2591 clear_bit(JME_FLAG_TSO, &jme->flags);
2592 netdev->features &= ~(NETIF_F_TSO
2603 jme_nway_reset(struct net_device *netdev)
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 jme_restart_an(jme);
2611 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2616 val = jread32(jme, JME_SMBCSR);
2617 to = JME_SMB_BUSY_TIMEOUT;
2618 while ((val & SMBCSR_BUSY) && --to) {
2620 val = jread32(jme, JME_SMBCSR);
2623 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2627 jwrite32(jme, JME_SMBINTF,
2628 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2629 SMBINTF_HWRWN_READ |
2632 val = jread32(jme, JME_SMBINTF);
2633 to = JME_SMB_BUSY_TIMEOUT;
2634 while ((val & SMBINTF_HWCMD) && --to) {
2636 val = jread32(jme, JME_SMBINTF);
2639 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2643 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2647 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2652 val = jread32(jme, JME_SMBCSR);
2653 to = JME_SMB_BUSY_TIMEOUT;
2654 while ((val & SMBCSR_BUSY) && --to) {
2656 val = jread32(jme, JME_SMBCSR);
2659 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2663 jwrite32(jme, JME_SMBINTF,
2664 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2665 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2666 SMBINTF_HWRWN_WRITE |
2669 val = jread32(jme, JME_SMBINTF);
2670 to = JME_SMB_BUSY_TIMEOUT;
2671 while ((val & SMBINTF_HWCMD) && --to) {
2673 val = jread32(jme, JME_SMBINTF);
2676 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2684 jme_get_eeprom_len(struct net_device *netdev)
2686 struct jme_adapter *jme = netdev_priv(netdev);
2688 val = jread32(jme, JME_SMBCSR);
2689 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2693 jme_get_eeprom(struct net_device *netdev,
2694 struct ethtool_eeprom *eeprom, u8 *data)
2696 struct jme_adapter *jme = netdev_priv(netdev);
2697 int i, offset = eeprom->offset, len = eeprom->len;
2700 * ethtool will check the boundary for us
2702 eeprom->magic = JME_EEPROM_MAGIC;
2703 for (i = 0 ; i < len ; ++i)
2704 data[i] = jme_smb_read(jme, i + offset);
2710 jme_set_eeprom(struct net_device *netdev,
2711 struct ethtool_eeprom *eeprom, u8 *data)
2713 struct jme_adapter *jme = netdev_priv(netdev);
2714 int i, offset = eeprom->offset, len = eeprom->len;
2716 if (eeprom->magic != JME_EEPROM_MAGIC)
2720 * ethtool will check the boundary for us
2722 for (i = 0 ; i < len ; ++i)
2723 jme_smb_write(jme, i + offset, data[i]);
2728 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2729 static struct ethtool_ops jme_ethtool_ops = {
2731 static const struct ethtool_ops jme_ethtool_ops = {
2733 .get_drvinfo = jme_get_drvinfo,
2734 .get_regs_len = jme_get_regs_len,
2735 .get_regs = jme_get_regs,
2736 .get_coalesce = jme_get_coalesce,
2737 .set_coalesce = jme_set_coalesce,
2738 .get_pauseparam = jme_get_pauseparam,
2739 .set_pauseparam = jme_set_pauseparam,
2740 .get_wol = jme_get_wol,
2741 .set_wol = jme_set_wol,
2742 .get_settings = jme_get_settings,
2743 .set_settings = jme_set_settings,
2744 .get_link = jme_get_link,
2745 .get_msglevel = jme_get_msglevel,
2746 .set_msglevel = jme_set_msglevel,
2747 .get_rx_csum = jme_get_rx_csum,
2748 .set_rx_csum = jme_set_rx_csum,
2749 .set_tx_csum = jme_set_tx_csum,
2750 .set_tso = jme_set_tso,
2751 .set_sg = ethtool_op_set_sg,
2752 .nway_reset = jme_nway_reset,
2753 .get_eeprom_len = jme_get_eeprom_len,
2754 .get_eeprom = jme_get_eeprom,
2755 .set_eeprom = jme_set_eeprom,
2759 jme_pci_dma64(struct pci_dev *pdev)
2761 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2762 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2763 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2765 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2768 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2769 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2771 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2775 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2776 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2777 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2779 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2782 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2783 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2785 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2789 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2790 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2791 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2793 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2794 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2802 jme_phy_init(struct jme_adapter *jme)
2806 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2807 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2811 jme_check_hw_ver(struct jme_adapter *jme)
2815 chipmode = jread32(jme, JME_CHIPMODE);
2817 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2818 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2821 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2822 static const struct net_device_ops jme_netdev_ops = {
2823 .ndo_open = jme_open,
2824 .ndo_stop = jme_close,
2825 .ndo_validate_addr = eth_validate_addr,
2826 .ndo_start_xmit = jme_start_xmit,
2827 .ndo_set_mac_address = jme_set_macaddr,
2828 .ndo_set_multicast_list = jme_set_multi,
2829 .ndo_change_mtu = jme_change_mtu,
2830 .ndo_tx_timeout = jme_tx_timeout,
2831 .ndo_vlan_rx_register = jme_vlan_rx_register,
2835 static int __devinit
2836 jme_init_one(struct pci_dev *pdev,
2837 const struct pci_device_id *ent)
2839 int rc = 0, using_dac, i;
2840 struct net_device *netdev;
2841 struct jme_adapter *jme;
2846 * set up PCI device basics
2848 rc = pci_enable_device(pdev);
2850 pr_err("Cannot enable PCI device\n");
2854 using_dac = jme_pci_dma64(pdev);
2855 if (using_dac < 0) {
2856 pr_err("Cannot set PCI DMA Mask\n");
2858 goto err_out_disable_pdev;
2861 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2862 pr_err("No PCI resource region found\n");
2864 goto err_out_disable_pdev;
2867 rc = pci_request_regions(pdev, DRV_NAME);
2869 pr_err("Cannot obtain PCI resource region\n");
2870 goto err_out_disable_pdev;
2873 pci_set_master(pdev);
2876 * alloc and init net device
2878 netdev = alloc_etherdev(sizeof(*jme));
2880 pr_err("Cannot allocate netdev structure\n");
2882 goto err_out_release_regions;
2884 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2885 netdev->netdev_ops = &jme_netdev_ops;
2887 netdev->open = jme_open;
2888 netdev->stop = jme_close;
2889 netdev->hard_start_xmit = jme_start_xmit;
2890 netdev->set_mac_address = jme_set_macaddr;
2891 netdev->set_multicast_list = jme_set_multi;
2892 netdev->change_mtu = jme_change_mtu;
2893 netdev->tx_timeout = jme_tx_timeout;
2894 netdev->vlan_rx_register = jme_vlan_rx_register;
2895 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2896 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2898 NETDEV_GET_STATS(netdev, &jme_get_stats);
2900 netdev->ethtool_ops = &jme_ethtool_ops;
2901 netdev->watchdog_timeo = TX_TIMEOUT;
2902 netdev->features = NETIF_F_HW_CSUM |
2908 NETIF_F_HW_VLAN_TX |
2911 netdev->features |= NETIF_F_HIGHDMA;
2913 SET_NETDEV_DEV(netdev, &pdev->dev);
2914 pci_set_drvdata(pdev, netdev);
2919 jme = netdev_priv(netdev);
2922 jme->jme_rx = netif_rx;
2923 jme->jme_vlan_rx = vlan_hwaccel_rx;
2924 jme->old_mtu = netdev->mtu = 1500;
2926 jme->tx_ring_size = 1 << 10;
2927 jme->tx_ring_mask = jme->tx_ring_size - 1;
2928 jme->tx_wake_threshold = 1 << 9;
2929 jme->rx_ring_size = 1 << 9;
2930 jme->rx_ring_mask = jme->rx_ring_size - 1;
2931 jme->msg_enable = JME_DEF_MSG_ENABLE;
2932 jme->regs = ioremap(pci_resource_start(pdev, 0),
2933 pci_resource_len(pdev, 0));
2935 pr_err("Mapping PCI resource region error\n");
2937 goto err_out_free_netdev;
2941 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2942 jwrite32(jme, JME_APMC, apmc);
2943 } else if (force_pseudohp) {
2944 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2945 jwrite32(jme, JME_APMC, apmc);
2948 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2950 spin_lock_init(&jme->phy_lock);
2951 spin_lock_init(&jme->macaddr_lock);
2952 spin_lock_init(&jme->rxmcs_lock);
2954 atomic_set(&jme->link_changing, 1);
2955 atomic_set(&jme->rx_cleaning, 1);
2956 atomic_set(&jme->tx_cleaning, 1);
2957 atomic_set(&jme->rx_empty, 1);
2959 tasklet_init(&jme->pcc_task,
2961 (unsigned long) jme);
2962 tasklet_init(&jme->linkch_task,
2963 jme_link_change_tasklet,
2964 (unsigned long) jme);
2965 tasklet_init(&jme->txclean_task,
2966 jme_tx_clean_tasklet,
2967 (unsigned long) jme);
2968 tasklet_init(&jme->rxclean_task,
2969 jme_rx_clean_tasklet,
2970 (unsigned long) jme);
2971 tasklet_init(&jme->rxempty_task,
2972 jme_rx_empty_tasklet,
2973 (unsigned long) jme);
2974 tasklet_disable_nosync(&jme->linkch_task);
2975 tasklet_disable_nosync(&jme->txclean_task);
2976 tasklet_disable_nosync(&jme->rxclean_task);
2977 tasklet_disable_nosync(&jme->rxempty_task);
2978 jme->dpi.cur = PCC_P1;
2981 jme->reg_rxcs = RXCS_DEFAULT;
2982 jme->reg_rxmcs = RXMCS_DEFAULT;
2984 jme->reg_pmcs = PMCS_MFEN;
2985 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2986 set_bit(JME_FLAG_TSO, &jme->flags);
2989 * Get Max Read Req Size from PCI Config Space
2991 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2992 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2993 switch (jme->mrrs) {
2995 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2998 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3001 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3006 * Must check before reset_mac_processor
3008 jme_check_hw_ver(jme);
3009 jme->mii_if.dev = netdev;
3011 jme->mii_if.phy_id = 0;
3012 for (i = 1 ; i < 32 ; ++i) {
3013 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3014 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3015 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3016 jme->mii_if.phy_id = i;
3021 if (!jme->mii_if.phy_id) {
3023 pr_err("Can not find phy_id\n");
3027 jme->reg_ghc |= GHC_LINK_POLL;
3029 jme->mii_if.phy_id = 1;
3031 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3032 jme->mii_if.supports_gmii = true;
3034 jme->mii_if.supports_gmii = false;
3035 jme->mii_if.mdio_read = jme_mdio_read;
3036 jme->mii_if.mdio_write = jme_mdio_write;
3039 jme_set_phyfifoa(jme);
3040 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
3046 * Reset MAC processor and reload EEPROM for MAC Address
3048 jme_reset_mac_processor(jme);
3049 rc = jme_reload_eeprom(jme);
3051 pr_err("Reload eeprom for reading MAC Address error\n");
3054 jme_load_macaddr(netdev);
3057 * Tell stack that we are not ready to work until open()
3059 netif_carrier_off(netdev);
3060 netif_stop_queue(netdev);
3065 rc = register_netdev(netdev);
3067 pr_err("Cannot register net device\n");
3071 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x "
3072 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3073 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3074 "JMC250 Gigabit Ethernet" :
3075 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3076 "JMC260 Fast Ethernet" : "Unknown",
3077 (jme->fpgaver != 0) ? " (FPGA)" : "",
3078 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3080 netdev->dev_addr[0],
3081 netdev->dev_addr[1],
3082 netdev->dev_addr[2],
3083 netdev->dev_addr[3],
3084 netdev->dev_addr[4],
3085 netdev->dev_addr[5]);
3091 err_out_free_netdev:
3092 pci_set_drvdata(pdev, NULL);
3093 free_netdev(netdev);
3094 err_out_release_regions:
3095 pci_release_regions(pdev);
3096 err_out_disable_pdev:
3097 pci_disable_device(pdev);
3102 static void __devexit
3103 jme_remove_one(struct pci_dev *pdev)
3105 struct net_device *netdev = pci_get_drvdata(pdev);
3106 struct jme_adapter *jme = netdev_priv(netdev);
3108 unregister_netdev(netdev);
3110 pci_set_drvdata(pdev, NULL);
3111 free_netdev(netdev);
3112 pci_release_regions(pdev);
3113 pci_disable_device(pdev);
3119 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3121 struct net_device *netdev = pci_get_drvdata(pdev);
3122 struct jme_adapter *jme = netdev_priv(netdev);
3124 atomic_dec(&jme->link_changing);
3126 netif_device_detach(netdev);
3127 netif_stop_queue(netdev);
3130 tasklet_disable(&jme->txclean_task);
3131 tasklet_disable(&jme->rxclean_task);
3132 tasklet_disable(&jme->rxempty_task);
3134 if (netif_carrier_ok(netdev)) {
3135 if (test_bit(JME_FLAG_POLL, &jme->flags))
3136 jme_polling_mode(jme);
3138 jme_stop_pcc_timer(jme);
3139 jme_reset_ghc_speed(jme);
3140 jme_disable_rx_engine(jme);
3141 jme_disable_tx_engine(jme);
3142 jme_reset_mac_processor(jme);
3143 jme_free_rx_resources(jme);
3144 jme_free_tx_resources(jme);
3145 netif_carrier_off(netdev);
3149 tasklet_enable(&jme->txclean_task);
3150 tasklet_hi_enable(&jme->rxclean_task);
3151 tasklet_hi_enable(&jme->rxempty_task);
3153 pci_save_state(pdev);
3154 if (jme->reg_pmcs) {
3155 jme_set_100m_half(jme);
3157 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3160 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3162 pci_enable_wake(pdev, PCI_D3cold, true);
3166 pci_set_power_state(pdev, PCI_D3cold);
3172 jme_resume(struct pci_dev *pdev)
3174 struct net_device *netdev = pci_get_drvdata(pdev);
3175 struct jme_adapter *jme = netdev_priv(netdev);
3178 pci_restore_state(pdev);
3180 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3182 jme_set_settings(netdev, &jme->old_ecmd);
3184 jme_reset_phy_processor(jme);
3188 netif_device_attach(netdev);
3190 atomic_inc(&jme->link_changing);
3192 jme_reset_link(jme);
3198 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3199 static struct pci_device_id jme_pci_tbl[] = {
3201 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3203 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3204 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3208 static struct pci_driver jme_driver = {
3210 .id_table = jme_pci_tbl,
3211 .probe = jme_init_one,
3212 .remove = __devexit_p(jme_remove_one),
3214 .suspend = jme_suspend,
3215 .resume = jme_resume,
3216 #endif /* CONFIG_PM */
3220 jme_init_module(void)
3222 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3223 return pci_register_driver(&jme_driver);
3227 jme_cleanup_module(void)
3229 pci_unregister_driver(&jme_driver);
3232 module_init(jme_init_module);
3233 module_exit(jme_cleanup_module);
3235 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3236 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3237 MODULE_LICENSE("GPL");
3238 MODULE_VERSION(DRV_VERSION);
3239 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);