2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * - Decode register dump for ethtool.
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
48 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
49 static struct net_device_stats *
50 jme_get_stats(struct net_device *netdev)
52 struct jme_adapter *jme = netdev_priv(netdev);
58 jme_mdio_read(struct net_device *netdev, int phy, int reg)
60 struct jme_adapter *jme = netdev_priv(netdev);
63 jwrite32(jme, JME_SMI, SMI_OP_REQ |
68 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
70 val = jread32(jme, JME_SMI);
71 if ((val & SMI_OP_REQ) == 0)
76 jeprintk("jme", "phy(%d) read timeout : %d\n", phy, reg);
80 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
84 jme_mdio_write(struct net_device *netdev,
85 int phy, int reg, int val)
87 struct jme_adapter *jme = netdev_priv(netdev);
90 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
91 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
92 smi_phy_addr(phy) | smi_reg_addr(reg));
95 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
97 val = jread32(jme, JME_SMI);
98 if ((val & SMI_OP_REQ) == 0)
103 jeprintk("jme", "phy(%d) write timeout : %d\n", phy, reg);
108 __always_inline static void
109 jme_reset_phy_processor(struct jme_adapter *jme)
113 jme_mdio_write(jme->dev,
115 MII_ADVERTISE, ADVERTISE_ALL |
116 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118 jme_mdio_write(jme->dev,
121 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
123 val = jme_mdio_read(jme->dev,
127 jme_mdio_write(jme->dev,
129 MII_BMCR, val | BMCR_RESET);
135 jme_setup_wakeup_frame(struct jme_adapter *jme,
136 __u32 *mask, __u32 crc, int fnr)
143 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
145 jwrite32(jme, JME_WFODP, crc);
151 for(i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
152 jwrite32(jme, JME_WFOI,
153 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
154 (fnr & WFOI_FRAME_SEL));
156 jwrite32(jme, JME_WFODP, mask[i]);
161 __always_inline static void
162 jme_reset_mac_processor(struct jme_adapter *jme)
164 __u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0,0,0,0};
165 __u32 crc = 0xCDCDCDCD;
169 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
171 jwrite32(jme, JME_GHC, jme->reg_ghc);
172 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
173 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
174 for(i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
175 jme_setup_wakeup_frame(jme, mask, crc, i);
177 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
179 gpreg0 = GPREG0_DEFAULT;
180 jwrite32(jme, JME_GPREG0, gpreg0);
181 jwrite32(jme, JME_GPREG1, 0);
184 __always_inline static void
185 jme_clear_pm(struct jme_adapter *jme)
187 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
188 pci_set_power_state(jme->pdev, PCI_D0);
189 pci_enable_wake(jme->pdev, PCI_D0, false);
193 jme_reload_eeprom(struct jme_adapter *jme)
198 val = jread32(jme, JME_SMBCSR);
200 if(val & SMBCSR_EEPROMD)
203 jwrite32(jme, JME_SMBCSR, val);
204 val |= SMBCSR_RELOAD;
205 jwrite32(jme, JME_SMBCSR, val);
208 for (i = JME_SMB_TIMEOUT; i > 0; --i)
211 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
216 jeprintk(jme->dev->name, "eeprom reload timeout\n");
227 jme_load_macaddr(struct net_device *netdev)
229 struct jme_adapter *jme = netdev_priv(netdev);
230 unsigned char macaddr[6];
233 spin_lock(&jme->macaddr_lock);
234 val = jread32(jme, JME_RXUMA_LO);
235 macaddr[0] = (val >> 0) & 0xFF;
236 macaddr[1] = (val >> 8) & 0xFF;
237 macaddr[2] = (val >> 16) & 0xFF;
238 macaddr[3] = (val >> 24) & 0xFF;
239 val = jread32(jme, JME_RXUMA_HI);
240 macaddr[4] = (val >> 0) & 0xFF;
241 macaddr[5] = (val >> 8) & 0xFF;
242 memcpy(netdev->dev_addr, macaddr, 6);
243 spin_unlock(&jme->macaddr_lock);
246 __always_inline static void
247 jme_set_rx_pcc(struct jme_adapter *jme, int p)
251 jwrite32(jme, JME_PCCRX0,
252 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
253 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 jwrite32(jme, JME_PCCRX0,
257 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
258 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
261 jwrite32(jme, JME_PCCRX0,
262 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
263 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
275 if(!(jme->flags & JME_FLAG_POLL))
276 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
280 jme_start_irq(struct jme_adapter *jme)
282 register struct dynpcc_info *dpi = &(jme->dpi);
284 jme_set_rx_pcc(jme, PCC_P1);
286 dpi->attempt = PCC_P1;
289 jwrite32(jme, JME_PCCTX,
290 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
291 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
298 jwrite32(jme, JME_IENS, INTR_ENABLE);
301 __always_inline static void
302 jme_stop_irq(struct jme_adapter *jme)
307 jwrite32(jme, JME_IENC, INTR_ENABLE);
311 __always_inline static void
312 jme_enable_shadow(struct jme_adapter *jme)
316 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
319 __always_inline static void
320 jme_disable_shadow(struct jme_adapter *jme)
322 jwrite32(jme, JME_SHBA_LO, 0x0);
326 jme_linkstat_from_phy(struct jme_adapter *jme)
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if(bmsr & BMCR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
339 jme_check_link(struct net_device *netdev, int testonly)
341 struct jme_adapter *jme = netdev_priv(netdev);
342 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
349 phylink = jme_linkstat_from_phy(jme);
351 phylink = jread32(jme, JME_PHY_LINK);
353 if (phylink & PHY_LINK_UP) {
354 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
356 * If we did not enable AN
357 * Speed/Duplex Info should be obtained from SMI
359 phylink = PHY_LINK_UP;
361 bmcr = jme_mdio_read(jme->dev,
366 phylink |= ((bmcr & BMCR_SPEED1000) &&
367 (bmcr & BMCR_SPEED100) == 0) ?
368 PHY_LINK_SPEED_1000M :
369 (bmcr & BMCR_SPEED100) ?
370 PHY_LINK_SPEED_100M :
373 phylink |= (bmcr & BMCR_FULLDPLX) ?
376 strcat(linkmsg, "Forced: ");
380 * Keep polling for speed/duplex resolve complete
382 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
388 phylink = jme_linkstat_from_phy(jme);
390 phylink = jread32(jme, JME_PHY_LINK);
394 jeprintk(netdev->name,
395 "Waiting speed resolve timeout.\n");
397 strcat(linkmsg, "ANed: ");
400 if(jme->phylink == phylink) {
407 jme->phylink = phylink;
409 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
413 switch(phylink & PHY_LINK_SPEED_MASK) {
414 case PHY_LINK_SPEED_10M:
415 ghc |= GHC_SPEED_10M;
416 strcat(linkmsg, "10 Mbps, ");
418 case PHY_LINK_SPEED_100M:
419 ghc |= GHC_SPEED_100M;
420 strcat(linkmsg, "100 Mbps, ");
422 case PHY_LINK_SPEED_1000M:
423 ghc |= GHC_SPEED_1000M;
424 strcat(linkmsg, "1000 Mbps, ");
429 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
431 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
435 if(phylink & PHY_LINK_MDI_STAT)
436 strcat(linkmsg, "MDI-X");
438 strcat(linkmsg, "MDI");
440 if(phylink & PHY_LINK_DUPLEX)
441 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
447 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
448 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
454 jwrite32(jme, JME_GHC, ghc);
456 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
457 netif_carrier_on(netdev);
463 jprintk(netdev->name, "Link is down.\n");
465 netif_carrier_off(netdev);
473 jme_setup_tx_resources(struct jme_adapter *jme)
475 struct jme_ring *txring = &(jme->txring[0]);
477 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
478 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
484 txring->dmaalloc = 0;
492 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
494 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
495 txring->next_to_use = 0;
496 atomic_set(&txring->next_to_clean, 0);
497 atomic_set(&txring->nr_free, jme->tx_ring_size);
500 * Initialize Transmit Descriptors
502 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
503 memset(txring->bufinf, 0,
504 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
510 jme_free_tx_resources(struct jme_adapter *jme)
513 struct jme_ring *txring = &(jme->txring[0]);
514 struct jme_buffer_info *txbi = txring->bufinf;
517 for(i = 0 ; i < jme->tx_ring_size ; ++i) {
518 txbi = txring->bufinf + i;
520 dev_kfree_skb(txbi->skb);
528 dma_free_coherent(&(jme->pdev->dev),
529 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
533 txring->alloc = NULL;
535 txring->dmaalloc = 0;
538 txring->next_to_use = 0;
539 atomic_set(&txring->next_to_clean, 0);
540 atomic_set(&txring->nr_free, 0);
544 __always_inline static void
545 jme_enable_tx_engine(struct jme_adapter *jme)
550 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
553 * Setup TX Queue 0 DMA Bass Address
555 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
556 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
557 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
560 * Setup TX Descptor Count
562 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
568 jwrite32(jme, JME_TXCS, jme->reg_txcs |
574 __always_inline static void
575 jme_restart_tx_engine(struct jme_adapter *jme)
580 jwrite32(jme, JME_TXCS, jme->reg_txcs |
585 __always_inline static void
586 jme_disable_tx_engine(struct jme_adapter *jme)
594 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
596 val = jread32(jme, JME_TXCS);
597 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
600 val = jread32(jme, JME_TXCS);
604 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
605 jme_reset_mac_processor(jme);
612 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
614 struct jme_ring *rxring = jme->rxring;
615 register volatile struct rxdesc* rxdesc = rxring->desc;
616 struct jme_buffer_info *rxbi = rxring->bufinf;
622 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
623 rxdesc->desc1.bufaddrl = cpu_to_le32(
624 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
625 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
626 if(jme->dev->features & NETIF_F_HIGHDMA)
627 rxdesc->desc1.flags = RXFLAG_64BIT;
629 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
633 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
635 struct jme_ring *rxring = &(jme->rxring[0]);
636 struct jme_buffer_info *rxbi = rxring->bufinf + i;
637 unsigned long offset;
640 skb = netdev_alloc_skb(jme->dev,
641 jme->dev->mtu + RX_EXTRA_LEN);
646 (unsigned long)(skb->data)
647 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
648 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
651 rxbi->len = skb_tailroom(skb);
652 rxbi->mapping = pci_map_page(jme->pdev,
653 virt_to_page(skb->data),
654 offset_in_page(skb->data),
662 jme_free_rx_buf(struct jme_adapter *jme, int i)
664 struct jme_ring *rxring = &(jme->rxring[0]);
665 struct jme_buffer_info *rxbi = rxring->bufinf;
669 pci_unmap_page(jme->pdev,
673 dev_kfree_skb(rxbi->skb);
681 jme_free_rx_resources(struct jme_adapter *jme)
684 struct jme_ring *rxring = &(jme->rxring[0]);
687 for(i = 0 ; i < jme->rx_ring_size ; ++i)
688 jme_free_rx_buf(jme, i);
690 dma_free_coherent(&(jme->pdev->dev),
691 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
694 rxring->alloc = NULL;
696 rxring->dmaalloc = 0;
699 rxring->next_to_use = 0;
700 atomic_set(&rxring->next_to_clean, 0);
704 jme_setup_rx_resources(struct jme_adapter *jme)
707 struct jme_ring *rxring = &(jme->rxring[0]);
709 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
710 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
715 rxring->dmaalloc = 0;
723 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
725 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
726 rxring->next_to_use = 0;
727 atomic_set(&rxring->next_to_clean, 0);
730 * Initiallize Receive Descriptors
732 for(i = 0 ; i < jme->rx_ring_size ; ++i) {
733 if(unlikely(jme_make_new_rx_buf(jme, i))) {
734 jme_free_rx_resources(jme);
738 jme_set_clean_rxdesc(jme, i);
744 __always_inline static void
745 jme_enable_rx_engine(struct jme_adapter *jme)
748 * Setup RX DMA Bass Address
750 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
751 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
752 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
755 * Setup RX Descriptor Count
757 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
760 * Setup Unicast Filter
762 jme_set_multi(jme->dev);
768 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
774 __always_inline static void
775 jme_restart_rx_engine(struct jme_adapter *jme)
780 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
787 __always_inline static void
788 jme_disable_rx_engine(struct jme_adapter *jme)
796 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
798 val = jread32(jme, JME_RXCS);
799 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
802 val = jread32(jme, JME_RXCS);
806 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
811 jme_rxsum_ok(struct jme_adapter *jme, __u16 flags)
813 if(!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
816 if(unlikely((flags & RXWBFLAG_TCPON) &&
817 !(flags & RXWBFLAG_TCPCS))) {
818 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
822 if(unlikely((flags & RXWBFLAG_UDPON) &&
823 !(flags & RXWBFLAG_UDPCS))) {
824 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
828 if(unlikely((flags & RXWBFLAG_IPV4) &&
829 !(flags & RXWBFLAG_IPCS))) {
830 csum_dbg(jme->dev->name, "IPv4 Checksum error.\n");
837 csum_dbg(jme->dev->name, "%s%s%s%s\n",
838 (flags & RXWBFLAG_IPV4)?"IPv4 ":"",
839 (flags & RXWBFLAG_IPV6)?"IPv6 ":"",
840 (flags & RXWBFLAG_UDPON)?"UDP ":"",
841 (flags & RXWBFLAG_TCPON)?"TCP":"");
846 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
848 struct jme_ring *rxring = &(jme->rxring[0]);
849 volatile struct rxdesc *rxdesc = rxring->desc;
850 struct jme_buffer_info *rxbi = rxring->bufinf;
858 pci_dma_sync_single_for_cpu(jme->pdev,
863 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
864 pci_dma_sync_single_for_device(jme->pdev,
869 ++(NET_STAT(jme).rx_dropped);
872 framesize = le16_to_cpu(rxdesc->descwb.framesize)
875 skb_reserve(skb, RX_PREPAD_SIZE);
876 skb_put(skb, framesize);
877 skb->protocol = eth_type_trans(skb, jme->dev);
879 if(jme_rxsum_ok(jme, rxdesc->descwb.flags))
880 skb->ip_summed = CHECKSUM_UNNECESSARY;
882 skb->ip_summed = CHECKSUM_NONE;
885 if(rxdesc->descwb.flags & RXWBFLAG_TAGON) {
886 vlan_dbg(jme->dev->name, "VLAN: %04x\n",
887 rxdesc->descwb.vlan);
889 vlan_dbg(jme->dev->name,
890 "VLAN Passed to kernel.\n");
891 jme->jme_vlan_rx(skb, jme->vlgrp,
892 le32_to_cpu(rxdesc->descwb.vlan));
893 NET_STAT(jme).rx_bytes += 4;
900 if((le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST) ==
902 ++(NET_STAT(jme).multicast);
904 jme->dev->last_rx = jiffies;
905 NET_STAT(jme).rx_bytes += framesize;
906 ++(NET_STAT(jme).rx_packets);
909 jme_set_clean_rxdesc(jme, idx);
916 jme_process_receive(struct jme_adapter *jme, int limit)
918 struct jme_ring *rxring = &(jme->rxring[0]);
919 volatile struct rxdesc *rxdesc = rxring->desc;
920 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
922 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
925 if(unlikely(atomic_read(&jme->link_changing) != 1))
928 if(unlikely(!netif_carrier_ok(jme->dev)))
931 i = atomic_read(&rxring->next_to_clean);
934 rxdesc = rxring->desc;
937 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
938 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
941 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
943 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
945 if(unlikely(desccnt > 1 ||
946 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
948 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
949 ++(NET_STAT(jme).rx_crc_errors);
950 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
951 ++(NET_STAT(jme).rx_fifo_errors);
953 ++(NET_STAT(jme).rx_errors);
956 rx_dbg(jme->dev->name,
957 "RX: More than one(%d) descriptor, "
959 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
960 limit -= desccnt - 1;
963 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
964 jme_set_clean_rxdesc(jme, j);
965 j = (j + 1) & (mask);
970 jme_alloc_and_feed_skb(jme, i);
973 i = (i + desccnt) & (mask);
978 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
979 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
980 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
983 atomic_set(&rxring->next_to_clean, i);
986 atomic_inc(&jme->rx_cleaning);
988 return limit > 0 ? limit : 0;
993 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
995 if(likely(atmp == dpi->cur)) {
1000 if(dpi->attempt == atmp) {
1004 dpi->attempt = atmp;
1011 jme_dynamic_pcc(struct jme_adapter *jme)
1013 register struct dynpcc_info *dpi = &(jme->dpi);
1015 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1016 jme_attempt_pcc(dpi, PCC_P3);
1017 else if((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1018 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1019 jme_attempt_pcc(dpi, PCC_P2);
1021 jme_attempt_pcc(dpi, PCC_P1);
1023 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1024 jme_set_rx_pcc(jme, dpi->attempt);
1025 dpi->cur = dpi->attempt;
1031 jme_start_pcc_timer(struct jme_adapter *jme)
1033 struct dynpcc_info *dpi = &(jme->dpi);
1034 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1035 dpi->last_pkts = NET_STAT(jme).rx_packets;
1037 jwrite32(jme, JME_TMCSR,
1038 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1041 __always_inline static void
1042 jme_stop_pcc_timer(struct jme_adapter *jme)
1044 jwrite32(jme, JME_TMCSR, 0);
1048 jme_pcc_tasklet(unsigned long arg)
1050 struct jme_adapter *jme = (struct jme_adapter*)arg;
1051 struct net_device *netdev = jme->dev;
1054 if(unlikely(!netif_carrier_ok(netdev) ||
1055 (atomic_read(&jme->link_changing) != 1)
1057 jme_stop_pcc_timer(jme);
1061 if(!(jme->flags & JME_FLAG_POLL))
1062 jme_dynamic_pcc(jme);
1064 jme_start_pcc_timer(jme);
1067 __always_inline static void
1068 jme_polling_mode(struct jme_adapter *jme)
1070 jme_set_rx_pcc(jme, PCC_OFF);
1073 __always_inline static void
1074 jme_interrupt_mode(struct jme_adapter *jme)
1076 jme_set_rx_pcc(jme, PCC_P1);
1080 jme_link_change_tasklet(unsigned long arg)
1082 struct jme_adapter *jme = (struct jme_adapter*)arg;
1083 struct net_device *netdev = jme->dev;
1084 int timeout = WAIT_TASKLET_TIMEOUT;
1087 if(!atomic_dec_and_test(&jme->link_changing))
1090 if(jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1093 jme->old_mtu = netdev->mtu;
1094 netif_stop_queue(netdev);
1096 while(--timeout > 0 &&
1098 atomic_read(&jme->rx_cleaning) != 1 ||
1099 atomic_read(&jme->tx_cleaning) != 1
1105 if(netif_carrier_ok(netdev)) {
1106 jme_stop_pcc_timer(jme);
1107 jme_reset_mac_processor(jme);
1108 jme_free_rx_resources(jme);
1109 jme_free_tx_resources(jme);
1111 if(jme->flags & JME_FLAG_POLL)
1112 jme_polling_mode(jme);
1115 jme_check_link(netdev, 0);
1116 if(netif_carrier_ok(netdev)) {
1117 rc = jme_setup_rx_resources(jme);
1119 jeprintk(netdev->name,
1120 "Allocating resources for RX error"
1121 ", Device STOPPED!\n");
1126 rc = jme_setup_tx_resources(jme);
1128 jeprintk(netdev->name,
1129 "Allocating resources for TX error"
1130 ", Device STOPPED!\n");
1131 goto err_out_free_rx_resources;
1134 jme_enable_rx_engine(jme);
1135 jme_enable_tx_engine(jme);
1137 netif_start_queue(netdev);
1139 if(jme->flags & JME_FLAG_POLL)
1140 jme_interrupt_mode(jme);
1142 jme_start_pcc_timer(jme);
1147 err_out_free_rx_resources:
1148 jme_free_rx_resources(jme);
1150 atomic_inc(&jme->link_changing);
1154 jme_rx_clean_tasklet(unsigned long arg)
1156 struct jme_adapter *jme = (struct jme_adapter*)arg;
1157 struct dynpcc_info *dpi = &(jme->dpi);
1159 jme_process_receive(jme, jme->rx_ring_size);
1165 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1167 struct jme_adapter *jme = jme_napi_priv(holder);
1168 struct net_device *netdev = jme->dev;
1171 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1173 while(atomic_read(&jme->rx_empty) > 0) {
1174 atomic_dec(&jme->rx_empty);
1175 ++(NET_STAT(jme).rx_dropped);
1176 jme_restart_rx_engine(jme);
1178 atomic_inc(&jme->rx_empty);
1181 JME_RX_COMPLETE(netdev, holder);
1182 jme_interrupt_mode(jme);
1185 JME_NAPI_WEIGHT_SET(budget, rest);
1186 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1190 jme_rx_empty_tasklet(unsigned long arg)
1192 struct jme_adapter *jme = (struct jme_adapter*)arg;
1194 if(unlikely(atomic_read(&jme->link_changing) != 1))
1197 if(unlikely(!netif_carrier_ok(jme->dev)))
1200 queue_dbg(jme->dev->name, "RX Queue Full!\n");
1202 jme_rx_clean_tasklet(arg);
1204 while(atomic_read(&jme->rx_empty) > 0) {
1205 atomic_dec(&jme->rx_empty);
1206 ++(NET_STAT(jme).rx_dropped);
1207 jme_restart_rx_engine(jme);
1209 atomic_inc(&jme->rx_empty);
1213 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1215 struct jme_ring *txring = jme->txring;
1218 if(unlikely(netif_queue_stopped(jme->dev) &&
1219 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1221 queue_dbg(jme->dev->name, "TX Queue Waked.\n");
1222 netif_wake_queue(jme->dev);
1229 jme_tx_clean_tasklet(unsigned long arg)
1231 struct jme_adapter *jme = (struct jme_adapter*)arg;
1232 struct jme_ring *txring = &(jme->txring[0]);
1233 volatile struct txdesc *txdesc = txring->desc;
1234 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1235 int i, j, cnt = 0, max, err, mask;
1237 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1240 if(unlikely(atomic_read(&jme->link_changing) != 1))
1243 if(unlikely(!netif_carrier_ok(jme->dev)))
1246 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1247 mask = jme->tx_ring_mask;
1249 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1251 for(i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1255 if(likely(ctxbi->skb &&
1256 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1258 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1260 tx_dbg(jme->dev->name,
1261 "Tx Tasklet: Clean %d+%d\n",
1264 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1265 ttxbi = txbi + ((i + j) & (mask));
1266 txdesc[(i + j) & (mask)].dw[0] = 0;
1268 pci_unmap_page(jme->pdev,
1277 dev_kfree_skb(ctxbi->skb);
1279 cnt += ctxbi->nr_desc;
1282 ++(NET_STAT(jme).tx_carrier_errors);
1284 ++(NET_STAT(jme).tx_packets);
1285 NET_STAT(jme).tx_bytes += ctxbi->len;
1290 ctxbi->start_xmit = 0;
1294 tx_dbg(jme->dev->name,
1296 " Stopped due to no skb.\n");
1298 tx_dbg(jme->dev->name,
1300 "Stopped due to not done.\n");
1304 i = (i + ctxbi->nr_desc) & mask;
1309 tx_dbg(jme->dev->name,
1310 "Tx Tasklet: Stop %d Jiffies %lu\n",
1313 atomic_set(&txring->next_to_clean, i);
1314 atomic_add(cnt, &txring->nr_free);
1316 jme_wake_queue_if_stopped(jme);
1319 atomic_inc(&jme->tx_cleaning);
1323 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1328 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1331 * Write 1 clear interrupt status
1333 jwrite32f(jme, JME_IEVE, intrstat);
1335 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1336 tasklet_schedule(&jme->linkch_task);
1340 if(intrstat & INTR_TMINTR)
1341 tasklet_schedule(&jme->pcc_task);
1343 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1344 tasklet_schedule(&jme->txclean_task);
1346 if(jme->flags & JME_FLAG_POLL) {
1347 if(intrstat & INTR_RX0EMP)
1348 atomic_inc(&jme->rx_empty);
1350 if((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1351 if(likely(JME_RX_SCHEDULE_PREP(jme))) {
1352 jme_polling_mode(jme);
1353 JME_RX_SCHEDULE(jme);
1358 if(intrstat & INTR_RX0EMP) {
1359 atomic_inc(&jme->rx_empty);
1360 tasklet_schedule(&jme->rxempty_task);
1363 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1364 tasklet_schedule(&jme->rxclean_task);
1369 * Re-enable interrupt
1371 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1377 jme_intr(int irq, void *dev_id)
1379 struct net_device *netdev = dev_id;
1380 struct jme_adapter *jme = netdev_priv(netdev);
1383 intrstat = jread32(jme, JME_IEVE);
1386 * Check if it's really an interrupt for us
1388 if(unlikely(intrstat == 0))
1392 * Check if the device still exist
1394 if(unlikely(intrstat == ~((typeof(intrstat))0)))
1397 jme_intr_msi(jme, intrstat);
1403 jme_msi(int irq, void *dev_id)
1405 struct net_device *netdev = dev_id;
1406 struct jme_adapter *jme = netdev_priv(netdev);
1409 pci_dma_sync_single_for_cpu(jme->pdev,
1411 sizeof(__u32) * SHADOW_REG_NR,
1412 PCI_DMA_FROMDEVICE);
1413 intrstat = jme->shadow_regs[SHADOW_IEVE];
1414 jme->shadow_regs[SHADOW_IEVE] = 0;
1416 jme_intr_msi(jme, intrstat);
1423 jme_reset_link(struct jme_adapter *jme)
1425 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1429 jme_restart_an(struct jme_adapter *jme)
1432 unsigned long flags;
1434 spin_lock_irqsave(&jme->phy_lock, flags);
1435 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1436 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1437 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1438 spin_unlock_irqrestore(&jme->phy_lock, flags);
1442 jme_request_irq(struct jme_adapter *jme)
1445 struct net_device *netdev = jme->dev;
1446 irq_handler_t handler = jme_intr;
1447 int irq_flags = IRQF_SHARED;
1449 if (!pci_enable_msi(jme->pdev)) {
1450 jme->flags |= JME_FLAG_MSI;
1455 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1458 jeprintk(netdev->name,
1459 "Unable to request %s interrupt (return: %d)\n",
1460 jme->flags & JME_FLAG_MSI ? "MSI":"INTx", rc);
1462 if(jme->flags & JME_FLAG_MSI) {
1463 pci_disable_msi(jme->pdev);
1464 jme->flags &= ~JME_FLAG_MSI;
1468 netdev->irq = jme->pdev->irq;
1475 jme_free_irq(struct jme_adapter *jme)
1477 free_irq(jme->pdev->irq, jme->dev);
1478 if (jme->flags & JME_FLAG_MSI) {
1479 pci_disable_msi(jme->pdev);
1480 jme->flags &= ~JME_FLAG_MSI;
1481 jme->dev->irq = jme->pdev->irq;
1486 jme_open(struct net_device *netdev)
1488 struct jme_adapter *jme = netdev_priv(netdev);
1489 int rc, timeout = 10;
1494 atomic_read(&jme->link_changing) != 1 ||
1495 atomic_read(&jme->rx_cleaning) != 1 ||
1496 atomic_read(&jme->tx_cleaning) != 1
1507 jme_reset_mac_processor(jme);
1508 JME_NAPI_ENABLE(jme);
1510 rc = jme_request_irq(jme);
1514 jme_enable_shadow(jme);
1517 if(jme->flags & JME_FLAG_SSET)
1518 jme_set_settings(netdev, &jme->old_ecmd);
1520 jme_reset_phy_processor(jme);
1522 jme_reset_link(jme);
1527 netif_stop_queue(netdev);
1528 netif_carrier_off(netdev);
1533 jme_set_100m_half(struct jme_adapter *jme)
1537 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1538 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1539 BMCR_SPEED1000 | BMCR_FULLDPLX);
1540 tmp |= BMCR_SPEED100;
1543 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1546 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1548 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1552 jme_phy_off(struct jme_adapter *jme)
1554 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1559 jme_close(struct net_device *netdev)
1561 struct jme_adapter *jme = netdev_priv(netdev);
1563 netif_stop_queue(netdev);
1564 netif_carrier_off(netdev);
1567 jme_disable_shadow(jme);
1570 JME_NAPI_DISABLE(jme);
1572 tasklet_kill(&jme->linkch_task);
1573 tasklet_kill(&jme->txclean_task);
1574 tasklet_kill(&jme->rxclean_task);
1575 tasklet_kill(&jme->rxempty_task);
1577 jme_reset_mac_processor(jme);
1578 jme_free_rx_resources(jme);
1579 jme_free_tx_resources(jme);
1587 jme_alloc_txdesc(struct jme_adapter *jme,
1588 struct sk_buff *skb)
1590 struct jme_ring *txring = jme->txring;
1591 int idx, nr_alloc, mask = jme->tx_ring_mask;
1593 idx = txring->next_to_use;
1594 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1596 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1599 atomic_sub(nr_alloc, &txring->nr_free);
1601 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1607 jme_fill_tx_map(struct pci_dev *pdev,
1608 volatile struct txdesc *txdesc,
1609 struct jme_buffer_info *txbi,
1617 dmaaddr = pci_map_page(pdev,
1623 pci_dma_sync_single_for_device(pdev,
1630 txdesc->desc2.flags = TXFLAG_OWN;
1631 txdesc->desc2.flags |= (hidma)?TXFLAG_64BIT:0;
1632 txdesc->desc2.datalen = cpu_to_le16(len);
1633 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1634 txdesc->desc2.bufaddrl = cpu_to_le32(
1635 (__u64)dmaaddr & 0xFFFFFFFFUL);
1637 txbi->mapping = dmaaddr;
1642 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1644 struct jme_ring *txring = jme->txring;
1645 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
1646 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1647 __u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1648 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1649 int mask = jme->tx_ring_mask;
1650 struct skb_frag_struct *frag;
1653 for(i = 0 ; i < nr_frags ; ++i) {
1654 frag = &skb_shinfo(skb)->frags[i];
1655 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1656 ctxbi = txbi + ((idx + i + 2) & (mask));
1658 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1659 frag->page_offset, frag->size, hidma);
1662 len = skb_is_nonlinear(skb)?skb_headlen(skb):skb->len;
1663 ctxdesc = txdesc + ((idx + 1) & (mask));
1664 ctxbi = txbi + ((idx + 1) & (mask));
1665 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1666 offset_in_page(skb->data), len, hidma);
1671 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1673 if(unlikely(skb_shinfo(skb)->gso_size &&
1674 skb_header_cloned(skb) &&
1675 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1684 jme_tx_tso(struct sk_buff *skb,
1685 volatile __u16 *mss, __u8 *flags)
1687 if((*mss = (skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT))) {
1688 *flags |= TXFLAG_LSEN;
1690 if(skb->protocol == __constant_htons(ETH_P_IP)) {
1691 struct iphdr *iph = ip_hdr(skb);
1694 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1700 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1702 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1715 jme_tx_csum(struct sk_buff *skb, __u8 *flags)
1717 if(skb->ip_summed == CHECKSUM_PARTIAL) {
1720 switch (skb->protocol) {
1721 case __constant_htons(ETH_P_IP):
1722 ip_proto = ip_hdr(skb)->protocol;
1724 case __constant_htons(ETH_P_IPV6):
1725 ip_proto = ipv6_hdr(skb)->nexthdr;
1734 *flags |= TXFLAG_TCPCS;
1737 *flags |= TXFLAG_UDPCS;
1740 jeprintk("jme", "Error upper layer protocol.\n");
1746 __always_inline static void
1747 jme_tx_vlan(struct sk_buff *skb, volatile __u16 *vlan, __u8 *flags)
1749 if(vlan_tx_tag_present(skb)) {
1750 vlan_dbg("jme", "Tag found!(%04x)\n", vlan_tx_tag_get(skb));
1751 *flags |= TXFLAG_TAGON;
1752 *vlan = vlan_tx_tag_get(skb);
1757 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1759 struct jme_ring *txring = jme->txring;
1760 volatile struct txdesc *txdesc;
1761 struct jme_buffer_info *txbi;
1764 txdesc = (volatile struct txdesc*)txring->desc + idx;
1765 txbi = txring->bufinf + idx;
1771 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1773 * Set OWN bit at final.
1774 * When kernel transmit faster than NIC.
1775 * And NIC trying to send this descriptor before we tell
1776 * it to start sending this TX queue.
1777 * Other fields are already filled correctly.
1780 flags = TXFLAG_OWN | TXFLAG_INT;
1781 //Set checksum flags while not tso
1782 if(jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1783 jme_tx_csum(skb, &flags);
1784 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1785 txdesc->desc1.flags = flags;
1787 * Set tx buffer info after telling NIC to send
1788 * For better tx_clean timing
1791 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1793 txbi->len = skb->len;
1794 if(!(txbi->start_xmit = jiffies))
1795 txbi->start_xmit = 1;
1801 jme_stop_queue_if_full(struct jme_adapter *jme)
1803 struct jme_ring *txring = jme->txring;
1804 struct jme_buffer_info *txbi = txring->bufinf;
1806 txbi += atomic_read(&txring->next_to_clean);
1809 if(unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1810 netif_stop_queue(jme->dev);
1811 queue_dbg(jme->dev->name, "TX Queue Paused.\n");
1813 if (atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold)) {
1814 netif_wake_queue(jme->dev);
1815 queue_dbg(jme->dev->name, "TX Queue Fast Waked.\n");
1819 if(unlikely( txbi->start_xmit &&
1820 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1822 netif_stop_queue(jme->dev);
1827 * This function is already protected by netif_tx_lock()
1830 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1832 struct jme_adapter *jme = netdev_priv(netdev);
1835 if(skb_shinfo(skb)->nr_frags) {
1836 tx_dbg(netdev->name, "Frags: %d Headlen: %d Len: %d MSS: %d Sum:%d\n",
1837 skb_shinfo(skb)->nr_frags,
1840 skb_shinfo(skb)->gso_size,
1844 if(unlikely(jme_expand_header(jme, skb))) {
1845 ++(NET_STAT(jme).tx_dropped);
1846 return NETDEV_TX_OK;
1849 idx = jme_alloc_txdesc(jme, skb);
1851 if(unlikely(idx<0)) {
1852 netif_stop_queue(netdev);
1853 jeprintk(netdev->name,
1854 "BUG! Tx ring full when queue awake!\n");
1856 return NETDEV_TX_BUSY;
1859 jme_map_tx_skb(jme, skb, idx);
1860 jme_fill_first_tx_desc(jme, skb, idx);
1862 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, skb_shinfo(skb)->nr_frags + 2);
1864 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1865 TXCS_SELECT_QUEUE0 |
1868 netdev->trans_start = jiffies;
1870 jme_stop_queue_if_full(jme);
1872 return NETDEV_TX_OK;
1876 jme_set_macaddr(struct net_device *netdev, void *p)
1878 struct jme_adapter *jme = netdev_priv(netdev);
1879 struct sockaddr *addr = p;
1882 if(netif_running(netdev))
1885 spin_lock(&jme->macaddr_lock);
1886 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1888 val = addr->sa_data[3] << 24 |
1889 addr->sa_data[2] << 16 |
1890 addr->sa_data[1] << 8 |
1892 jwrite32(jme, JME_RXUMA_LO, val);
1893 val = addr->sa_data[5] << 8 |
1895 jwrite32(jme, JME_RXUMA_HI, val);
1896 spin_unlock(&jme->macaddr_lock);
1902 jme_set_multi(struct net_device *netdev)
1904 struct jme_adapter *jme = netdev_priv(netdev);
1905 u32 mc_hash[2] = {};
1907 unsigned long flags;
1909 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1911 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1913 if (netdev->flags & IFF_PROMISC) {
1914 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1916 else if (netdev->flags & IFF_ALLMULTI) {
1917 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1919 else if(netdev->flags & IFF_MULTICAST) {
1920 struct dev_mc_list *mclist;
1923 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1924 for (i = 0, mclist = netdev->mc_list;
1925 mclist && i < netdev->mc_count;
1926 ++i, mclist = mclist->next) {
1928 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1929 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1932 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1933 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1937 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1939 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1943 jme_change_mtu(struct net_device *netdev, int new_mtu)
1945 struct jme_adapter *jme = netdev_priv(netdev);
1947 if(new_mtu == jme->old_mtu)
1950 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1951 ((new_mtu) < IPV6_MIN_MTU))
1954 if(new_mtu > 4000) {
1955 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1956 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1957 jme_restart_rx_engine(jme);
1960 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1961 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1962 jme_restart_rx_engine(jme);
1965 if(new_mtu > 1900) {
1966 netdev->features &= ~(NETIF_F_HW_CSUM |
1971 if(jme->flags & JME_FLAG_TXCSUM)
1972 netdev->features |= NETIF_F_HW_CSUM;
1973 if(jme->flags & JME_FLAG_TSO)
1974 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
1977 netdev->mtu = new_mtu;
1978 jme_reset_link(jme);
1984 jme_tx_timeout(struct net_device *netdev)
1986 struct jme_adapter *jme = netdev_priv(netdev);
1989 jme_reset_phy_processor(jme);
1990 if(jme->flags & JME_FLAG_SSET)
1991 jme_set_settings(netdev, &jme->old_ecmd);
1994 * Force to Reset the link again
1996 jme_reset_link(jme);
2000 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2002 struct jme_adapter *jme = netdev_priv(netdev);
2008 jme_get_drvinfo(struct net_device *netdev,
2009 struct ethtool_drvinfo *info)
2011 struct jme_adapter *jme = netdev_priv(netdev);
2013 strcpy(info->driver, DRV_NAME);
2014 strcpy(info->version, DRV_VERSION);
2015 strcpy(info->bus_info, pci_name(jme->pdev));
2019 jme_get_regs_len(struct net_device *netdev)
2025 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
2029 for(i = 0 ; i < len ; i += 4)
2030 p[i >> 2] = jread32(jme, reg + i);
2035 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2037 struct jme_adapter *jme = netdev_priv(netdev);
2038 __u32 *p32 = (__u32*)p;
2040 memset(p, 0, 0x400);
2043 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2046 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2049 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2052 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2057 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2059 struct jme_adapter *jme = netdev_priv(netdev);
2061 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2062 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2064 if(jme->flags & JME_FLAG_POLL) {
2065 ecmd->use_adaptive_rx_coalesce = false;
2066 ecmd->rx_coalesce_usecs = 0;
2067 ecmd->rx_max_coalesced_frames = 0;
2071 ecmd->use_adaptive_rx_coalesce = true;
2073 switch(jme->dpi.cur) {
2075 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2076 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2079 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2080 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2083 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2084 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2094 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2096 struct jme_adapter *jme = netdev_priv(netdev);
2097 struct dynpcc_info *dpi = &(jme->dpi);
2099 if(netif_running(netdev))
2102 if(ecmd->use_adaptive_rx_coalesce
2103 && (jme->flags & JME_FLAG_POLL)) {
2104 jme->flags &= ~JME_FLAG_POLL;
2105 jme->jme_rx = netif_rx;
2106 jme->jme_vlan_rx = vlan_hwaccel_rx;
2108 dpi->attempt = PCC_P1;
2110 jme_set_rx_pcc(jme, PCC_P1);
2111 jme_interrupt_mode(jme);
2113 else if(!(ecmd->use_adaptive_rx_coalesce)
2114 && !(jme->flags & JME_FLAG_POLL)) {
2115 jme->flags |= JME_FLAG_POLL;
2116 jme->jme_rx = netif_receive_skb;
2117 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2118 jme_interrupt_mode(jme);
2125 jme_get_pauseparam(struct net_device *netdev,
2126 struct ethtool_pauseparam *ecmd)
2128 struct jme_adapter *jme = netdev_priv(netdev);
2129 unsigned long flags;
2132 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2133 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2135 spin_lock_irqsave(&jme->phy_lock, flags);
2136 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2137 spin_unlock_irqrestore(&jme->phy_lock, flags);
2140 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2144 jme_set_pauseparam(struct net_device *netdev,
2145 struct ethtool_pauseparam *ecmd)
2147 struct jme_adapter *jme = netdev_priv(netdev);
2148 unsigned long flags;
2151 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
2152 (ecmd->tx_pause != 0)) {
2155 jme->reg_txpfc |= TXPFC_PF_EN;
2157 jme->reg_txpfc &= ~TXPFC_PF_EN;
2159 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2162 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2163 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
2164 (ecmd->rx_pause != 0)) {
2167 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2169 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2171 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2173 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2175 spin_lock_irqsave(&jme->phy_lock, flags);
2176 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2177 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
2178 (ecmd->autoneg != 0)) {
2181 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2183 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2185 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2186 MII_ADVERTISE, val);
2188 spin_unlock_irqrestore(&jme->phy_lock, flags);
2194 jme_get_wol(struct net_device *netdev,
2195 struct ethtool_wolinfo *wol)
2197 struct jme_adapter *jme = netdev_priv(netdev);
2199 wol->supported = WAKE_MAGIC | WAKE_PHY;
2203 if(jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2204 wol->wolopts |= WAKE_PHY;
2206 if(jme->reg_pmcs & PMCS_MFEN)
2207 wol->wolopts |= WAKE_MAGIC;
2212 jme_set_wol(struct net_device *netdev,
2213 struct ethtool_wolinfo *wol)
2215 struct jme_adapter *jme = netdev_priv(netdev);
2217 if(wol->wolopts & (WAKE_MAGICSECURE |
2226 if(wol->wolopts & WAKE_PHY)
2227 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2229 if(wol->wolopts & WAKE_MAGIC)
2230 jme->reg_pmcs |= PMCS_MFEN;
2237 jme_get_settings(struct net_device *netdev,
2238 struct ethtool_cmd *ecmd)
2240 struct jme_adapter *jme = netdev_priv(netdev);
2242 unsigned long flags;
2244 spin_lock_irqsave(&jme->phy_lock, flags);
2245 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2246 spin_unlock_irqrestore(&jme->phy_lock, flags);
2251 jme_set_settings(struct net_device *netdev,
2252 struct ethtool_cmd *ecmd)
2254 struct jme_adapter *jme = netdev_priv(netdev);
2256 unsigned long flags;
2258 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2261 if(jme->mii_if.force_media &&
2262 ecmd->autoneg != AUTONEG_ENABLE &&
2263 (jme->mii_if.full_duplex != ecmd->duplex))
2266 spin_lock_irqsave(&jme->phy_lock, flags);
2267 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2268 spin_unlock_irqrestore(&jme->phy_lock, flags);
2271 jme_reset_link(jme);
2274 jme->flags |= JME_FLAG_SSET;
2275 jme->old_ecmd = *ecmd;
2282 jme_get_link(struct net_device *netdev)
2284 struct jme_adapter *jme = netdev_priv(netdev);
2285 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2289 jme_get_rx_csum(struct net_device *netdev)
2291 struct jme_adapter *jme = netdev_priv(netdev);
2293 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2297 jme_set_rx_csum(struct net_device *netdev, u32 on)
2299 struct jme_adapter *jme = netdev_priv(netdev);
2300 unsigned long flags;
2302 spin_lock_irqsave(&jme->rxmcs_lock, flags);
2304 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2306 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2307 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2308 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
2314 jme_set_tx_csum(struct net_device *netdev, u32 on)
2316 struct jme_adapter *jme = netdev_priv(netdev);
2319 jme->flags |= JME_FLAG_TXCSUM;
2320 if(netdev->mtu <= 1900)
2321 netdev->features |= NETIF_F_HW_CSUM;
2324 jme->flags &= ~JME_FLAG_TXCSUM;
2325 netdev->features &= ~NETIF_F_HW_CSUM;
2332 jme_set_tso(struct net_device *netdev, u32 on)
2334 struct jme_adapter *jme = netdev_priv(netdev);
2337 jme->flags |= JME_FLAG_TSO;
2338 if(netdev->mtu <= 1900)
2339 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2342 jme->flags &= ~JME_FLAG_TSO;
2343 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2350 jme_nway_reset(struct net_device *netdev)
2352 struct jme_adapter *jme = netdev_priv(netdev);
2353 jme_restart_an(jme);
2357 static const struct ethtool_ops jme_ethtool_ops = {
2358 .get_drvinfo = jme_get_drvinfo,
2359 .get_regs_len = jme_get_regs_len,
2360 .get_regs = jme_get_regs,
2361 .get_coalesce = jme_get_coalesce,
2362 .set_coalesce = jme_set_coalesce,
2363 .get_pauseparam = jme_get_pauseparam,
2364 .set_pauseparam = jme_set_pauseparam,
2365 .get_wol = jme_get_wol,
2366 .set_wol = jme_set_wol,
2367 .get_settings = jme_get_settings,
2368 .set_settings = jme_set_settings,
2369 .get_link = jme_get_link,
2370 .get_rx_csum = jme_get_rx_csum,
2371 .set_rx_csum = jme_set_rx_csum,
2372 .set_tx_csum = jme_set_tx_csum,
2373 .set_tso = jme_set_tso,
2374 .set_sg = ethtool_op_set_sg,
2375 .nway_reset = jme_nway_reset,
2379 jme_pci_dma64(struct pci_dev *pdev)
2381 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
2382 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
2383 dprintk("jme", "64Bit DMA Selected.\n");
2387 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
2388 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK)) {
2389 dprintk("jme", "40Bit DMA Selected.\n");
2393 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2394 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
2395 dprintk("jme", "32Bit DMA Selected.\n");
2402 __always_inline static void
2403 jme_phy_init(struct jme_adapter *jme)
2407 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2408 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2411 __always_inline static void
2412 jme_set_gmii(struct jme_adapter *jme)
2414 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
2418 jme_check_hw_ver(struct jme_adapter *jme)
2422 chipmode = jread32(jme, JME_CHIPMODE);
2424 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2425 jme->chipver = (chipmode & CM_CHIPVER_MASK) >> CM_CHIPVER_SHIFT;
2428 static int __devinit
2429 jme_init_one(struct pci_dev *pdev,
2430 const struct pci_device_id *ent)
2432 int rc = 0, using_dac, i;
2433 struct net_device *netdev;
2434 struct jme_adapter *jme;
2438 * set up PCI device basics
2440 rc = pci_enable_device(pdev);
2442 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2446 using_dac = jme_pci_dma64(pdev);
2448 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2450 goto err_out_disable_pdev;
2453 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2454 printk(KERN_ERR PFX "No PCI resource region found.\n");
2456 goto err_out_disable_pdev;
2459 rc = pci_request_regions(pdev, DRV_NAME);
2461 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2462 goto err_out_disable_pdev;
2465 pci_set_master(pdev);
2468 * alloc and init net device
2470 netdev = alloc_etherdev(sizeof(*jme));
2472 printk(KERN_ERR PFX "Cannot allocate netdev structure.\n");
2474 goto err_out_release_regions;
2476 netdev->open = jme_open;
2477 netdev->stop = jme_close;
2478 netdev->hard_start_xmit = jme_start_xmit;
2479 netdev->set_mac_address = jme_set_macaddr;
2480 netdev->set_multicast_list = jme_set_multi;
2481 netdev->change_mtu = jme_change_mtu;
2482 netdev->ethtool_ops = &jme_ethtool_ops;
2483 netdev->tx_timeout = jme_tx_timeout;
2484 netdev->watchdog_timeo = TX_TIMEOUT;
2485 netdev->vlan_rx_register = jme_vlan_rx_register;
2486 NETDEV_GET_STATS(netdev, &jme_get_stats);
2487 netdev->features = NETIF_F_HW_CSUM |
2491 NETIF_F_HW_VLAN_TX |
2494 netdev->features |= NETIF_F_HIGHDMA;
2496 SET_NETDEV_DEV(netdev, &pdev->dev);
2497 pci_set_drvdata(pdev, netdev);
2502 jme = netdev_priv(netdev);
2505 jme->jme_rx = netif_rx;
2506 jme->jme_vlan_rx = vlan_hwaccel_rx;
2507 jme->old_mtu = netdev->mtu = 1500;
2509 jme->tx_ring_size = 1 << 10;
2510 jme->tx_ring_mask = jme->tx_ring_size - 1;
2511 jme->tx_wake_threshold = 1 << 9;
2512 jme->rx_ring_size = 1 << 9;
2513 jme->rx_ring_mask = jme->rx_ring_size - 1;
2514 jme->regs = ioremap(pci_resource_start(pdev, 0),
2515 pci_resource_len(pdev, 0));
2517 printk(KERN_ERR PFX "Mapping PCI resource region error.\n");
2519 goto err_out_free_netdev;
2521 jme->shadow_regs = pci_alloc_consistent(pdev,
2522 sizeof(__u32) * SHADOW_REG_NR,
2523 &(jme->shadow_dma));
2524 if (!(jme->shadow_regs)) {
2525 printk(KERN_ERR PFX "Allocating shadow register mapping error.\n");
2530 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2532 spin_lock_init(&jme->phy_lock);
2533 spin_lock_init(&jme->macaddr_lock);
2534 spin_lock_init(&jme->rxmcs_lock);
2536 atomic_set(&jme->link_changing, 1);
2537 atomic_set(&jme->rx_cleaning, 1);
2538 atomic_set(&jme->tx_cleaning, 1);
2539 atomic_set(&jme->rx_empty, 1);
2541 tasklet_init(&jme->pcc_task,
2543 (unsigned long) jme);
2544 tasklet_init(&jme->linkch_task,
2545 &jme_link_change_tasklet,
2546 (unsigned long) jme);
2547 tasklet_init(&jme->txclean_task,
2548 &jme_tx_clean_tasklet,
2549 (unsigned long) jme);
2550 tasklet_init(&jme->rxclean_task,
2551 &jme_rx_clean_tasklet,
2552 (unsigned long) jme);
2553 tasklet_init(&jme->rxempty_task,
2554 &jme_rx_empty_tasklet,
2555 (unsigned long) jme);
2556 jme->dpi.cur = PCC_P1;
2558 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2559 jme->reg_rxcs = RXCS_DEFAULT;
2560 jme->reg_rxmcs = RXMCS_DEFAULT;
2562 jme->reg_pmcs = PMCS_LFEN | PMCS_LREN | PMCS_MFEN;
2563 jme->flags = JME_FLAG_TXCSUM | JME_FLAG_TSO;
2566 * Get Max Read Req Size from PCI Config Space
2568 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2571 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2574 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2577 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2583 * Must check before reset_mac_processor
2585 jme_check_hw_ver(jme);
2586 jme->mii_if.dev = netdev;
2588 jme->mii_if.phy_id = 0;
2589 for(i = 1 ; i < 32 ; ++i) {
2590 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2591 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2592 if(bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2593 jme->mii_if.phy_id = i;
2598 if(!jme->mii_if.phy_id) {
2600 printk(KERN_ERR PFX "Can not find phy_id.\n");
2601 goto err_out_free_shadow;
2604 jme->reg_ghc |= GHC_LINK_POLL;
2607 jme->mii_if.phy_id = 1;
2609 jme->mii_if.supports_gmii = 1;
2610 jme->mii_if.mdio_read = jme_mdio_read;
2611 jme->mii_if.mdio_write = jme_mdio_write;
2621 * Reset MAC processor and reload EEPROM for MAC Address
2623 jme_reset_mac_processor(jme);
2624 rc = jme_reload_eeprom(jme);
2627 "Reload eeprom for reading MAC Address error.\n");
2628 goto err_out_free_shadow;
2630 jme_load_macaddr(netdev);
2634 * Tell stack that we are not ready to work until open()
2636 netif_carrier_off(netdev);
2637 netif_stop_queue(netdev);
2642 rc = register_netdev(netdev);
2644 printk(KERN_ERR PFX "Cannot register net device.\n");
2645 goto err_out_free_shadow;
2648 jprintk(netdev->name,
2649 "JMC250 gigabit%s ver:%u eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2650 (jme->fpgaver != 0)?" (FPGA)":"",
2651 (jme->fpgaver != 0)?jme->fpgaver:jme->chipver,
2652 netdev->dev_addr[0],
2653 netdev->dev_addr[1],
2654 netdev->dev_addr[2],
2655 netdev->dev_addr[3],
2656 netdev->dev_addr[4],
2657 netdev->dev_addr[5]);
2661 err_out_free_shadow:
2662 pci_free_consistent(pdev,
2663 sizeof(__u32) * SHADOW_REG_NR,
2668 err_out_free_netdev:
2669 pci_set_drvdata(pdev, NULL);
2670 free_netdev(netdev);
2671 err_out_release_regions:
2672 pci_release_regions(pdev);
2673 err_out_disable_pdev:
2674 pci_disable_device(pdev);
2679 static void __devexit
2680 jme_remove_one(struct pci_dev *pdev)
2682 struct net_device *netdev = pci_get_drvdata(pdev);
2683 struct jme_adapter *jme = netdev_priv(netdev);
2685 unregister_netdev(netdev);
2686 pci_free_consistent(pdev,
2687 sizeof(__u32) * SHADOW_REG_NR,
2691 pci_set_drvdata(pdev, NULL);
2692 free_netdev(netdev);
2693 pci_release_regions(pdev);
2694 pci_disable_device(pdev);
2699 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2701 struct net_device *netdev = pci_get_drvdata(pdev);
2702 struct jme_adapter *jme = netdev_priv(netdev);
2705 atomic_dec(&jme->link_changing);
2707 netif_device_detach(netdev);
2708 netif_stop_queue(netdev);
2712 while(--timeout > 0 &&
2714 atomic_read(&jme->rx_cleaning) != 1 ||
2715 atomic_read(&jme->tx_cleaning) != 1
2720 jeprintk(netdev->name, "Waiting tasklets timeout.\n");
2723 jme_disable_shadow(jme);
2725 if(netif_carrier_ok(netdev)) {
2726 jme_stop_pcc_timer(jme);
2727 jme_reset_mac_processor(jme);
2728 jme_free_rx_resources(jme);
2729 jme_free_tx_resources(jme);
2730 netif_carrier_off(netdev);
2733 if(jme->flags & JME_FLAG_POLL)
2734 jme_polling_mode(jme);
2738 pci_save_state(pdev);
2740 jme_set_100m_half(jme);
2741 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2742 pci_enable_wake(pdev, PCI_D3hot, true);
2743 pci_enable_wake(pdev, PCI_D3cold, true);
2747 pci_enable_wake(pdev, PCI_D3hot, false);
2748 pci_enable_wake(pdev, PCI_D3cold, false);
2750 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2756 jme_resume(struct pci_dev *pdev)
2758 struct net_device *netdev = pci_get_drvdata(pdev);
2759 struct jme_adapter *jme = netdev_priv(netdev);
2762 pci_restore_state(pdev);
2764 if(jme->flags & JME_FLAG_SSET)
2765 jme_set_settings(netdev, &jme->old_ecmd);
2767 jme_reset_phy_processor(jme);
2769 jme_reset_mac_processor(jme);
2770 jme_enable_shadow(jme);
2771 jme_request_irq(jme);
2773 netif_device_attach(netdev);
2775 atomic_inc(&jme->link_changing);
2777 jme_reset_link(jme);
2782 static struct pci_device_id jme_pci_tbl[] = {
2783 { PCI_VDEVICE(JMICRON, 0x250) },
2787 static struct pci_driver jme_driver = {
2789 .id_table = jme_pci_tbl,
2790 .probe = jme_init_one,
2791 .remove = __devexit_p(jme_remove_one),
2793 .suspend = jme_suspend,
2794 .resume = jme_resume,
2795 #endif /* CONFIG_PM */
2799 jme_init_module(void)
2801 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2802 "driver version %s\n", DRV_VERSION);
2803 return pci_register_driver(&jme_driver);
2807 jme_cleanup_module(void)
2809 pci_unregister_driver(&jme_driver);
2812 module_init(jme_init_module);
2813 module_exit(jme_cleanup_module);
2815 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2816 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2817 MODULE_LICENSE("GPL");
2818 MODULE_VERSION(DRV_VERSION);
2819 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);