2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/module.h>
27 #include <linux/kernel.h>
28 #include <linux/pci.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
38 #include <linux/ipv6.h>
39 #include <linux/tcp.h>
40 #include <linux/udp.h>
41 #include <linux/if_vlan.h>
42 #include <linux/slab.h>
43 #include <net/ip6_checksum.h>
46 static int force_pseudohp = -1;
47 static int no_pseudohp = -1;
48 static int no_extplug = -1;
49 module_param(force_pseudohp, int, 0);
50 MODULE_PARM_DESC(force_pseudohp,
51 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
52 module_param(no_pseudohp, int, 0);
53 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
54 module_param(no_extplug, int, 0);
55 MODULE_PARM_DESC(no_extplug,
56 "Do not use external plug signal for pseudo hot-plug.");
59 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 struct jme_adapter *jme = netdev_priv(netdev);
62 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
65 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72 val = jread32(jme, JME_SMI);
73 if ((val & SMI_OP_REQ) == 0)
78 pr_err("phy(%d) read timeout : %d\n", phy, reg);
85 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
89 jme_mdio_write(struct net_device *netdev,
90 int phy, int reg, int val)
92 struct jme_adapter *jme = netdev_priv(netdev);
95 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
96 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
97 smi_phy_addr(phy) | smi_reg_addr(reg));
100 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 pr_err("phy(%d) write timeout : %d\n", phy, reg);
111 jme_reset_phy_processor(struct jme_adapter *jme)
115 jme_mdio_write(jme->dev,
117 MII_ADVERTISE, ADVERTISE_ALL |
118 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
121 jme_mdio_write(jme->dev,
124 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126 val = jme_mdio_read(jme->dev,
130 jme_mdio_write(jme->dev,
132 MII_BMCR, val | BMCR_RESET);
136 jme_setup_wakeup_frame(struct jme_adapter *jme,
137 u32 *mask, u32 crc, int fnr)
144 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 jwrite32(jme, JME_WFODP, crc);
152 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
153 jwrite32(jme, JME_WFOI,
154 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
155 (fnr & WFOI_FRAME_SEL));
157 jwrite32(jme, JME_WFODP, mask[i]);
163 jme_reset_mac_processor(struct jme_adapter *jme)
165 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
166 u32 crc = 0xCDCDCDCD;
170 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 jwrite32(jme, JME_GHC, jme->reg_ghc);
174 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
175 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
176 jwrite32(jme, JME_RXQDC, 0x00000000);
177 jwrite32(jme, JME_RXNDA, 0x00000000);
178 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_TXQDC, 0x00000000);
181 jwrite32(jme, JME_TXNDA, 0x00000000);
183 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
185 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
186 jme_setup_wakeup_frame(jme, mask, crc, i);
188 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 gpreg0 = GPREG0_DEFAULT;
191 jwrite32(jme, JME_GPREG0, gpreg0);
192 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
196 jme_reset_ghc_speed(struct jme_adapter *jme)
198 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
199 jwrite32(jme, JME_GHC, jme->reg_ghc);
203 jme_clear_pm(struct jme_adapter *jme)
205 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
206 pci_set_power_state(jme->pdev, PCI_D0);
207 pci_enable_wake(jme->pdev, PCI_D0, false);
211 jme_reload_eeprom(struct jme_adapter *jme)
216 val = jread32(jme, JME_SMBCSR);
218 if (val & SMBCSR_EEPROMD) {
220 jwrite32(jme, JME_SMBCSR, val);
221 val |= SMBCSR_RELOAD;
222 jwrite32(jme, JME_SMBCSR, val);
225 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 pr_err("eeprom reload timeout\n");
241 jme_load_macaddr(struct net_device *netdev)
243 struct jme_adapter *jme = netdev_priv(netdev);
244 unsigned char macaddr[6];
247 spin_lock_bh(&jme->macaddr_lock);
248 val = jread32(jme, JME_RXUMA_LO);
249 macaddr[0] = (val >> 0) & 0xFF;
250 macaddr[1] = (val >> 8) & 0xFF;
251 macaddr[2] = (val >> 16) & 0xFF;
252 macaddr[3] = (val >> 24) & 0xFF;
253 val = jread32(jme, JME_RXUMA_HI);
254 macaddr[4] = (val >> 0) & 0xFF;
255 macaddr[5] = (val >> 8) & 0xFF;
256 memcpy(netdev->dev_addr, macaddr, 6);
257 spin_unlock_bh(&jme->macaddr_lock);
261 jme_set_rx_pcc(struct jme_adapter *jme, int p)
265 jwrite32(jme, JME_PCCRX0,
266 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
267 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
270 jwrite32(jme, JME_PCCRX0,
271 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
272 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
275 jwrite32(jme, JME_PCCRX0,
276 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
277 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
280 jwrite32(jme, JME_PCCRX0,
281 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
282 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
289 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
290 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
294 jme_start_irq(struct jme_adapter *jme)
296 register struct dynpcc_info *dpi = &(jme->dpi);
298 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->attempt = PCC_P1;
303 jwrite32(jme, JME_PCCTX,
304 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
305 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
312 jwrite32(jme, JME_IENS, INTR_ENABLE);
316 jme_stop_irq(struct jme_adapter *jme)
321 jwrite32f(jme, JME_IENC, INTR_ENABLE);
325 jme_linkstat_from_phy(struct jme_adapter *jme)
329 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
330 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
331 if (bmsr & BMSR_ANCOMP)
332 phylink |= PHY_LINK_AUTONEG_COMPLETE;
338 jme_set_phyfifoa(struct jme_adapter *jme)
340 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
344 jme_set_phyfifob(struct jme_adapter *jme)
346 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
350 jme_check_link(struct net_device *netdev, int testonly)
352 struct jme_adapter *jme = netdev_priv(netdev);
353 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
360 phylink = jme_linkstat_from_phy(jme);
362 phylink = jread32(jme, JME_PHY_LINK);
364 if (phylink & PHY_LINK_UP) {
365 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
367 * If we did not enable AN
368 * Speed/Duplex Info should be obtained from SMI
370 phylink = PHY_LINK_UP;
372 bmcr = jme_mdio_read(jme->dev,
376 phylink |= ((bmcr & BMCR_SPEED1000) &&
377 (bmcr & BMCR_SPEED100) == 0) ?
378 PHY_LINK_SPEED_1000M :
379 (bmcr & BMCR_SPEED100) ?
380 PHY_LINK_SPEED_100M :
383 phylink |= (bmcr & BMCR_FULLDPLX) ?
386 strcat(linkmsg, "Forced: ");
389 * Keep polling for speed/duplex resolve complete
391 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
397 phylink = jme_linkstat_from_phy(jme);
399 phylink = jread32(jme, JME_PHY_LINK);
402 pr_err("Waiting speed resolve timeout\n");
404 strcat(linkmsg, "ANed: ");
407 if (jme->phylink == phylink) {
414 jme->phylink = phylink;
416 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
417 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
418 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
419 switch (phylink & PHY_LINK_SPEED_MASK) {
420 case PHY_LINK_SPEED_10M:
421 ghc |= GHC_SPEED_10M |
422 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
423 strcat(linkmsg, "10 Mbps, ");
425 case PHY_LINK_SPEED_100M:
426 ghc |= GHC_SPEED_100M |
427 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
428 strcat(linkmsg, "100 Mbps, ");
430 case PHY_LINK_SPEED_1000M:
431 ghc |= GHC_SPEED_1000M |
432 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
433 strcat(linkmsg, "1000 Mbps, ");
439 if (phylink & PHY_LINK_DUPLEX) {
440 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
443 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
447 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
448 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
450 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
453 gpreg1 = GPREG1_DEFAULT;
454 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
455 if (!(phylink & PHY_LINK_DUPLEX))
456 gpreg1 |= GPREG1_HALFMODEPATCH;
457 switch (phylink & PHY_LINK_SPEED_MASK) {
458 case PHY_LINK_SPEED_10M:
459 jme_set_phyfifoa(jme);
460 gpreg1 |= GPREG1_RSSPATCH;
462 case PHY_LINK_SPEED_100M:
463 jme_set_phyfifob(jme);
464 gpreg1 |= GPREG1_RSSPATCH;
466 case PHY_LINK_SPEED_1000M:
467 jme_set_phyfifoa(jme);
474 jwrite32(jme, JME_GPREG1, gpreg1);
475 jwrite32(jme, JME_GHC, ghc);
478 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
485 netif_carrier_on(netdev);
490 netif_info(jme, link, jme->dev, "Link is down\n");
492 netif_carrier_off(netdev);
500 jme_setup_tx_resources(struct jme_adapter *jme)
502 struct jme_ring *txring = &(jme->txring[0]);
504 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
505 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
515 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
517 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
518 txring->next_to_use = 0;
519 atomic_set(&txring->next_to_clean, 0);
520 atomic_set(&txring->nr_free, jme->tx_ring_size);
522 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
523 jme->tx_ring_size, GFP_ATOMIC);
524 if (unlikely(!(txring->bufinf)))
525 goto err_free_txring;
528 * Initialize Transmit Descriptors
530 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
531 memset(txring->bufinf, 0,
532 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
537 dma_free_coherent(&(jme->pdev->dev),
538 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
544 txring->dmaalloc = 0;
546 txring->bufinf = NULL;
552 jme_free_tx_resources(struct jme_adapter *jme)
555 struct jme_ring *txring = &(jme->txring[0]);
556 struct jme_buffer_info *txbi;
559 if (txring->bufinf) {
560 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
561 txbi = txring->bufinf + i;
563 dev_kfree_skb(txbi->skb);
569 txbi->start_xmit = 0;
571 kfree(txring->bufinf);
574 dma_free_coherent(&(jme->pdev->dev),
575 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
579 txring->alloc = NULL;
581 txring->dmaalloc = 0;
583 txring->bufinf = NULL;
585 txring->next_to_use = 0;
586 atomic_set(&txring->next_to_clean, 0);
587 atomic_set(&txring->nr_free, 0);
591 jme_enable_tx_engine(struct jme_adapter *jme)
596 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
600 * Setup TX Queue 0 DMA Bass Address
602 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
603 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
604 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607 * Setup TX Descptor Count
609 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
615 jwrite32(jme, JME_TXCS, jme->reg_txcs |
622 jme_restart_tx_engine(struct jme_adapter *jme)
627 jwrite32(jme, JME_TXCS, jme->reg_txcs |
633 jme_disable_tx_engine(struct jme_adapter *jme)
641 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 val = jread32(jme, JME_TXCS);
645 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
647 val = jread32(jme, JME_TXCS);
652 pr_err("Disable TX engine timeout\n");
656 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
658 struct jme_ring *rxring = &(jme->rxring[0]);
659 register struct rxdesc *rxdesc = rxring->desc;
660 struct jme_buffer_info *rxbi = rxring->bufinf;
666 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
667 rxdesc->desc1.bufaddrl = cpu_to_le32(
668 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
669 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
670 if (jme->dev->features & NETIF_F_HIGHDMA)
671 rxdesc->desc1.flags = RXFLAG_64BIT;
673 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
677 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
679 struct jme_ring *rxring = &(jme->rxring[0]);
680 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 skb = netdev_alloc_skb(jme->dev,
684 jme->dev->mtu + RX_EXTRA_LEN);
689 rxbi->len = skb_tailroom(skb);
690 rxbi->mapping = pci_map_page(jme->pdev,
691 virt_to_page(skb->data),
692 offset_in_page(skb->data),
700 jme_free_rx_buf(struct jme_adapter *jme, int i)
702 struct jme_ring *rxring = &(jme->rxring[0]);
703 struct jme_buffer_info *rxbi = rxring->bufinf;
707 pci_unmap_page(jme->pdev,
711 dev_kfree_skb(rxbi->skb);
719 jme_free_rx_resources(struct jme_adapter *jme)
722 struct jme_ring *rxring = &(jme->rxring[0]);
725 if (rxring->bufinf) {
726 for (i = 0 ; i < jme->rx_ring_size ; ++i)
727 jme_free_rx_buf(jme, i);
728 kfree(rxring->bufinf);
731 dma_free_coherent(&(jme->pdev->dev),
732 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
735 rxring->alloc = NULL;
737 rxring->dmaalloc = 0;
739 rxring->bufinf = NULL;
741 rxring->next_to_use = 0;
742 atomic_set(&rxring->next_to_clean, 0);
746 jme_setup_rx_resources(struct jme_adapter *jme)
749 struct jme_ring *rxring = &(jme->rxring[0]);
751 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
752 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
761 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
763 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
764 rxring->next_to_use = 0;
765 atomic_set(&rxring->next_to_clean, 0);
767 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
768 jme->rx_ring_size, GFP_ATOMIC);
769 if (unlikely(!(rxring->bufinf)))
770 goto err_free_rxring;
773 * Initiallize Receive Descriptors
775 memset(rxring->bufinf, 0,
776 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
777 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
778 if (unlikely(jme_make_new_rx_buf(jme, i))) {
779 jme_free_rx_resources(jme);
783 jme_set_clean_rxdesc(jme, i);
789 dma_free_coherent(&(jme->pdev->dev),
790 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
795 rxring->dmaalloc = 0;
797 rxring->bufinf = NULL;
803 jme_enable_rx_engine(struct jme_adapter *jme)
808 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
813 * Setup RX DMA Bass Address
815 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
816 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
817 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
820 * Setup RX Descriptor Count
822 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
825 * Setup Unicast Filter
827 jme_set_multi(jme->dev);
833 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
840 jme_restart_rx_engine(struct jme_adapter *jme)
845 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
852 jme_disable_rx_engine(struct jme_adapter *jme)
860 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
863 val = jread32(jme, JME_RXCS);
864 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
866 val = jread32(jme, JME_RXCS);
871 pr_err("Disable RX engine timeout\n");
876 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
878 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
881 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
882 == RXWBFLAG_TCPON)) {
883 if (flags & RXWBFLAG_IPV4)
884 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
888 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
889 == RXWBFLAG_UDPON)) {
890 if (flags & RXWBFLAG_IPV4)
891 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
895 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
897 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
905 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
907 struct jme_ring *rxring = &(jme->rxring[0]);
908 struct rxdesc *rxdesc = rxring->desc;
909 struct jme_buffer_info *rxbi = rxring->bufinf;
917 pci_dma_sync_single_for_cpu(jme->pdev,
922 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
923 pci_dma_sync_single_for_device(jme->pdev,
928 ++(NET_STAT(jme).rx_dropped);
930 framesize = le16_to_cpu(rxdesc->descwb.framesize)
933 skb_reserve(skb, RX_PREPAD_SIZE);
934 skb_put(skb, framesize);
935 skb->protocol = eth_type_trans(skb, jme->dev);
937 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
938 skb->ip_summed = CHECKSUM_UNNECESSARY;
940 skb_checksum_none_assert(skb);
942 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
944 jme->jme_vlan_rx(skb, jme->vlgrp,
945 le16_to_cpu(rxdesc->descwb.vlan));
946 NET_STAT(jme).rx_bytes += 4;
954 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
955 cpu_to_le16(RXWBFLAG_DEST_MUL))
956 ++(NET_STAT(jme).multicast);
958 NET_STAT(jme).rx_bytes += framesize;
959 ++(NET_STAT(jme).rx_packets);
962 jme_set_clean_rxdesc(jme, idx);
967 jme_process_receive(struct jme_adapter *jme, int limit)
969 struct jme_ring *rxring = &(jme->rxring[0]);
970 struct rxdesc *rxdesc = rxring->desc;
971 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
973 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
976 if (unlikely(atomic_read(&jme->link_changing) != 1))
979 if (unlikely(!netif_carrier_ok(jme->dev)))
982 i = atomic_read(&rxring->next_to_clean);
984 rxdesc = rxring->desc;
987 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
988 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
992 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
994 if (unlikely(desccnt > 1 ||
995 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
997 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
998 ++(NET_STAT(jme).rx_crc_errors);
999 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1000 ++(NET_STAT(jme).rx_fifo_errors);
1002 ++(NET_STAT(jme).rx_errors);
1005 limit -= desccnt - 1;
1007 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1008 jme_set_clean_rxdesc(jme, j);
1009 j = (j + 1) & (mask);
1013 jme_alloc_and_feed_skb(jme, i);
1016 i = (i + desccnt) & (mask);
1020 atomic_set(&rxring->next_to_clean, i);
1023 atomic_inc(&jme->rx_cleaning);
1025 return limit > 0 ? limit : 0;
1030 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1032 if (likely(atmp == dpi->cur)) {
1037 if (dpi->attempt == atmp) {
1040 dpi->attempt = atmp;
1047 jme_dynamic_pcc(struct jme_adapter *jme)
1049 register struct dynpcc_info *dpi = &(jme->dpi);
1051 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1052 jme_attempt_pcc(dpi, PCC_P3);
1053 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1054 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1055 jme_attempt_pcc(dpi, PCC_P2);
1057 jme_attempt_pcc(dpi, PCC_P1);
1059 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1060 if (dpi->attempt < dpi->cur)
1061 tasklet_schedule(&jme->rxclean_task);
1062 jme_set_rx_pcc(jme, dpi->attempt);
1063 dpi->cur = dpi->attempt;
1069 jme_start_pcc_timer(struct jme_adapter *jme)
1071 struct dynpcc_info *dpi = &(jme->dpi);
1072 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1073 dpi->last_pkts = NET_STAT(jme).rx_packets;
1075 jwrite32(jme, JME_TMCSR,
1076 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1080 jme_stop_pcc_timer(struct jme_adapter *jme)
1082 jwrite32(jme, JME_TMCSR, 0);
1086 jme_shutdown_nic(struct jme_adapter *jme)
1090 phylink = jme_linkstat_from_phy(jme);
1092 if (!(phylink & PHY_LINK_UP)) {
1094 * Disable all interrupt before issue timer
1097 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1102 jme_pcc_tasklet(unsigned long arg)
1104 struct jme_adapter *jme = (struct jme_adapter *)arg;
1105 struct net_device *netdev = jme->dev;
1107 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1108 jme_shutdown_nic(jme);
1112 if (unlikely(!netif_carrier_ok(netdev) ||
1113 (atomic_read(&jme->link_changing) != 1)
1115 jme_stop_pcc_timer(jme);
1119 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1120 jme_dynamic_pcc(jme);
1122 jme_start_pcc_timer(jme);
1126 jme_polling_mode(struct jme_adapter *jme)
1128 jme_set_rx_pcc(jme, PCC_OFF);
1132 jme_interrupt_mode(struct jme_adapter *jme)
1134 jme_set_rx_pcc(jme, PCC_P1);
1138 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1141 apmc = jread32(jme, JME_APMC);
1142 return apmc & JME_APMC_PSEUDO_HP_EN;
1146 jme_start_shutdown_timer(struct jme_adapter *jme)
1150 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1151 apmc &= ~JME_APMC_EPIEN_CTRL;
1153 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1156 jwrite32f(jme, JME_APMC, apmc);
1158 jwrite32f(jme, JME_TIMER2, 0);
1159 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1160 jwrite32(jme, JME_TMCSR,
1161 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1165 jme_stop_shutdown_timer(struct jme_adapter *jme)
1169 jwrite32f(jme, JME_TMCSR, 0);
1170 jwrite32f(jme, JME_TIMER2, 0);
1171 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1173 apmc = jread32(jme, JME_APMC);
1174 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1175 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1177 jwrite32f(jme, JME_APMC, apmc);
1181 jme_link_change_tasklet(unsigned long arg)
1183 struct jme_adapter *jme = (struct jme_adapter *)arg;
1184 struct net_device *netdev = jme->dev;
1187 while (!atomic_dec_and_test(&jme->link_changing)) {
1188 atomic_inc(&jme->link_changing);
1189 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1190 while (atomic_read(&jme->link_changing) != 1)
1191 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1194 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1197 jme->old_mtu = netdev->mtu;
1198 netif_stop_queue(netdev);
1199 if (jme_pseudo_hotplug_enabled(jme))
1200 jme_stop_shutdown_timer(jme);
1202 jme_stop_pcc_timer(jme);
1203 tasklet_disable(&jme->txclean_task);
1204 tasklet_disable(&jme->rxclean_task);
1205 tasklet_disable(&jme->rxempty_task);
1207 if (netif_carrier_ok(netdev)) {
1208 jme_reset_ghc_speed(jme);
1209 jme_disable_rx_engine(jme);
1210 jme_disable_tx_engine(jme);
1211 jme_reset_mac_processor(jme);
1212 jme_free_rx_resources(jme);
1213 jme_free_tx_resources(jme);
1215 if (test_bit(JME_FLAG_POLL, &jme->flags))
1216 jme_polling_mode(jme);
1218 netif_carrier_off(netdev);
1221 jme_check_link(netdev, 0);
1222 if (netif_carrier_ok(netdev)) {
1223 rc = jme_setup_rx_resources(jme);
1225 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1226 goto out_enable_tasklet;
1229 rc = jme_setup_tx_resources(jme);
1231 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1232 goto err_out_free_rx_resources;
1235 jme_enable_rx_engine(jme);
1236 jme_enable_tx_engine(jme);
1238 netif_start_queue(netdev);
1240 if (test_bit(JME_FLAG_POLL, &jme->flags))
1241 jme_interrupt_mode(jme);
1243 jme_start_pcc_timer(jme);
1244 } else if (jme_pseudo_hotplug_enabled(jme)) {
1245 jme_start_shutdown_timer(jme);
1248 goto out_enable_tasklet;
1250 err_out_free_rx_resources:
1251 jme_free_rx_resources(jme);
1253 tasklet_enable(&jme->txclean_task);
1254 tasklet_hi_enable(&jme->rxclean_task);
1255 tasklet_hi_enable(&jme->rxempty_task);
1257 atomic_inc(&jme->link_changing);
1261 jme_rx_clean_tasklet(unsigned long arg)
1263 struct jme_adapter *jme = (struct jme_adapter *)arg;
1264 struct dynpcc_info *dpi = &(jme->dpi);
1266 jme_process_receive(jme, jme->rx_ring_size);
1272 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1274 struct jme_adapter *jme = jme_napi_priv(holder);
1277 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1279 while (atomic_read(&jme->rx_empty) > 0) {
1280 atomic_dec(&jme->rx_empty);
1281 ++(NET_STAT(jme).rx_dropped);
1282 jme_restart_rx_engine(jme);
1284 atomic_inc(&jme->rx_empty);
1287 JME_RX_COMPLETE(netdev, holder);
1288 jme_interrupt_mode(jme);
1291 JME_NAPI_WEIGHT_SET(budget, rest);
1292 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1296 jme_rx_empty_tasklet(unsigned long arg)
1298 struct jme_adapter *jme = (struct jme_adapter *)arg;
1300 if (unlikely(atomic_read(&jme->link_changing) != 1))
1303 if (unlikely(!netif_carrier_ok(jme->dev)))
1306 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1308 jme_rx_clean_tasklet(arg);
1310 while (atomic_read(&jme->rx_empty) > 0) {
1311 atomic_dec(&jme->rx_empty);
1312 ++(NET_STAT(jme).rx_dropped);
1313 jme_restart_rx_engine(jme);
1315 atomic_inc(&jme->rx_empty);
1319 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1321 struct jme_ring *txring = &(jme->txring[0]);
1324 if (unlikely(netif_queue_stopped(jme->dev) &&
1325 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1326 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1327 netif_wake_queue(jme->dev);
1333 jme_tx_clean_tasklet(unsigned long arg)
1335 struct jme_adapter *jme = (struct jme_adapter *)arg;
1336 struct jme_ring *txring = &(jme->txring[0]);
1337 struct txdesc *txdesc = txring->desc;
1338 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1339 int i, j, cnt = 0, max, err, mask;
1341 tx_dbg(jme, "Into txclean\n");
1343 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1346 if (unlikely(atomic_read(&jme->link_changing) != 1))
1349 if (unlikely(!netif_carrier_ok(jme->dev)))
1352 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1353 mask = jme->tx_ring_mask;
1355 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1359 if (likely(ctxbi->skb &&
1360 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1362 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1363 i, ctxbi->nr_desc, jiffies);
1365 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1367 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1368 ttxbi = txbi + ((i + j) & (mask));
1369 txdesc[(i + j) & (mask)].dw[0] = 0;
1371 pci_unmap_page(jme->pdev,
1380 dev_kfree_skb(ctxbi->skb);
1382 cnt += ctxbi->nr_desc;
1384 if (unlikely(err)) {
1385 ++(NET_STAT(jme).tx_carrier_errors);
1387 ++(NET_STAT(jme).tx_packets);
1388 NET_STAT(jme).tx_bytes += ctxbi->len;
1393 ctxbi->start_xmit = 0;
1399 i = (i + ctxbi->nr_desc) & mask;
1404 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1405 atomic_set(&txring->next_to_clean, i);
1406 atomic_add(cnt, &txring->nr_free);
1408 jme_wake_queue_if_stopped(jme);
1411 atomic_inc(&jme->tx_cleaning);
1415 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1420 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1422 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1424 * Link change event is critical
1425 * all other events are ignored
1427 jwrite32(jme, JME_IEVE, intrstat);
1428 tasklet_schedule(&jme->linkch_task);
1432 if (intrstat & INTR_TMINTR) {
1433 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1434 tasklet_schedule(&jme->pcc_task);
1437 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1438 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1439 tasklet_schedule(&jme->txclean_task);
1442 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1443 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1449 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1450 if (intrstat & INTR_RX0EMP)
1451 atomic_inc(&jme->rx_empty);
1453 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1455 jme_polling_mode(jme);
1456 JME_RX_SCHEDULE(jme);
1460 if (intrstat & INTR_RX0EMP) {
1461 atomic_inc(&jme->rx_empty);
1462 tasklet_hi_schedule(&jme->rxempty_task);
1463 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1464 tasklet_hi_schedule(&jme->rxclean_task);
1470 * Re-enable interrupt
1472 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1476 jme_intr(int irq, void *dev_id)
1478 struct net_device *netdev = dev_id;
1479 struct jme_adapter *jme = netdev_priv(netdev);
1482 intrstat = jread32(jme, JME_IEVE);
1485 * Check if it's really an interrupt for us
1487 if (unlikely((intrstat & INTR_ENABLE) == 0))
1491 * Check if the device still exist
1493 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1496 jme_intr_msi(jme, intrstat);
1502 jme_msi(int irq, void *dev_id)
1504 struct net_device *netdev = dev_id;
1505 struct jme_adapter *jme = netdev_priv(netdev);
1508 intrstat = jread32(jme, JME_IEVE);
1510 jme_intr_msi(jme, intrstat);
1516 jme_reset_link(struct jme_adapter *jme)
1518 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1522 jme_restart_an(struct jme_adapter *jme)
1526 spin_lock_bh(&jme->phy_lock);
1527 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1528 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1529 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1530 spin_unlock_bh(&jme->phy_lock);
1534 jme_request_irq(struct jme_adapter *jme)
1537 struct net_device *netdev = jme->dev;
1538 irq_handler_t handler = jme_intr;
1539 int irq_flags = IRQF_SHARED;
1541 if (!pci_enable_msi(jme->pdev)) {
1542 set_bit(JME_FLAG_MSI, &jme->flags);
1547 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1551 "Unable to request %s interrupt (return: %d)\n",
1552 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1555 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1556 pci_disable_msi(jme->pdev);
1557 clear_bit(JME_FLAG_MSI, &jme->flags);
1560 netdev->irq = jme->pdev->irq;
1567 jme_free_irq(struct jme_adapter *jme)
1569 free_irq(jme->pdev->irq, jme->dev);
1570 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1571 pci_disable_msi(jme->pdev);
1572 clear_bit(JME_FLAG_MSI, &jme->flags);
1573 jme->dev->irq = jme->pdev->irq;
1578 jme_phy_on(struct jme_adapter *jme)
1582 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1583 bmcr &= ~BMCR_PDOWN;
1584 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1588 jme_open(struct net_device *netdev)
1590 struct jme_adapter *jme = netdev_priv(netdev);
1594 JME_NAPI_ENABLE(jme);
1596 tasklet_enable(&jme->linkch_task);
1597 tasklet_enable(&jme->txclean_task);
1598 tasklet_hi_enable(&jme->rxclean_task);
1599 tasklet_hi_enable(&jme->rxempty_task);
1601 rc = jme_request_irq(jme);
1607 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1609 jme_set_settings(netdev, &jme->old_ecmd);
1611 jme_reset_phy_processor(jme);
1614 jme_reset_link(jme);
1619 netif_stop_queue(netdev);
1620 netif_carrier_off(netdev);
1626 jme_set_100m_half(struct jme_adapter *jme)
1630 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1631 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1632 BMCR_SPEED1000 | BMCR_FULLDPLX);
1633 tmp |= BMCR_SPEED100;
1636 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1639 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1641 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1644 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1646 jme_wait_link(struct jme_adapter *jme)
1648 u32 phylink, to = JME_WAIT_LINK_TIME;
1651 phylink = jme_linkstat_from_phy(jme);
1652 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1654 phylink = jme_linkstat_from_phy(jme);
1660 jme_phy_off(struct jme_adapter *jme)
1662 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1666 jme_close(struct net_device *netdev)
1668 struct jme_adapter *jme = netdev_priv(netdev);
1670 netif_stop_queue(netdev);
1671 netif_carrier_off(netdev);
1676 JME_NAPI_DISABLE(jme);
1678 tasklet_disable(&jme->linkch_task);
1679 tasklet_disable(&jme->txclean_task);
1680 tasklet_disable(&jme->rxclean_task);
1681 tasklet_disable(&jme->rxempty_task);
1683 jme_reset_ghc_speed(jme);
1684 jme_disable_rx_engine(jme);
1685 jme_disable_tx_engine(jme);
1686 jme_reset_mac_processor(jme);
1687 jme_free_rx_resources(jme);
1688 jme_free_tx_resources(jme);
1696 jme_alloc_txdesc(struct jme_adapter *jme,
1697 struct sk_buff *skb)
1699 struct jme_ring *txring = &(jme->txring[0]);
1700 int idx, nr_alloc, mask = jme->tx_ring_mask;
1702 idx = txring->next_to_use;
1703 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1705 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1708 atomic_sub(nr_alloc, &txring->nr_free);
1710 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1716 jme_fill_tx_map(struct pci_dev *pdev,
1717 struct txdesc *txdesc,
1718 struct jme_buffer_info *txbi,
1726 dmaaddr = pci_map_page(pdev,
1732 pci_dma_sync_single_for_device(pdev,
1739 txdesc->desc2.flags = TXFLAG_OWN;
1740 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1741 txdesc->desc2.datalen = cpu_to_le16(len);
1742 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1743 txdesc->desc2.bufaddrl = cpu_to_le32(
1744 (__u64)dmaaddr & 0xFFFFFFFFUL);
1746 txbi->mapping = dmaaddr;
1751 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1753 struct jme_ring *txring = &(jme->txring[0]);
1754 struct txdesc *txdesc = txring->desc, *ctxdesc;
1755 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1756 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1757 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1758 int mask = jme->tx_ring_mask;
1759 struct skb_frag_struct *frag;
1762 for (i = 0 ; i < nr_frags ; ++i) {
1763 frag = &skb_shinfo(skb)->frags[i];
1764 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1765 ctxbi = txbi + ((idx + i + 2) & (mask));
1767 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1768 frag->page_offset, frag->size, hidma);
1771 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1772 ctxdesc = txdesc + ((idx + 1) & (mask));
1773 ctxbi = txbi + ((idx + 1) & (mask));
1774 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1775 offset_in_page(skb->data), len, hidma);
1780 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1782 if (unlikely(skb_shinfo(skb)->gso_size &&
1783 skb_header_cloned(skb) &&
1784 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1793 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1795 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1797 *flags |= TXFLAG_LSEN;
1799 if (skb->protocol == htons(ETH_P_IP)) {
1800 struct iphdr *iph = ip_hdr(skb);
1803 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1808 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1810 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1823 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1825 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1828 switch (skb->protocol) {
1829 case htons(ETH_P_IP):
1830 ip_proto = ip_hdr(skb)->protocol;
1832 case htons(ETH_P_IPV6):
1833 ip_proto = ipv6_hdr(skb)->nexthdr;
1842 *flags |= TXFLAG_TCPCS;
1845 *flags |= TXFLAG_UDPCS;
1848 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1855 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1857 if (vlan_tx_tag_present(skb)) {
1858 *flags |= TXFLAG_TAGON;
1859 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1864 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1866 struct jme_ring *txring = &(jme->txring[0]);
1867 struct txdesc *txdesc;
1868 struct jme_buffer_info *txbi;
1871 txdesc = (struct txdesc *)txring->desc + idx;
1872 txbi = txring->bufinf + idx;
1878 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1880 * Set OWN bit at final.
1881 * When kernel transmit faster than NIC.
1882 * And NIC trying to send this descriptor before we tell
1883 * it to start sending this TX queue.
1884 * Other fields are already filled correctly.
1887 flags = TXFLAG_OWN | TXFLAG_INT;
1889 * Set checksum flags while not tso
1891 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1892 jme_tx_csum(jme, skb, &flags);
1893 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1894 jme_map_tx_skb(jme, skb, idx);
1895 txdesc->desc1.flags = flags;
1897 * Set tx buffer info after telling NIC to send
1898 * For better tx_clean timing
1901 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1903 txbi->len = skb->len;
1904 txbi->start_xmit = jiffies;
1905 if (!txbi->start_xmit)
1906 txbi->start_xmit = (0UL-1);
1912 jme_stop_queue_if_full(struct jme_adapter *jme)
1914 struct jme_ring *txring = &(jme->txring[0]);
1915 struct jme_buffer_info *txbi = txring->bufinf;
1916 int idx = atomic_read(&txring->next_to_clean);
1921 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1922 netif_stop_queue(jme->dev);
1923 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1925 if (atomic_read(&txring->nr_free)
1926 >= (jme->tx_wake_threshold)) {
1927 netif_wake_queue(jme->dev);
1928 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1932 if (unlikely(txbi->start_xmit &&
1933 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1935 netif_stop_queue(jme->dev);
1936 netif_info(jme, tx_queued, jme->dev,
1937 "TX Queue Stopped %d@%lu\n", idx, jiffies);
1942 * This function is already protected by netif_tx_lock()
1946 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1948 struct jme_adapter *jme = netdev_priv(netdev);
1951 if (unlikely(jme_expand_header(jme, skb))) {
1952 ++(NET_STAT(jme).tx_dropped);
1953 return NETDEV_TX_OK;
1956 idx = jme_alloc_txdesc(jme, skb);
1958 if (unlikely(idx < 0)) {
1959 netif_stop_queue(netdev);
1960 netif_err(jme, tx_err, jme->dev,
1961 "BUG! Tx ring full when queue awake!\n");
1963 return NETDEV_TX_BUSY;
1966 jme_fill_tx_desc(jme, skb, idx);
1968 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1969 TXCS_SELECT_QUEUE0 |
1973 tx_dbg(jme, "xmit: %d+%d@%lu\n",
1974 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1975 jme_stop_queue_if_full(jme);
1977 return NETDEV_TX_OK;
1981 jme_set_macaddr(struct net_device *netdev, void *p)
1983 struct jme_adapter *jme = netdev_priv(netdev);
1984 struct sockaddr *addr = p;
1987 if (netif_running(netdev))
1990 spin_lock_bh(&jme->macaddr_lock);
1991 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1993 val = (addr->sa_data[3] & 0xff) << 24 |
1994 (addr->sa_data[2] & 0xff) << 16 |
1995 (addr->sa_data[1] & 0xff) << 8 |
1996 (addr->sa_data[0] & 0xff);
1997 jwrite32(jme, JME_RXUMA_LO, val);
1998 val = (addr->sa_data[5] & 0xff) << 8 |
1999 (addr->sa_data[4] & 0xff);
2000 jwrite32(jme, JME_RXUMA_HI, val);
2001 spin_unlock_bh(&jme->macaddr_lock);
2007 jme_set_multi(struct net_device *netdev)
2009 struct jme_adapter *jme = netdev_priv(netdev);
2010 u32 mc_hash[2] = {};
2012 spin_lock_bh(&jme->rxmcs_lock);
2014 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2016 if (netdev->flags & IFF_PROMISC) {
2017 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2018 } else if (netdev->flags & IFF_ALLMULTI) {
2019 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2020 } else if (netdev->flags & IFF_MULTICAST) {
2021 struct netdev_hw_addr *ha;
2024 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2025 netdev_for_each_mc_addr(ha, netdev) {
2026 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2027 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2030 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2031 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2035 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2037 spin_unlock_bh(&jme->rxmcs_lock);
2041 jme_change_mtu(struct net_device *netdev, int new_mtu)
2043 struct jme_adapter *jme = netdev_priv(netdev);
2045 if (new_mtu == jme->old_mtu)
2048 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2049 ((new_mtu) < IPV6_MIN_MTU))
2052 if (new_mtu > 4000) {
2053 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2054 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2055 jme_restart_rx_engine(jme);
2057 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2058 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2059 jme_restart_rx_engine(jme);
2062 if (new_mtu > 1900) {
2063 netdev->features &= ~(NETIF_F_HW_CSUM |
2067 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2068 netdev->features |= NETIF_F_HW_CSUM;
2069 if (test_bit(JME_FLAG_TSO, &jme->flags))
2070 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2073 netdev->mtu = new_mtu;
2074 jme_reset_link(jme);
2080 jme_tx_timeout(struct net_device *netdev)
2082 struct jme_adapter *jme = netdev_priv(netdev);
2085 jme_reset_phy_processor(jme);
2086 if (test_bit(JME_FLAG_SSET, &jme->flags))
2087 jme_set_settings(netdev, &jme->old_ecmd);
2090 * Force to Reset the link again
2092 jme_reset_link(jme);
2095 static inline void jme_pause_rx(struct jme_adapter *jme)
2097 atomic_dec(&jme->link_changing);
2099 jme_set_rx_pcc(jme, PCC_OFF);
2100 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101 JME_NAPI_DISABLE(jme);
2103 tasklet_disable(&jme->rxclean_task);
2104 tasklet_disable(&jme->rxempty_task);
2108 static inline void jme_resume_rx(struct jme_adapter *jme)
2110 struct dynpcc_info *dpi = &(jme->dpi);
2112 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2113 JME_NAPI_ENABLE(jme);
2115 tasklet_hi_enable(&jme->rxclean_task);
2116 tasklet_hi_enable(&jme->rxempty_task);
2119 dpi->attempt = PCC_P1;
2121 jme_set_rx_pcc(jme, PCC_P1);
2123 atomic_inc(&jme->link_changing);
2127 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2129 struct jme_adapter *jme = netdev_priv(netdev);
2137 jme_get_drvinfo(struct net_device *netdev,
2138 struct ethtool_drvinfo *info)
2140 struct jme_adapter *jme = netdev_priv(netdev);
2142 strcpy(info->driver, DRV_NAME);
2143 strcpy(info->version, DRV_VERSION);
2144 strcpy(info->bus_info, pci_name(jme->pdev));
2148 jme_get_regs_len(struct net_device *netdev)
2154 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2158 for (i = 0 ; i < len ; i += 4)
2159 p[i >> 2] = jread32(jme, reg + i);
2163 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2166 u16 *p16 = (u16 *)p;
2168 for (i = 0 ; i < reg_nr ; ++i)
2169 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2173 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2175 struct jme_adapter *jme = netdev_priv(netdev);
2176 u32 *p32 = (u32 *)p;
2178 memset(p, 0xFF, JME_REG_LEN);
2181 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2184 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2187 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2190 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2193 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2197 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2199 struct jme_adapter *jme = netdev_priv(netdev);
2201 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2202 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2204 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2205 ecmd->use_adaptive_rx_coalesce = false;
2206 ecmd->rx_coalesce_usecs = 0;
2207 ecmd->rx_max_coalesced_frames = 0;
2211 ecmd->use_adaptive_rx_coalesce = true;
2213 switch (jme->dpi.cur) {
2215 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2216 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2219 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2220 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2223 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2224 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2234 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2236 struct jme_adapter *jme = netdev_priv(netdev);
2237 struct dynpcc_info *dpi = &(jme->dpi);
2239 if (netif_running(netdev))
2242 if (ecmd->use_adaptive_rx_coalesce &&
2243 test_bit(JME_FLAG_POLL, &jme->flags)) {
2244 clear_bit(JME_FLAG_POLL, &jme->flags);
2245 jme->jme_rx = netif_rx;
2246 jme->jme_vlan_rx = vlan_hwaccel_rx;
2248 dpi->attempt = PCC_P1;
2250 jme_set_rx_pcc(jme, PCC_P1);
2251 jme_interrupt_mode(jme);
2252 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2253 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2254 set_bit(JME_FLAG_POLL, &jme->flags);
2255 jme->jme_rx = netif_receive_skb;
2256 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2257 jme_interrupt_mode(jme);
2264 jme_get_pauseparam(struct net_device *netdev,
2265 struct ethtool_pauseparam *ecmd)
2267 struct jme_adapter *jme = netdev_priv(netdev);
2270 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2271 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2273 spin_lock_bh(&jme->phy_lock);
2274 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2275 spin_unlock_bh(&jme->phy_lock);
2278 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2282 jme_set_pauseparam(struct net_device *netdev,
2283 struct ethtool_pauseparam *ecmd)
2285 struct jme_adapter *jme = netdev_priv(netdev);
2288 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2289 (ecmd->tx_pause != 0)) {
2292 jme->reg_txpfc |= TXPFC_PF_EN;
2294 jme->reg_txpfc &= ~TXPFC_PF_EN;
2296 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2299 spin_lock_bh(&jme->rxmcs_lock);
2300 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2301 (ecmd->rx_pause != 0)) {
2304 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2306 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2308 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2310 spin_unlock_bh(&jme->rxmcs_lock);
2312 spin_lock_bh(&jme->phy_lock);
2313 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2314 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2315 (ecmd->autoneg != 0)) {
2318 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2320 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2322 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2323 MII_ADVERTISE, val);
2325 spin_unlock_bh(&jme->phy_lock);
2331 jme_get_wol(struct net_device *netdev,
2332 struct ethtool_wolinfo *wol)
2334 struct jme_adapter *jme = netdev_priv(netdev);
2336 wol->supported = WAKE_MAGIC | WAKE_PHY;
2340 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2341 wol->wolopts |= WAKE_PHY;
2343 if (jme->reg_pmcs & PMCS_MFEN)
2344 wol->wolopts |= WAKE_MAGIC;
2349 jme_set_wol(struct net_device *netdev,
2350 struct ethtool_wolinfo *wol)
2352 struct jme_adapter *jme = netdev_priv(netdev);
2354 if (wol->wolopts & (WAKE_MAGICSECURE |
2363 if (wol->wolopts & WAKE_PHY)
2364 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2366 if (wol->wolopts & WAKE_MAGIC)
2367 jme->reg_pmcs |= PMCS_MFEN;
2369 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2375 jme_get_settings(struct net_device *netdev,
2376 struct ethtool_cmd *ecmd)
2378 struct jme_adapter *jme = netdev_priv(netdev);
2381 spin_lock_bh(&jme->phy_lock);
2382 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2383 spin_unlock_bh(&jme->phy_lock);
2388 jme_set_settings(struct net_device *netdev,
2389 struct ethtool_cmd *ecmd)
2391 struct jme_adapter *jme = netdev_priv(netdev);
2394 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2397 if (jme->mii_if.force_media &&
2398 ecmd->autoneg != AUTONEG_ENABLE &&
2399 (jme->mii_if.full_duplex != ecmd->duplex))
2402 spin_lock_bh(&jme->phy_lock);
2403 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2404 spin_unlock_bh(&jme->phy_lock);
2407 jme_reset_link(jme);
2410 set_bit(JME_FLAG_SSET, &jme->flags);
2411 jme->old_ecmd = *ecmd;
2418 jme_get_link(struct net_device *netdev)
2420 struct jme_adapter *jme = netdev_priv(netdev);
2421 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2425 jme_get_msglevel(struct net_device *netdev)
2427 struct jme_adapter *jme = netdev_priv(netdev);
2428 return jme->msg_enable;
2432 jme_set_msglevel(struct net_device *netdev, u32 value)
2434 struct jme_adapter *jme = netdev_priv(netdev);
2435 jme->msg_enable = value;
2439 jme_get_rx_csum(struct net_device *netdev)
2441 struct jme_adapter *jme = netdev_priv(netdev);
2442 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2446 jme_set_rx_csum(struct net_device *netdev, u32 on)
2448 struct jme_adapter *jme = netdev_priv(netdev);
2450 spin_lock_bh(&jme->rxmcs_lock);
2452 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2454 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2455 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2456 spin_unlock_bh(&jme->rxmcs_lock);
2462 jme_set_tx_csum(struct net_device *netdev, u32 on)
2464 struct jme_adapter *jme = netdev_priv(netdev);
2467 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2468 if (netdev->mtu <= 1900)
2469 netdev->features |= NETIF_F_HW_CSUM;
2471 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2472 netdev->features &= ~NETIF_F_HW_CSUM;
2479 jme_set_tso(struct net_device *netdev, u32 on)
2481 struct jme_adapter *jme = netdev_priv(netdev);
2484 set_bit(JME_FLAG_TSO, &jme->flags);
2485 if (netdev->mtu <= 1900)
2486 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2488 clear_bit(JME_FLAG_TSO, &jme->flags);
2489 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2496 jme_nway_reset(struct net_device *netdev)
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499 jme_restart_an(jme);
2504 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2509 val = jread32(jme, JME_SMBCSR);
2510 to = JME_SMB_BUSY_TIMEOUT;
2511 while ((val & SMBCSR_BUSY) && --to) {
2513 val = jread32(jme, JME_SMBCSR);
2516 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2520 jwrite32(jme, JME_SMBINTF,
2521 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2522 SMBINTF_HWRWN_READ |
2525 val = jread32(jme, JME_SMBINTF);
2526 to = JME_SMB_BUSY_TIMEOUT;
2527 while ((val & SMBINTF_HWCMD) && --to) {
2529 val = jread32(jme, JME_SMBINTF);
2532 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2536 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2540 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2545 val = jread32(jme, JME_SMBCSR);
2546 to = JME_SMB_BUSY_TIMEOUT;
2547 while ((val & SMBCSR_BUSY) && --to) {
2549 val = jread32(jme, JME_SMBCSR);
2552 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2556 jwrite32(jme, JME_SMBINTF,
2557 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2558 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2559 SMBINTF_HWRWN_WRITE |
2562 val = jread32(jme, JME_SMBINTF);
2563 to = JME_SMB_BUSY_TIMEOUT;
2564 while ((val & SMBINTF_HWCMD) && --to) {
2566 val = jread32(jme, JME_SMBINTF);
2569 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2577 jme_get_eeprom_len(struct net_device *netdev)
2579 struct jme_adapter *jme = netdev_priv(netdev);
2581 val = jread32(jme, JME_SMBCSR);
2582 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2586 jme_get_eeprom(struct net_device *netdev,
2587 struct ethtool_eeprom *eeprom, u8 *data)
2589 struct jme_adapter *jme = netdev_priv(netdev);
2590 int i, offset = eeprom->offset, len = eeprom->len;
2593 * ethtool will check the boundary for us
2595 eeprom->magic = JME_EEPROM_MAGIC;
2596 for (i = 0 ; i < len ; ++i)
2597 data[i] = jme_smb_read(jme, i + offset);
2603 jme_set_eeprom(struct net_device *netdev,
2604 struct ethtool_eeprom *eeprom, u8 *data)
2606 struct jme_adapter *jme = netdev_priv(netdev);
2607 int i, offset = eeprom->offset, len = eeprom->len;
2609 if (eeprom->magic != JME_EEPROM_MAGIC)
2613 * ethtool will check the boundary for us
2615 for (i = 0 ; i < len ; ++i)
2616 jme_smb_write(jme, i + offset, data[i]);
2621 static const struct ethtool_ops jme_ethtool_ops = {
2622 .get_drvinfo = jme_get_drvinfo,
2623 .get_regs_len = jme_get_regs_len,
2624 .get_regs = jme_get_regs,
2625 .get_coalesce = jme_get_coalesce,
2626 .set_coalesce = jme_set_coalesce,
2627 .get_pauseparam = jme_get_pauseparam,
2628 .set_pauseparam = jme_set_pauseparam,
2629 .get_wol = jme_get_wol,
2630 .set_wol = jme_set_wol,
2631 .get_settings = jme_get_settings,
2632 .set_settings = jme_set_settings,
2633 .get_link = jme_get_link,
2634 .get_msglevel = jme_get_msglevel,
2635 .set_msglevel = jme_set_msglevel,
2636 .get_rx_csum = jme_get_rx_csum,
2637 .set_rx_csum = jme_set_rx_csum,
2638 .set_tx_csum = jme_set_tx_csum,
2639 .set_tso = jme_set_tso,
2640 .set_sg = ethtool_op_set_sg,
2641 .nway_reset = jme_nway_reset,
2642 .get_eeprom_len = jme_get_eeprom_len,
2643 .get_eeprom = jme_get_eeprom,
2644 .set_eeprom = jme_set_eeprom,
2648 jme_pci_dma64(struct pci_dev *pdev)
2650 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2651 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2652 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2655 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2656 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2657 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2660 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2661 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2668 jme_phy_init(struct jme_adapter *jme)
2672 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2673 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2677 jme_check_hw_ver(struct jme_adapter *jme)
2681 chipmode = jread32(jme, JME_CHIPMODE);
2683 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2684 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2687 static const struct net_device_ops jme_netdev_ops = {
2688 .ndo_open = jme_open,
2689 .ndo_stop = jme_close,
2690 .ndo_validate_addr = eth_validate_addr,
2691 .ndo_start_xmit = jme_start_xmit,
2692 .ndo_set_mac_address = jme_set_macaddr,
2693 .ndo_set_multicast_list = jme_set_multi,
2694 .ndo_change_mtu = jme_change_mtu,
2695 .ndo_tx_timeout = jme_tx_timeout,
2696 .ndo_vlan_rx_register = jme_vlan_rx_register,
2699 static int __devinit
2700 jme_init_one(struct pci_dev *pdev,
2701 const struct pci_device_id *ent)
2703 int rc = 0, using_dac, i;
2704 struct net_device *netdev;
2705 struct jme_adapter *jme;
2710 * set up PCI device basics
2712 rc = pci_enable_device(pdev);
2714 pr_err("Cannot enable PCI device\n");
2718 using_dac = jme_pci_dma64(pdev);
2719 if (using_dac < 0) {
2720 pr_err("Cannot set PCI DMA Mask\n");
2722 goto err_out_disable_pdev;
2725 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2726 pr_err("No PCI resource region found\n");
2728 goto err_out_disable_pdev;
2731 rc = pci_request_regions(pdev, DRV_NAME);
2733 pr_err("Cannot obtain PCI resource region\n");
2734 goto err_out_disable_pdev;
2737 pci_set_master(pdev);
2740 * alloc and init net device
2742 netdev = alloc_etherdev(sizeof(*jme));
2744 pr_err("Cannot allocate netdev structure\n");
2746 goto err_out_release_regions;
2748 netdev->netdev_ops = &jme_netdev_ops;
2749 netdev->ethtool_ops = &jme_ethtool_ops;
2750 netdev->watchdog_timeo = TX_TIMEOUT;
2751 netdev->features = NETIF_F_HW_CSUM |
2755 NETIF_F_HW_VLAN_TX |
2758 netdev->features |= NETIF_F_HIGHDMA;
2760 SET_NETDEV_DEV(netdev, &pdev->dev);
2761 pci_set_drvdata(pdev, netdev);
2766 jme = netdev_priv(netdev);
2769 jme->jme_rx = netif_rx;
2770 jme->jme_vlan_rx = vlan_hwaccel_rx;
2771 jme->old_mtu = netdev->mtu = 1500;
2773 jme->tx_ring_size = 1 << 10;
2774 jme->tx_ring_mask = jme->tx_ring_size - 1;
2775 jme->tx_wake_threshold = 1 << 9;
2776 jme->rx_ring_size = 1 << 9;
2777 jme->rx_ring_mask = jme->rx_ring_size - 1;
2778 jme->msg_enable = JME_DEF_MSG_ENABLE;
2779 jme->regs = ioremap(pci_resource_start(pdev, 0),
2780 pci_resource_len(pdev, 0));
2782 pr_err("Mapping PCI resource region error\n");
2784 goto err_out_free_netdev;
2788 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2789 jwrite32(jme, JME_APMC, apmc);
2790 } else if (force_pseudohp) {
2791 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2792 jwrite32(jme, JME_APMC, apmc);
2795 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2797 spin_lock_init(&jme->phy_lock);
2798 spin_lock_init(&jme->macaddr_lock);
2799 spin_lock_init(&jme->rxmcs_lock);
2801 atomic_set(&jme->link_changing, 1);
2802 atomic_set(&jme->rx_cleaning, 1);
2803 atomic_set(&jme->tx_cleaning, 1);
2804 atomic_set(&jme->rx_empty, 1);
2806 tasklet_init(&jme->pcc_task,
2808 (unsigned long) jme);
2809 tasklet_init(&jme->linkch_task,
2810 jme_link_change_tasklet,
2811 (unsigned long) jme);
2812 tasklet_init(&jme->txclean_task,
2813 jme_tx_clean_tasklet,
2814 (unsigned long) jme);
2815 tasklet_init(&jme->rxclean_task,
2816 jme_rx_clean_tasklet,
2817 (unsigned long) jme);
2818 tasklet_init(&jme->rxempty_task,
2819 jme_rx_empty_tasklet,
2820 (unsigned long) jme);
2821 tasklet_disable_nosync(&jme->linkch_task);
2822 tasklet_disable_nosync(&jme->txclean_task);
2823 tasklet_disable_nosync(&jme->rxclean_task);
2824 tasklet_disable_nosync(&jme->rxempty_task);
2825 jme->dpi.cur = PCC_P1;
2828 jme->reg_rxcs = RXCS_DEFAULT;
2829 jme->reg_rxmcs = RXMCS_DEFAULT;
2831 jme->reg_pmcs = PMCS_MFEN;
2832 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2833 set_bit(JME_FLAG_TSO, &jme->flags);
2836 * Get Max Read Req Size from PCI Config Space
2838 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2839 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2840 switch (jme->mrrs) {
2842 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2845 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2848 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2853 * Must check before reset_mac_processor
2855 jme_check_hw_ver(jme);
2856 jme->mii_if.dev = netdev;
2858 jme->mii_if.phy_id = 0;
2859 for (i = 1 ; i < 32 ; ++i) {
2860 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2861 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2862 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2863 jme->mii_if.phy_id = i;
2868 if (!jme->mii_if.phy_id) {
2870 pr_err("Can not find phy_id\n");
2874 jme->reg_ghc |= GHC_LINK_POLL;
2876 jme->mii_if.phy_id = 1;
2878 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2879 jme->mii_if.supports_gmii = true;
2881 jme->mii_if.supports_gmii = false;
2882 jme->mii_if.mdio_read = jme_mdio_read;
2883 jme->mii_if.mdio_write = jme_mdio_write;
2886 jme_set_phyfifoa(jme);
2887 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2893 * Reset MAC processor and reload EEPROM for MAC Address
2895 jme_reset_mac_processor(jme);
2896 rc = jme_reload_eeprom(jme);
2898 pr_err("Reload eeprom for reading MAC Address error\n");
2901 jme_load_macaddr(netdev);
2904 * Tell stack that we are not ready to work until open()
2906 netif_carrier_off(netdev);
2907 netif_stop_queue(netdev);
2912 rc = register_netdev(netdev);
2914 pr_err("Cannot register net device\n");
2918 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2919 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2920 "JMC250 Gigabit Ethernet" :
2921 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2922 "JMC260 Fast Ethernet" : "Unknown",
2923 (jme->fpgaver != 0) ? " (FPGA)" : "",
2924 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2925 jme->rev, netdev->dev_addr);
2931 err_out_free_netdev:
2932 pci_set_drvdata(pdev, NULL);
2933 free_netdev(netdev);
2934 err_out_release_regions:
2935 pci_release_regions(pdev);
2936 err_out_disable_pdev:
2937 pci_disable_device(pdev);
2942 static void __devexit
2943 jme_remove_one(struct pci_dev *pdev)
2945 struct net_device *netdev = pci_get_drvdata(pdev);
2946 struct jme_adapter *jme = netdev_priv(netdev);
2948 unregister_netdev(netdev);
2950 pci_set_drvdata(pdev, NULL);
2951 free_netdev(netdev);
2952 pci_release_regions(pdev);
2953 pci_disable_device(pdev);
2959 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2961 struct net_device *netdev = pci_get_drvdata(pdev);
2962 struct jme_adapter *jme = netdev_priv(netdev);
2964 atomic_dec(&jme->link_changing);
2966 netif_device_detach(netdev);
2967 netif_stop_queue(netdev);
2970 tasklet_disable(&jme->txclean_task);
2971 tasklet_disable(&jme->rxclean_task);
2972 tasklet_disable(&jme->rxempty_task);
2974 if (netif_carrier_ok(netdev)) {
2975 if (test_bit(JME_FLAG_POLL, &jme->flags))
2976 jme_polling_mode(jme);
2978 jme_stop_pcc_timer(jme);
2979 jme_reset_ghc_speed(jme);
2980 jme_disable_rx_engine(jme);
2981 jme_disable_tx_engine(jme);
2982 jme_reset_mac_processor(jme);
2983 jme_free_rx_resources(jme);
2984 jme_free_tx_resources(jme);
2985 netif_carrier_off(netdev);
2989 tasklet_enable(&jme->txclean_task);
2990 tasklet_hi_enable(&jme->rxclean_task);
2991 tasklet_hi_enable(&jme->rxempty_task);
2993 pci_save_state(pdev);
2994 if (jme->reg_pmcs) {
2995 jme_set_100m_half(jme);
2997 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3000 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3002 pci_enable_wake(pdev, PCI_D3cold, true);
3006 pci_set_power_state(pdev, PCI_D3cold);
3012 jme_resume(struct pci_dev *pdev)
3014 struct net_device *netdev = pci_get_drvdata(pdev);
3015 struct jme_adapter *jme = netdev_priv(netdev);
3018 pci_restore_state(pdev);
3020 if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3022 jme_set_settings(netdev, &jme->old_ecmd);
3024 jme_reset_phy_processor(jme);
3028 netif_device_attach(netdev);
3030 atomic_inc(&jme->link_changing);
3032 jme_reset_link(jme);
3038 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3039 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3040 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3044 static struct pci_driver jme_driver = {
3046 .id_table = jme_pci_tbl,
3047 .probe = jme_init_one,
3048 .remove = __devexit_p(jme_remove_one),
3050 .suspend = jme_suspend,
3051 .resume = jme_resume,
3052 #endif /* CONFIG_PM */
3056 jme_init_module(void)
3058 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3059 return pci_register_driver(&jme_driver);
3063 jme_cleanup_module(void)
3065 pci_unregister_driver(&jme_driver);
3068 module_init(jme_init_module);
3069 module_exit(jme_cleanup_module);
3071 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3072 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3073 MODULE_LICENSE("GPL");
3074 MODULE_VERSION(DRV_VERSION);
3075 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);