2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Backdoor for changing "FIFO Threshold for processing next packet"
28 * ethtool -C eth1 adaptive-rx on adaptive-tx on \
29 * rx-usecs 250 rx-frames-low N
30 * N := 16 | 32 | 64 | 128
34 * Timeline before release:
35 * Stage 4: Basic feature support.
37 * - Implement Power Managemt related functions.
39 * Stage 5: Advanced offloading support.
41 * - Implement VLAN offloading.
43 * - Implement scatter-gather offloading.
44 * Use pci_map_page on scattered sk_buff for HIGHMEM support
45 * - Implement TCP Segement offloading.
46 * Due to TX FIFO size, we should turn off tso when mtu > 1500.
48 * Stage 6: CPU Load balancing.
51 * Along with multiple RX queue, for CPU load balancing.
54 * - Cleanup/re-orginize code, performence tuneing(alignment etc...).
55 * - Test and Release 1.0
58 * - Use NAPI instead of rx_tasklet?
59 * PCC Support Both Packet Counter and Timeout Interrupt for
60 * receive and transmit complete, does NAPI really needed?
61 * - Decode register dump for ethtool.
64 #include <linux/version.h>
65 #include <linux/module.h>
66 #include <linux/kernel.h>
67 #include <linux/pci.h>
68 #include <linux/netdevice.h>
69 #include <linux/etherdevice.h>
70 #include <linux/ethtool.h>
71 #include <linux/mii.h>
72 #include <linux/crc32.h>
73 #include <linux/delay.h>
76 #include <linux/ipv6.h>
77 #include <linux/tcp.h>
78 #include <linux/udp.h>
81 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
82 static struct net_device_stats *
83 jme_get_stats(struct net_device *netdev)
85 struct jme_adapter *jme = netdev_priv(netdev);
91 jme_mdio_read(struct net_device *netdev, int phy, int reg)
93 struct jme_adapter *jme = netdev_priv(netdev);
96 jwrite32(jme, JME_SMI, SMI_OP_REQ |
101 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
103 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
108 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
112 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
116 jme_mdio_write(struct net_device *netdev,
117 int phy, int reg, int val)
119 struct jme_adapter *jme = netdev_priv(netdev);
122 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
123 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
124 smi_phy_addr(phy) | smi_reg_addr(reg));
127 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
129 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
134 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
139 __always_inline static void
140 jme_reset_phy_processor(struct jme_adapter *jme)
144 jme_mdio_write(jme->dev,
146 MII_ADVERTISE, ADVERTISE_ALL |
147 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
149 jme_mdio_write(jme->dev,
152 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
154 val = jme_mdio_read(jme->dev,
158 jme_mdio_write(jme->dev,
160 MII_BMCR, val | BMCR_RESET);
166 __always_inline static void
167 jme_reset_mac_processor(struct jme_adapter *jme)
169 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
171 jwrite32(jme, JME_GHC, jme->reg_ghc);
172 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
173 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
174 jwrite32(jme, JME_WFODP, 0);
175 jwrite32(jme, JME_WFOI, 0);
176 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
177 jwrite32(jme, JME_GPREG1, 0);
180 __always_inline static void
181 jme_clear_pm(struct jme_adapter *jme)
183 jwrite32(jme, JME_PMCS, 0xFFFF0000);
184 pci_set_power_state(jme->pdev, PCI_D0);
188 jme_reload_eeprom(struct jme_adapter *jme)
193 val = jread32(jme, JME_SMBCSR);
195 if(val & SMBCSR_EEPROMD)
198 jwrite32(jme, JME_SMBCSR, val);
199 val |= SMBCSR_RELOAD;
200 jwrite32(jme, JME_SMBCSR, val);
203 for (i = JME_SMB_TIMEOUT; i > 0; --i)
206 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
211 jeprintk(jme->dev->name, "eeprom reload timeout\n");
222 jme_load_macaddr(struct net_device *netdev)
224 struct jme_adapter *jme = netdev_priv(netdev);
225 unsigned char macaddr[6];
228 spin_lock(&jme->macaddr_lock);
229 val = jread32(jme, JME_RXUMA_LO);
230 macaddr[0] = (val >> 0) & 0xFF;
231 macaddr[1] = (val >> 8) & 0xFF;
232 macaddr[2] = (val >> 16) & 0xFF;
233 macaddr[3] = (val >> 24) & 0xFF;
234 val = jread32(jme, JME_RXUMA_HI);
235 macaddr[4] = (val >> 0) & 0xFF;
236 macaddr[5] = (val >> 8) & 0xFF;
237 memcpy(netdev->dev_addr, macaddr, 6);
238 spin_unlock(&jme->macaddr_lock);
241 __always_inline static void
242 jme_set_rx_pcc(struct jme_adapter *jme, int p)
246 jwrite32(jme, JME_PCCRX0,
247 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
248 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
251 jwrite32(jme, JME_PCCRX0,
252 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
253 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
256 jwrite32(jme, JME_PCCRX0,
257 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
258 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
264 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
268 jme_start_irq(struct jme_adapter *jme)
270 register struct dynpcc_info *dpi = &(jme->dpi);
272 jme_set_rx_pcc(jme, PCC_P1);
274 dpi->attempt = PCC_P1;
277 jwrite32(jme, JME_PCCTX,
278 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
279 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
286 jwrite32(jme, JME_IENS, INTR_ENABLE);
289 __always_inline static void
290 jme_stop_irq(struct jme_adapter *jme)
295 jwrite32(jme, JME_IENC, INTR_ENABLE);
299 __always_inline static void
300 jme_enable_shadow(struct jme_adapter *jme)
304 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
307 __always_inline static void
308 jme_disable_shadow(struct jme_adapter *jme)
310 jwrite32(jme, JME_SHBA_LO, 0x0);
314 jme_check_link(struct net_device *netdev, int testonly)
316 struct jme_adapter *jme = netdev_priv(netdev);
317 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
321 phylink = jread32(jme, JME_PHY_LINK);
323 if (phylink & PHY_LINK_UP) {
324 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
326 * If we did not enable AN
327 * Speed/Duplex Info should be obtained from SMI
329 phylink = PHY_LINK_UP;
331 bmcr = jme_mdio_read(jme->dev,
336 phylink |= ((bmcr & BMCR_SPEED1000) &&
337 (bmcr & BMCR_SPEED100) == 0) ?
338 PHY_LINK_SPEED_1000M :
339 (bmcr & BMCR_SPEED100) ?
340 PHY_LINK_SPEED_100M :
343 phylink |= (bmcr & BMCR_FULLDPLX) ?
346 strcpy(linkmsg, "Forced: ");
350 * Keep polling for speed/duplex resolve complete
352 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
356 phylink = jread32(jme, JME_PHY_LINK);
361 jeprintk(netdev->name,
362 "Waiting speed resolve timeout.\n");
364 strcpy(linkmsg, "ANed: ");
367 if(jme->phylink == phylink) {
374 jme->phylink = phylink;
376 switch(phylink & PHY_LINK_SPEED_MASK) {
377 case PHY_LINK_SPEED_10M:
379 strcpy(linkmsg, "10 Mbps, ");
381 case PHY_LINK_SPEED_100M:
382 ghc = GHC_SPEED_100M;
383 strcpy(linkmsg, "100 Mbps, ");
385 case PHY_LINK_SPEED_1000M:
386 ghc = GHC_SPEED_1000M;
387 strcpy(linkmsg, "1000 Mbps, ");
393 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
395 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
399 if(phylink & PHY_LINK_MDI_STAT)
400 strcat(linkmsg, "MDI-X");
402 strcat(linkmsg, "MDI");
404 if(phylink & PHY_LINK_DUPLEX)
405 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
407 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
411 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
412 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
414 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
418 jwrite32(jme, JME_GHC, ghc);
420 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
421 netif_carrier_on(netdev);
427 jprintk(netdev->name, "Link is down.\n");
429 netif_carrier_off(netdev);
438 jme_alloc_txdesc(struct jme_adapter *jme,
441 struct jme_ring *txring = jme->txring;
444 idx = txring->next_to_use;
446 if(unlikely(atomic_read(&txring->nr_free) < nr_alloc))
449 atomic_sub(nr_alloc, &txring->nr_free);
451 if((txring->next_to_use += nr_alloc) >= RING_DESC_NR)
452 txring->next_to_use -= RING_DESC_NR;
458 jme_tx_csum(struct sk_buff *skb, unsigned mtu, __u8 *flags)
460 if(skb->ip_summed == CHECKSUM_PARTIAL) {
463 switch (skb->protocol) {
464 case __constant_htons(ETH_P_IP):
465 ip_proto = ip_hdr(skb)->protocol;
467 case __constant_htons(ETH_P_IPV6):
468 ip_proto = ipv6_hdr(skb)->nexthdr;
478 *flags |= TXFLAG_TCPCS;
481 *flags |= TXFLAG_UDPCS;
484 jeprintk("jme", "Error upper layer protocol.\n");
491 jme_set_new_txdesc(struct jme_adapter *jme,
494 struct jme_ring *txring = jme->txring;
495 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
496 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
502 idx = jme_alloc_txdesc(jme, nr_desc);
505 return NETDEV_TX_BUSY;
507 for(i = 1 ; i < nr_desc ; ++i) {
508 ctxdesc = txdesc + ((idx + i) & (RING_DESC_NR-1));
509 ctxbi = txbi + ((idx + i) & (RING_DESC_NR-1));
511 dmaaddr = pci_map_single(jme->pdev,
516 pci_dma_sync_single_for_device(jme->pdev,
523 ctxdesc->desc2.flags = TXFLAG_OWN;
524 if(jme->dev->features & NETIF_F_HIGHDMA)
525 ctxdesc->desc2.flags |= TXFLAG_64BIT;
526 ctxdesc->desc2.datalen = cpu_to_le16(skb->len);
527 ctxdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
528 ctxdesc->desc2.bufaddrl = cpu_to_le32(
529 (__u64)dmaaddr & 0xFFFFFFFFUL);
531 ctxbi->mapping = dmaaddr;
532 ctxbi->len = skb->len;
535 ctxdesc = txdesc + idx;
542 ctxdesc->desc1.pktsize = cpu_to_le16(skb->len);
544 * Set OWN bit at final.
545 * When kernel transmit faster than NIC.
546 * And NIC trying to send this descriptor before we tell
547 * it to start sending this TX queue.
548 * Other fields are already filled correctly.
551 flags = TXFLAG_OWN | TXFLAG_INT;
552 jme_tx_csum(skb, jme->dev->mtu, &flags);
553 ctxdesc->desc1.flags = flags;
555 * Set tx buffer info after telling NIC to send
556 * For better tx_clean timing
559 ctxbi->nr_desc = nr_desc;
562 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, nr_desc);
569 jme_setup_tx_resources(struct jme_adapter *jme)
571 struct jme_ring *txring = &(jme->txring[0]);
573 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
580 txring->dmaalloc = 0;
588 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
590 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
591 txring->next_to_use = 0;
592 txring->next_to_clean = 0;
593 atomic_set(&txring->nr_free, RING_DESC_NR);
596 * Initiallize Transmit Descriptors
598 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE);
599 memset(txring->bufinf, 0,
600 sizeof(struct jme_buffer_info) * RING_DESC_NR);
606 jme_free_tx_resources(struct jme_adapter *jme)
609 struct jme_ring *txring = &(jme->txring[0]);
610 struct jme_buffer_info *txbi = txring->bufinf;
613 for(i = 0 ; i < RING_DESC_NR ; ++i) {
614 txbi = txring->bufinf + i;
616 dev_kfree_skb(txbi->skb);
624 dma_free_coherent(&(jme->pdev->dev),
629 txring->alloc = NULL;
631 txring->dmaalloc = 0;
634 txring->next_to_use = 0;
635 txring->next_to_clean = 0;
636 atomic_set(&txring->nr_free, 0);
640 __always_inline static void
641 jme_enable_tx_engine(struct jme_adapter *jme)
646 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
649 * Setup TX Queue 0 DMA Bass Address
651 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
652 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
653 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
656 * Setup TX Descptor Count
658 jwrite32(jme, JME_TXQDC, RING_DESC_NR);
664 jwrite32(jme, JME_TXCS, jme->reg_txcs |
670 __always_inline static void
671 jme_disable_tx_engine(struct jme_adapter *jme)
679 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
681 val = jread32(jme, JME_TXCS);
682 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
685 val = jread32(jme, JME_TXCS);
689 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
690 jme_reset_mac_processor(jme);
697 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
699 struct jme_ring *rxring = jme->rxring;
700 register volatile struct rxdesc* rxdesc = rxring->desc;
701 struct jme_buffer_info *rxbi = rxring->bufinf;
707 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
708 rxdesc->desc1.bufaddrl = cpu_to_le32(
709 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
710 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
711 if(jme->dev->features & NETIF_F_HIGHDMA)
712 rxdesc->desc1.flags = RXFLAG_64BIT;
714 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
718 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
720 struct jme_ring *rxring = &(jme->rxring[0]);
721 struct jme_buffer_info *rxbi = rxring->bufinf;
722 unsigned long offset;
725 skb = netdev_alloc_skb(jme->dev,
726 jme->dev->mtu + RX_EXTRA_LEN);
730 if(unlikely(skb_is_nonlinear(skb))) {
731 dprintk(jme->dev->name,
732 "Allocated skb fragged(%d).\n",
733 skb_shinfo(skb)->nr_frags);
739 (unsigned long)(skb->data)
740 & ((unsigned long)RX_BUF_DMA_ALIGN - 1)))
741 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
745 rxbi->len = skb_tailroom(skb);
746 rxbi->mapping = pci_map_single(jme->pdev,
755 jme_free_rx_buf(struct jme_adapter *jme, int i)
757 struct jme_ring *rxring = &(jme->rxring[0]);
758 struct jme_buffer_info *rxbi = rxring->bufinf;
762 pci_unmap_single(jme->pdev,
766 dev_kfree_skb(rxbi->skb);
774 jme_free_rx_resources(struct jme_adapter *jme)
777 struct jme_ring *rxring = &(jme->rxring[0]);
780 for(i = 0 ; i < RING_DESC_NR ; ++i)
781 jme_free_rx_buf(jme, i);
783 dma_free_coherent(&(jme->pdev->dev),
787 rxring->alloc = NULL;
789 rxring->dmaalloc = 0;
792 rxring->next_to_use = 0;
793 rxring->next_to_clean = 0;
797 jme_setup_rx_resources(struct jme_adapter *jme)
800 struct jme_ring *rxring = &(jme->rxring[0]);
802 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
808 rxring->dmaalloc = 0;
816 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
818 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
819 rxring->next_to_use = 0;
820 rxring->next_to_clean = 0;
823 * Initiallize Receive Descriptors
825 for(i = 0 ; i < RING_DESC_NR ; ++i) {
826 if(unlikely(jme_make_new_rx_buf(jme, i))) {
827 jme_free_rx_resources(jme);
831 jme_set_clean_rxdesc(jme, i);
837 __always_inline static void
838 jme_enable_rx_engine(struct jme_adapter *jme)
841 * Setup RX DMA Bass Address
843 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
844 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
845 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
848 * Setup RX Descptor Count
850 jwrite32(jme, JME_RXQDC, RING_DESC_NR);
853 * Setup Unicast Filter
855 jme_set_multi(jme->dev);
861 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
867 __always_inline static void
868 jme_restart_rx_engine(struct jme_adapter *jme)
873 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
880 __always_inline static void
881 jme_disable_rx_engine(struct jme_adapter *jme)
889 val = jread32(jme, JME_RXCS);
891 jwrite32(jme, JME_RXCS, val);
893 val = jread32(jme, JME_RXCS);
894 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
897 val = jread32(jme, JME_RXCS);
901 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
906 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx, int summed)
908 struct jme_ring *rxring = &(jme->rxring[0]);
909 volatile struct rxdesc *rxdesc = rxring->desc;
910 struct jme_buffer_info *rxbi = rxring->bufinf;
918 pci_dma_sync_single_for_cpu(jme->pdev,
923 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
924 pci_dma_sync_single_for_device(jme->pdev,
929 ++(NET_STAT(jme).rx_dropped);
932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
940 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 if(le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST_MUL)
945 ++(NET_STAT(jme).multicast);
947 jme->dev->last_rx = jiffies;
948 NET_STAT(jme).rx_bytes += framesize;
949 ++(NET_STAT(jme).rx_packets);
952 jme_set_clean_rxdesc(jme, idx);
957 jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
959 if(unlikely((flags & RXWBFLAG_TCPON) &&
960 !(flags & RXWBFLAG_TCPCS))) {
961 csum_dbg(jme->dev->name, "TCP Checksum error.\n");
964 else if(unlikely((flags & RXWBFLAG_UDPON) &&
965 !(flags & RXWBFLAG_UDPCS))) {
966 csum_dbg(jme->dev->name, "UDP Checksum error.\n");
969 else if(unlikely((flags & RXWBFLAG_IPV4) &&
970 !(flags & RXWBFLAG_IPCS))) {
971 csum_dbg(jme->dev->name, "IPV4 Checksum error.\n");
980 jme_process_receive(struct jme_adapter *jme, int limit)
982 struct jme_ring *rxring = &(jme->rxring[0]);
983 volatile struct rxdesc *rxdesc = rxring->desc;
984 int i, j, ccnt, desccnt;
986 i = rxring->next_to_clean;
989 rxdesc = rxring->desc;
992 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
993 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
996 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
998 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
1000 if(unlikely(desccnt > 1 ||
1001 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
1002 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
1004 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
1005 ++(NET_STAT(jme).rx_crc_errors);
1006 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
1007 ++(NET_STAT(jme).rx_fifo_errors);
1009 ++(NET_STAT(jme).rx_errors);
1012 rx_dbg(jme->dev->name,
1013 "RX: More than one(%d) descriptor, "
1015 desccnt, le16_to_cpu(rxdesc->descwb.framesize));
1016 limit -= desccnt - 1;
1019 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
1020 jme_set_clean_rxdesc(jme, j);
1022 if(unlikely(++j == RING_DESC_NR))
1028 jme_alloc_and_feed_skb(jme, i,
1029 (rxdesc->descwb.flags &
1035 if((i += desccnt) >= RING_DESC_NR)
1040 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
1041 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
1042 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
1045 rxring->next_to_clean = i;
1047 return limit > 0 ? limit : 0;
1052 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1054 if(likely(atmp == dpi->cur))
1057 if(dpi->attempt == atmp) {
1061 dpi->attempt = atmp;
1068 jme_dynamic_pcc(struct jme_adapter *jme)
1070 register struct dynpcc_info *dpi = &(jme->dpi);
1072 if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1073 jme_attempt_pcc(dpi, PCC_P3);
1074 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P2_THRESHOLD
1075 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1076 jme_attempt_pcc(dpi, PCC_P2);
1078 jme_attempt_pcc(dpi, PCC_P1);
1080 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 20)) {
1081 jme_set_rx_pcc(jme, dpi->attempt);
1082 dpi->cur = dpi->attempt;
1088 jme_start_pcc_timer(struct jme_adapter *jme)
1090 struct dynpcc_info *dpi = &(jme->dpi);
1091 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1092 dpi->last_pkts = NET_STAT(jme).rx_packets;
1094 jwrite32(jme, JME_TMCSR,
1095 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1099 jme_pcc_tasklet(unsigned long arg)
1101 struct jme_adapter *jme = (struct jme_adapter*)arg;
1102 struct net_device *netdev = jme->dev;
1104 if(netif_queue_stopped(netdev)) {
1105 jwrite32(jme, JME_TMCSR, 0);
1108 jme_dynamic_pcc(jme);
1109 jme_start_pcc_timer(jme);
1113 jme_link_change_tasklet(unsigned long arg)
1115 struct jme_adapter *jme = (struct jme_adapter*)arg;
1116 struct net_device *netdev = jme->dev;
1117 int timeout = WAIT_TASKLET_TIMEOUT;
1120 if(!atomic_dec_and_test(&jme->link_changing))
1123 if(jme_check_link(netdev, 1) && jme->oldmtu == netdev->mtu)
1126 jme->oldmtu = netdev->mtu;
1127 netif_stop_queue(netdev);
1129 while(--timeout > 0 &&
1131 atomic_read(&jme->rx_cleaning) != 1 ||
1132 atomic_read(&jme->tx_cleaning) != 1
1138 if(netif_carrier_ok(netdev)) {
1139 jme_reset_mac_processor(jme);
1140 jme_free_rx_resources(jme);
1141 jme_free_tx_resources(jme);
1144 jme_check_link(netdev, 0);
1145 if(netif_carrier_ok(netdev)) {
1146 rc = jme_setup_rx_resources(jme);
1148 jeprintk(netdev->name,
1149 "Allocating resources for RX error"
1150 ", Device STOPPED!\n");
1155 rc = jme_setup_tx_resources(jme);
1157 jeprintk(netdev->name,
1158 "Allocating resources for TX error"
1159 ", Device STOPPED!\n");
1160 goto err_out_free_rx_resources;
1163 jme_enable_rx_engine(jme);
1164 jme_enable_tx_engine(jme);
1166 netif_start_queue(netdev);
1167 jme_start_pcc_timer(jme);
1172 err_out_free_rx_resources:
1173 jme_free_rx_resources(jme);
1175 atomic_inc(&jme->link_changing);
1179 jme_rx_clean_tasklet(unsigned long arg)
1181 struct jme_adapter *jme = (struct jme_adapter*)arg;
1182 struct dynpcc_info *dpi = &(jme->dpi);
1184 if(unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1187 if(unlikely(atomic_read(&jme->link_changing) != 1))
1190 if(unlikely(netif_queue_stopped(jme->dev)))
1193 jme_process_receive(jme, RING_DESC_NR);
1197 atomic_inc(&jme->rx_cleaning);
1201 jme_rx_empty_tasklet(unsigned long arg)
1203 struct jme_adapter *jme = (struct jme_adapter*)arg;
1205 if(unlikely(atomic_read(&jme->link_changing) != 1))
1208 if(unlikely(netif_queue_stopped(jme->dev)))
1211 jme_rx_clean_tasklet(arg);
1212 jme_restart_rx_engine(jme);
1216 jme_tx_clean_tasklet(unsigned long arg)
1218 struct jme_adapter *jme = (struct jme_adapter*)arg;
1219 struct jme_ring *txring = &(jme->txring[0]);
1220 volatile struct txdesc *txdesc = txring->desc;
1221 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1222 int i, j, cnt = 0, max, err;
1224 if(unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1227 if(unlikely(atomic_read(&jme->link_changing) != 1))
1230 if(unlikely(netif_queue_stopped(jme->dev)))
1233 max = RING_DESC_NR - atomic_read(&txring->nr_free);
1235 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1237 for(i = txring->next_to_clean ; cnt < max ; ) {
1241 if(ctxbi->skb && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
1243 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1245 tx_dbg(jme->dev->name,
1246 "Tx Tasklet: Clean %d+%d\n",
1249 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1250 ttxbi = txbi + ((i + j) & (RING_DESC_NR - 1));
1251 txdesc[(i+j)&(RING_DESC_NR-1)].dw[0] = 0;
1253 pci_unmap_single(jme->pdev,
1259 NET_STAT(jme).tx_bytes += ttxbi->len;
1265 dev_kfree_skb(ctxbi->skb);
1268 cnt += ctxbi->nr_desc;
1271 ++(NET_STAT(jme).tx_carrier_errors);
1273 ++(NET_STAT(jme).tx_packets);
1277 tx_dbg(jme->dev->name,
1279 " Stoped due to no skb.\n");
1281 tx_dbg(jme->dev->name,
1283 "Stoped due to not done.\n");
1287 if(unlikely((i += ctxbi->nr_desc) >= RING_DESC_NR))
1293 tx_dbg(jme->dev->name,
1294 "Tx Tasklet: Stop %d Jiffies %lu\n",
1296 txring->next_to_clean = i;
1298 atomic_add(cnt, &txring->nr_free);
1301 atomic_inc(&jme->tx_cleaning);
1305 jme_intr_msi(struct jme_adapter *jme, __u32 intrstat)
1310 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1312 if(intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1313 tasklet_schedule(&jme->linkch_task);
1317 if(intrstat & INTR_TMINTR)
1318 tasklet_schedule(&jme->pcc_task);
1320 if(intrstat & INTR_RX0EMP)
1321 tasklet_schedule(&jme->rxempty_task);
1323 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1324 tasklet_schedule(&jme->rxclean_task);
1326 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1327 tasklet_schedule(&jme->txclean_task);
1329 if((intrstat & ~INTR_ENABLE) != 0) {
1331 * Some interrupt not handled
1332 * but not enabled also (for debug)
1338 * Deassert interrupts
1340 jwrite32f(jme, JME_IEVE, intrstat);
1343 * Re-enable interrupt
1345 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1351 jme_intr(int irq, void *dev_id)
1353 struct net_device *netdev = dev_id;
1354 struct jme_adapter *jme = netdev_priv(netdev);
1355 irqreturn_t rc = IRQ_HANDLED;
1358 intrstat = jread32(jme, JME_IEVE);
1361 * Check if it's really an interrupt for us
1363 if(unlikely(intrstat == 0)) {
1369 * Check if the device still exist
1371 if(unlikely(intrstat == ~((typeof(intrstat))0))) {
1377 * Allow one interrupt handling at a time
1379 if(unlikely(!atomic_dec_and_test(&jme->intr_sem)))
1382 jme_intr_msi(jme, intrstat);
1386 * Enable next interrupt handling
1388 atomic_inc(&jme->intr_sem);
1395 jme_msi(int irq, void *dev_id)
1397 struct net_device *netdev = dev_id;
1398 struct jme_adapter *jme = netdev_priv(netdev);
1401 pci_dma_sync_single_for_cpu(jme->pdev,
1403 sizeof(__u32) * SHADOW_REG_NR,
1404 PCI_DMA_FROMDEVICE);
1405 intrstat = jme->shadow_regs[SHADOW_IEVE];
1406 jme->shadow_regs[SHADOW_IEVE] = 0;
1408 jme_intr_msi(jme, intrstat);
1415 jme_reset_link(struct jme_adapter *jme)
1417 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1421 jme_restart_an(struct jme_adapter *jme)
1424 unsigned long flags;
1426 spin_lock_irqsave(&jme->phy_lock, flags);
1427 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1428 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1429 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1430 spin_unlock_irqrestore(&jme->phy_lock, flags);
1434 jme_request_irq(struct jme_adapter *jme)
1437 struct net_device *netdev = jme->dev;
1438 irq_handler_t handler = jme_intr;
1439 int irq_flags = IRQF_SHARED;
1441 if (!pci_enable_msi(jme->pdev)) {
1442 jme->flags |= JME_FLAG_MSI;
1447 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1450 jeprintk(netdev->name,
1451 "Unable to allocate %s interrupt (return: %d)\n",
1452 jme->flags & JME_FLAG_MSI ? "MSI":"INTx",
1455 if(jme->flags & JME_FLAG_MSI) {
1456 pci_disable_msi(jme->pdev);
1457 jme->flags &= ~JME_FLAG_MSI;
1461 netdev->irq = jme->pdev->irq;
1468 jme_free_irq(struct jme_adapter *jme)
1470 free_irq(jme->pdev->irq, jme->dev);
1471 if (jme->flags & JME_FLAG_MSI) {
1472 pci_disable_msi(jme->pdev);
1473 jme->flags &= ~JME_FLAG_MSI;
1474 jme->dev->irq = jme->pdev->irq;
1479 jme_open(struct net_device *netdev)
1481 struct jme_adapter *jme = netdev_priv(netdev);
1482 int rc, timeout = 100;
1487 atomic_read(&jme->link_changing) != 1 ||
1488 atomic_read(&jme->rx_cleaning) != 1 ||
1489 atomic_read(&jme->tx_cleaning) != 1
1499 jme_reset_mac_processor(jme);
1501 rc = jme_request_irq(jme);
1505 jme_enable_shadow(jme);
1507 jme_restart_an(jme);
1512 netif_stop_queue(netdev);
1513 netif_carrier_off(netdev);
1518 jme_close(struct net_device *netdev)
1520 struct jme_adapter *jme = netdev_priv(netdev);
1522 netif_stop_queue(netdev);
1523 netif_carrier_off(netdev);
1526 jme_disable_shadow(jme);
1529 tasklet_kill(&jme->linkch_task);
1530 tasklet_kill(&jme->txclean_task);
1531 tasklet_kill(&jme->rxclean_task);
1532 tasklet_kill(&jme->rxempty_task);
1534 jme_reset_mac_processor(jme);
1535 jme_free_rx_resources(jme);
1536 jme_free_tx_resources(jme);
1542 * This function is already protected by netif_tx_lock()
1545 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1547 struct jme_adapter *jme = netdev_priv(netdev);
1550 if(unlikely(netif_queue_stopped(jme->dev)))
1551 return NETDEV_TX_BUSY;
1555 ("jme", "Frags: %d Headlen: %d Len: %d Sum:%d\n",
1556 skb_shinfo(skb)->nr_frags,
1563 rc = jme_set_new_txdesc(jme, skb);
1565 if(unlikely(rc != NETDEV_TX_OK))
1568 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1569 TXCS_SELECT_QUEUE0 |
1572 netdev->trans_start = jiffies;
1574 return NETDEV_TX_OK;
1578 jme_set_macaddr(struct net_device *netdev, void *p)
1580 struct jme_adapter *jme = netdev_priv(netdev);
1581 struct sockaddr *addr = p;
1584 if(netif_running(netdev))
1587 spin_lock(&jme->macaddr_lock);
1588 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1590 val = addr->sa_data[3] << 24 |
1591 addr->sa_data[2] << 16 |
1592 addr->sa_data[1] << 8 |
1594 jwrite32(jme, JME_RXUMA_LO, val);
1595 val = addr->sa_data[5] << 8 |
1597 jwrite32(jme, JME_RXUMA_HI, val);
1598 spin_unlock(&jme->macaddr_lock);
1604 jme_set_multi(struct net_device *netdev)
1606 struct jme_adapter *jme = netdev_priv(netdev);
1607 u32 mc_hash[2] = {};
1609 unsigned long flags;
1611 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1613 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1615 if (netdev->flags & IFF_PROMISC) {
1616 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1618 else if (netdev->flags & IFF_ALLMULTI) {
1619 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1621 else if(netdev->flags & IFF_MULTICAST) {
1622 struct dev_mc_list *mclist;
1625 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1626 for (i = 0, mclist = netdev->mc_list;
1627 mclist && i < netdev->mc_count;
1628 ++i, mclist = mclist->next) {
1630 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1631 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1634 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1635 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1639 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1641 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1645 jme_change_mtu(struct net_device *netdev, int new_mtu)
1647 struct jme_adapter *jme = netdev_priv(netdev);
1649 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
1650 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
1653 if(new_mtu > 4000) {
1654 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1655 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1656 jme_restart_rx_engine(jme);
1659 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1660 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1661 jme_restart_rx_engine(jme);
1664 if(new_mtu > 1900) {
1665 netdev->features &= ~NETIF_F_HW_CSUM;
1668 netdev->features |= NETIF_F_HW_CSUM;
1671 netdev->mtu = new_mtu;
1672 jme_reset_link(jme);
1678 jme_tx_timeout(struct net_device *netdev)
1680 struct jme_adapter *jme = netdev_priv(netdev);
1684 * And the link change will reinitiallize all RX/TX resources
1686 jme_restart_an(jme);
1690 jme_get_drvinfo(struct net_device *netdev,
1691 struct ethtool_drvinfo *info)
1693 struct jme_adapter *jme = netdev_priv(netdev);
1695 strcpy(info->driver, DRV_NAME);
1696 strcpy(info->version, DRV_VERSION);
1697 strcpy(info->bus_info, pci_name(jme->pdev));
1701 jme_get_regs_len(struct net_device *netdev)
1707 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1711 for(i = 0 ; i < len ; i += 4)
1712 p[i >> 2] = jread32(jme, reg + i);
1717 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1719 struct jme_adapter *jme = netdev_priv(netdev);
1720 __u32 *p32 = (__u32*)p;
1722 memset(p, 0, 0x400);
1725 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1728 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1731 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1734 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1739 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1741 struct jme_adapter *jme = netdev_priv(netdev);
1743 ecmd->use_adaptive_rx_coalesce = true;
1744 ecmd->tx_coalesce_usecs = PCC_TX_TO;
1745 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1747 switch(jme->dpi.cur) {
1749 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1750 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1753 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1754 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1757 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1758 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1768 * It's not actually for coalesce.
1769 * It changes internell FIFO related setting for testing.
1772 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1774 struct jme_adapter *jme = netdev_priv(netdev);
1776 if(ecmd->use_adaptive_rx_coalesce &&
1777 ecmd->use_adaptive_tx_coalesce &&
1778 ecmd->rx_coalesce_usecs == 250 &&
1779 (ecmd->rx_max_coalesced_frames_low == 16 ||
1780 ecmd->rx_max_coalesced_frames_low == 32 ||
1781 ecmd->rx_max_coalesced_frames_low == 64 ||
1782 ecmd->rx_max_coalesced_frames_low == 128)) {
1783 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
1784 switch(ecmd->rx_max_coalesced_frames_low) {
1786 jme->reg_rxcs |= RXCS_FIFOTHNP_16QW;
1789 jme->reg_rxcs |= RXCS_FIFOTHNP_32QW;
1792 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
1796 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
1798 jme_restart_rx_engine(jme);
1808 jme_get_pauseparam(struct net_device *netdev,
1809 struct ethtool_pauseparam *ecmd)
1811 struct jme_adapter *jme = netdev_priv(netdev);
1812 unsigned long flags;
1815 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1816 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1818 spin_lock_irqsave(&jme->phy_lock, flags);
1819 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1820 spin_unlock_irqrestore(&jme->phy_lock, flags);
1821 ecmd->autoneg = (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1825 jme_set_pauseparam(struct net_device *netdev,
1826 struct ethtool_pauseparam *ecmd)
1828 struct jme_adapter *jme = netdev_priv(netdev);
1829 unsigned long flags;
1832 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1833 (ecmd->tx_pause != 0)) {
1836 jme->reg_txpfc |= TXPFC_PF_EN;
1838 jme->reg_txpfc &= ~TXPFC_PF_EN;
1840 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
1843 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1844 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
1845 (ecmd->rx_pause != 0)) {
1848 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
1850 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
1852 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1854 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1856 spin_lock_irqsave(&jme->phy_lock, flags);
1857 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1858 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
1859 (ecmd->autoneg != 0)) {
1862 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1864 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1866 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, val);
1868 spin_unlock_irqrestore(&jme->phy_lock, flags);
1874 jme_get_settings(struct net_device *netdev,
1875 struct ethtool_cmd *ecmd)
1877 struct jme_adapter *jme = netdev_priv(netdev);
1879 unsigned long flags;
1881 spin_lock_irqsave(&jme->phy_lock, flags);
1882 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
1883 spin_unlock_irqrestore(&jme->phy_lock, flags);
1888 jme_set_settings(struct net_device *netdev,
1889 struct ethtool_cmd *ecmd)
1891 struct jme_adapter *jme = netdev_priv(netdev);
1893 unsigned long flags;
1895 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
1898 if(jme->mii_if.force_media &&
1899 ecmd->autoneg != AUTONEG_ENABLE &&
1900 (jme->mii_if.full_duplex != ecmd->duplex))
1903 spin_lock_irqsave(&jme->phy_lock, flags);
1904 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
1905 spin_unlock_irqrestore(&jme->phy_lock, flags);
1908 jme_reset_link(jme);
1914 jme_get_link(struct net_device *netdev)
1916 struct jme_adapter *jme = netdev_priv(netdev);
1917 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
1921 jme_get_rx_csum(struct net_device *netdev)
1923 struct jme_adapter *jme = netdev_priv(netdev);
1925 return jme->reg_rxmcs & RXMCS_CHECKSUM;
1929 jme_set_rx_csum(struct net_device *netdev, u32 on)
1931 struct jme_adapter *jme = netdev_priv(netdev);
1932 unsigned long flags;
1934 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1936 jme->reg_rxmcs |= RXMCS_CHECKSUM;
1938 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
1939 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1940 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1946 jme_set_tx_csum(struct net_device *netdev, u32 on)
1949 netdev->features |= NETIF_F_HW_CSUM;
1951 netdev->features &= ~NETIF_F_HW_CSUM;
1957 jme_nway_reset(struct net_device *netdev)
1959 struct jme_adapter *jme = netdev_priv(netdev);
1960 jme_restart_an(jme);
1964 static const struct ethtool_ops jme_ethtool_ops = {
1965 .get_drvinfo = jme_get_drvinfo,
1966 .get_regs_len = jme_get_regs_len,
1967 .get_regs = jme_get_regs,
1968 .get_coalesce = jme_get_coalesce,
1969 .set_coalesce = jme_set_coalesce,
1970 .get_pauseparam = jme_get_pauseparam,
1971 .set_pauseparam = jme_set_pauseparam,
1972 .get_settings = jme_get_settings,
1973 .set_settings = jme_set_settings,
1974 .get_link = jme_get_link,
1975 .get_rx_csum = jme_get_rx_csum,
1976 .set_rx_csum = jme_set_rx_csum,
1977 .set_tx_csum = jme_set_tx_csum,
1978 .nway_reset = jme_nway_reset,
1982 jme_pci_dma64(struct pci_dev *pdev)
1984 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
1985 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1988 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
1989 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
1992 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
1993 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
1999 static int __devinit
2000 jme_init_one(struct pci_dev *pdev,
2001 const struct pci_device_id *ent)
2003 int rc = 0, using_dac;
2004 struct net_device *netdev;
2005 struct jme_adapter *jme;
2008 * set up PCI device basics
2010 rc = pci_enable_device(pdev);
2012 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
2016 using_dac = jme_pci_dma64(pdev);
2018 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
2020 goto err_out_disable_pdev;
2023 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2024 printk(KERN_ERR PFX "No PCI resource region found.\n");
2026 goto err_out_disable_pdev;
2029 rc = pci_request_regions(pdev, DRV_NAME);
2031 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
2032 goto err_out_disable_pdev;
2035 pci_set_master(pdev);
2038 * alloc and init net device
2040 netdev = alloc_etherdev(sizeof(*jme));
2043 goto err_out_release_regions;
2045 netdev->open = jme_open;
2046 netdev->stop = jme_close;
2047 netdev->hard_start_xmit = jme_start_xmit;
2048 netdev->set_mac_address = jme_set_macaddr;
2049 netdev->set_multicast_list = jme_set_multi;
2050 netdev->change_mtu = jme_change_mtu;
2051 netdev->ethtool_ops = &jme_ethtool_ops;
2052 netdev->tx_timeout = jme_tx_timeout;
2053 netdev->watchdog_timeo = TX_TIMEOUT;
2054 NETDEV_GET_STATS(netdev, &jme_get_stats);
2055 netdev->features = NETIF_F_HW_CSUM;
2057 netdev->features |= NETIF_F_HIGHDMA;
2059 SET_NETDEV_DEV(netdev, &pdev->dev);
2060 pci_set_drvdata(pdev, netdev);
2065 jme = netdev_priv(netdev);
2068 jme->oldmtu = netdev->mtu = 1500;
2070 jme->regs = ioremap(pci_resource_start(pdev, 0),
2071 pci_resource_len(pdev, 0));
2074 goto err_out_free_netdev;
2076 jme->shadow_regs = pci_alloc_consistent(pdev,
2077 sizeof(__u32) * SHADOW_REG_NR,
2078 &(jme->shadow_dma));
2079 if (!(jme->shadow_regs)) {
2084 spin_lock_init(&jme->phy_lock);
2085 spin_lock_init(&jme->macaddr_lock);
2086 spin_lock_init(&jme->rxmcs_lock);
2088 atomic_set(&jme->intr_sem, 1);
2089 atomic_set(&jme->link_changing, 1);
2090 atomic_set(&jme->rx_cleaning, 1);
2091 atomic_set(&jme->tx_cleaning, 1);
2093 tasklet_init(&jme->pcc_task,
2095 (unsigned long) jme);
2096 tasklet_init(&jme->linkch_task,
2097 &jme_link_change_tasklet,
2098 (unsigned long) jme);
2099 tasklet_init(&jme->txclean_task,
2100 &jme_tx_clean_tasklet,
2101 (unsigned long) jme);
2102 tasklet_init(&jme->rxclean_task,
2103 &jme_rx_clean_tasklet,
2104 (unsigned long) jme);
2105 tasklet_init(&jme->rxempty_task,
2106 &jme_rx_empty_tasklet,
2107 (unsigned long) jme);
2108 jme->mii_if.dev = netdev;
2109 jme->mii_if.phy_id = 1;
2110 jme->mii_if.supports_gmii = 1;
2111 jme->mii_if.mdio_read = jme_mdio_read;
2112 jme->mii_if.mdio_write = jme_mdio_write;
2114 jme->dpi.cur = PCC_P1;
2116 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
2117 jme->reg_rxcs = RXCS_DEFAULT;
2118 jme->reg_rxmcs = RXMCS_DEFAULT;
2121 * Get Max Read Req Size from PCI Config Space
2123 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
2126 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2129 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2132 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2138 * Reset MAC processor and reload EEPROM for MAC Address
2141 jme_reset_phy_processor(jme);
2142 jme_reset_mac_processor(jme);
2143 rc = jme_reload_eeprom(jme);
2146 "Rload eeprom for reading MAC Address error.\n");
2147 goto err_out_free_shadow;
2149 jme_load_macaddr(netdev);
2153 * Tell stack that we are not ready to work until open()
2155 netif_carrier_off(netdev);
2156 netif_stop_queue(netdev);
2161 rc = register_netdev(netdev);
2163 printk(KERN_ERR PFX "Cannot register net device.\n");
2164 goto err_out_free_shadow;
2167 jprintk(netdev->name,
2168 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
2169 netdev->dev_addr[0],
2170 netdev->dev_addr[1],
2171 netdev->dev_addr[2],
2172 netdev->dev_addr[3],
2173 netdev->dev_addr[4],
2174 netdev->dev_addr[5]);
2178 err_out_free_shadow:
2179 pci_free_consistent(pdev,
2180 sizeof(__u32) * SHADOW_REG_NR,
2185 err_out_free_netdev:
2186 pci_set_drvdata(pdev, NULL);
2187 free_netdev(netdev);
2188 err_out_release_regions:
2189 pci_release_regions(pdev);
2190 err_out_disable_pdev:
2191 pci_disable_device(pdev);
2196 static void __devexit
2197 jme_remove_one(struct pci_dev *pdev)
2199 struct net_device *netdev = pci_get_drvdata(pdev);
2200 struct jme_adapter *jme = netdev_priv(netdev);
2202 unregister_netdev(netdev);
2203 pci_free_consistent(pdev,
2204 sizeof(__u32) * SHADOW_REG_NR,
2208 pci_set_drvdata(pdev, NULL);
2209 free_netdev(netdev);
2210 pci_release_regions(pdev);
2211 pci_disable_device(pdev);
2215 static struct pci_device_id jme_pci_tbl[] = {
2216 { PCI_VDEVICE(JMICRON, 0x250) },
2220 static struct pci_driver jme_driver = {
2222 .id_table = jme_pci_tbl,
2223 .probe = jme_init_one,
2224 .remove = __devexit_p(jme_remove_one),
2227 .suspend = jme_suspend,
2228 .resume = jme_resume,
2229 #endif /* CONFIG_PM */
2234 jme_init_module(void)
2236 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2237 "driver version %s\n", DRV_VERSION);
2238 return pci_register_driver(&jme_driver);
2242 jme_cleanup_module(void)
2244 pci_unregister_driver(&jme_driver);
2247 module_init(jme_init_module);
2248 module_exit(jme_cleanup_module);
2250 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2251 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2252 MODULE_LICENSE("GPL");
2253 MODULE_VERSION(DRV_VERSION);
2254 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);