jme.c

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/mii.h>
  34 #include <linux/crc32.h>
  35 #include <linux/delay.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/in.h>
  38 #include <linux/ip.h>
  39 #include <linux/ipv6.h>
  40 #include <linux/tcp.h>
  41 #include <linux/udp.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/slab.h>
  44 #include <net/ip6_checksum.h>
  45 #include "jme.h"
  46
  47 static int force_pseudohp = -1;
  48 static int no_pseudohp = -1;
  49 static int no_extplug = -1;
  50 module_param(force_pseudohp, int, 0);
  51 MODULE_PARM_DESC(force_pseudohp,
  52         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  53 module_param(no_pseudohp, int, 0);
  54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  55 module_param(no_extplug, int, 0);
  56 MODULE_PARM_DESC(no_extplug,
  57         "Do not use external plug signal for pseudo hot-plug.");
  58
  59 static int
  60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
  61 {
  62         struct jme_adapter *jme = netdev_priv(netdev);
  63         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  64
  65 read_again:
  66         jwrite32(jme, JME_SMI, SMI_OP_REQ |
  67                                 smi_phy_addr(phy) |
  68                                 smi_reg_addr(reg));
  69
  70         wmb();
  71         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  72                 udelay(20);
  73                 val = jread32(jme, JME_SMI);
  74                 if ((val & SMI_OP_REQ) == 0)
  75                         break;
  76         }
  77
  78         if (i == 0) {
  79                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
  80                 return 0;
  81         }
  82
  83         if (again--)
  84                 goto read_again;
  85
  86         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  87 }
  88
  89 static void
  90 jme_mdio_write(struct net_device *netdev,
  91                                 int phy, int reg, int val)
  92 {
  93         struct jme_adapter *jme = netdev_priv(netdev);
  94         int i;
  95
  96         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  97                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  98                 smi_phy_addr(phy) | smi_reg_addr(reg));
  99
 100         wmb();
 101         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
 102                 udelay(20);
 103                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
 104                         break;
 105         }
 106
 107         if (i == 0)
 108                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
 109 }
 110
 111 static inline void
 112 jme_reset_phy_processor(struct jme_adapter *jme)
 113 {
 114         u32 val;
 115
 116         jme_mdio_write(jme->dev,
 117                         jme->mii_if.phy_id,
 118                         MII_ADVERTISE, ADVERTISE_ALL |
 119                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 120
 121         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
 122                 jme_mdio_write(jme->dev,
 123                                 jme->mii_if.phy_id,
 124                                 MII_CTRL1000,
 125                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 126
 127         val = jme_mdio_read(jme->dev,
 128                                 jme->mii_if.phy_id,
 129                                 MII_BMCR);
 130
 131         jme_mdio_write(jme->dev,
 132                         jme->mii_if.phy_id,
 133                         MII_BMCR, val | BMCR_RESET);
 134 }
 135
 136 static void
 137 jme_setup_wakeup_frame(struct jme_adapter *jme,
 138                        const u32 *mask, u32 crc, int fnr)
 139 {
 140         int i;
 141
 142         /*
 143          * Setup CRC pattern
 144          */
 145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
 146         wmb();
 147         jwrite32(jme, JME_WFODP, crc);
 148         wmb();
 149
 150         /*
 151          * Setup Mask
 152          */
 153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
 154                 jwrite32(jme, JME_WFOI,
 155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
 156                                 (fnr & WFOI_FRAME_SEL));
 157                 wmb();
 158                 jwrite32(jme, JME_WFODP, mask[i]);
 159                 wmb();
 160         }
 161 }
 162
 163 static inline void
 164 jme_mac_rxclk_off(struct jme_adapter *jme)
 165 {
 166         jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
 167         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 168 }
 169
 170 static inline void
 171 jme_mac_rxclk_on(struct jme_adapter *jme)
 172 {
 173         jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
 174         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 175 }
 176
 177 static inline void
 178 jme_mac_txclk_off(struct jme_adapter *jme)
 179 {
 180         jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
 181         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 182 }
 183
 184 static inline void
 185 jme_mac_txclk_on(struct jme_adapter *jme)
 186 {
 187         u32 speed = jme->reg_ghc & GHC_SPEED;
 188         if (speed == GHC_SPEED_1000M)
 189                 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 190         else
 191                 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 192         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 193 }
 194
 195 static inline void
 196 jme_reset_ghc_speed(struct jme_adapter *jme)
 197 {
 198         jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
 199         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 200 }
 201
 202 static inline void
 203 jme_reset_250A2_workaround(struct jme_adapter *jme)
 204 {
 205         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 206                              GPREG1_RSSPATCH);
 207         jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 208 }
 209
 210 static inline void
 211 jme_assert_ghc_reset(struct jme_adapter *jme)
 212 {
 213         jme->reg_ghc |= GHC_SWRST;
 214         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 215 }
 216
 217 static inline void
 218 jme_clear_ghc_reset(struct jme_adapter *jme)
 219 {
 220         jme->reg_ghc &= ~GHC_SWRST;
 221         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 222 }
 223
 224 static inline void
 225 jme_reset_mac_processor(struct jme_adapter *jme)
 226 {
 227         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
 228         u32 crc = 0xCDCDCDCD;
 229         u32 gpreg0;
 230         int i;
 231
 232         jme_reset_ghc_speed(jme);
 233         jme_reset_250A2_workaround(jme);
 234
 235         jme_mac_rxclk_on(jme);
 236         jme_mac_txclk_on(jme);
 237         udelay(1);
 238         jme_assert_ghc_reset(jme);
 239         udelay(1);
 240         jme_mac_rxclk_off(jme);
 241         jme_mac_txclk_off(jme);
 242         udelay(1);
 243         jme_clear_ghc_reset(jme);
 244         udelay(1);
 245         jme_mac_rxclk_on(jme);
 246         jme_mac_txclk_on(jme);
 247         udelay(1);
 248         jme_mac_rxclk_off(jme);
 249         jme_mac_txclk_off(jme);
 250
 251         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
 252         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
 253         jwrite32(jme, JME_RXQDC, 0x00000000);
 254         jwrite32(jme, JME_RXNDA, 0x00000000);
 255         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
 256         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
 257         jwrite32(jme, JME_TXQDC, 0x00000000);
 258         jwrite32(jme, JME_TXNDA, 0x00000000);
 259
 260         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
 261         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
 262         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
 263                 jme_setup_wakeup_frame(jme, mask, crc, i);
 264         if (jme->fpgaver)
 265                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
 266         else
 267                 gpreg0 = GPREG0_DEFAULT;
 268         jwrite32(jme, JME_GPREG0, gpreg0);
 269 }
 270
 271 static inline void
 272 jme_clear_pm(struct jme_adapter *jme)
 273 {
 274         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
 275         pci_set_power_state(jme->pdev, PCI_D0);
 276         pci_enable_wake(jme->pdev, PCI_D0, false);
 277 }
 278
 279 static int
 280 jme_reload_eeprom(struct jme_adapter *jme)
 281 {
 282         u32 val;
 283         int i;
 284
 285         val = jread32(jme, JME_SMBCSR);
 286
 287         if (val & SMBCSR_EEPROMD) {
 288                 val |= SMBCSR_CNACK;
 289                 jwrite32(jme, JME_SMBCSR, val);
 290                 val |= SMBCSR_RELOAD;
 291                 jwrite32(jme, JME_SMBCSR, val);
 292                 mdelay(12);
 293
 294                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
 295                         mdelay(1);
 296                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
 297                                 break;
 298                 }
 299
 300                 if (i == 0) {
 301                         pr_err("eeprom reload timeout\n");
 302                         return -EIO;
 303                 }
 304         }
 305
 306         return 0;
 307 }
 308
 309 static void
 310 jme_load_macaddr(struct net_device *netdev)
 311 {
 312         struct jme_adapter *jme = netdev_priv(netdev);
 313         unsigned char macaddr[6];
 314         u32 val;
 315
 316         spin_lock_bh(&jme->macaddr_lock);
 317         val = jread32(jme, JME_RXUMA_LO);
 318         macaddr[0] = (val >>  0) & 0xFF;
 319         macaddr[1] = (val >>  8) & 0xFF;
 320         macaddr[2] = (val >> 16) & 0xFF;
 321         macaddr[3] = (val >> 24) & 0xFF;
 322         val = jread32(jme, JME_RXUMA_HI);
 323         macaddr[4] = (val >>  0) & 0xFF;
 324         macaddr[5] = (val >>  8) & 0xFF;
 325         memcpy(netdev->dev_addr, macaddr, 6);
 326         spin_unlock_bh(&jme->macaddr_lock);
 327 }
 328
 329 static inline void
 330 jme_set_rx_pcc(struct jme_adapter *jme, int p)
 331 {
 332         switch (p) {
 333         case PCC_OFF:
 334                 jwrite32(jme, JME_PCCRX0,
 335                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 336                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 337                 break;
 338         case PCC_P1:
 339                 jwrite32(jme, JME_PCCRX0,
 340                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 341                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 342                 break;
 343         case PCC_P2:
 344                 jwrite32(jme, JME_PCCRX0,
 345                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 346                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 347                 break;
 348         case PCC_P3:
 349                 jwrite32(jme, JME_PCCRX0,
 350                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 351                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 352                 break;
 353         default:
 354                 break;
 355         }
 356         wmb();
 357
 358         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
 359                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
 360 }
 361
 362 static void
 363 jme_start_irq(struct jme_adapter *jme)
 364 {
 365         register struct dynpcc_info *dpi = &(jme->dpi);
 366
 367         jme_set_rx_pcc(jme, PCC_P1);
 368         dpi->cur                = PCC_P1;
 369         dpi->attempt            = PCC_P1;
 370         dpi->cnt                = 0;
 371
 372         jwrite32(jme, JME_PCCTX,
 373                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
 374                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
 375                         PCCTXQ0_EN
 376                 );
 377
 378         /*
 379          * Enable Interrupts
 380          */
 381         jwrite32(jme, JME_IENS, INTR_ENABLE);
 382 }
 383
 384 static inline void
 385 jme_stop_irq(struct jme_adapter *jme)
 386 {
 387         /*
 388          * Disable Interrupts
 389          */
 390         jwrite32f(jme, JME_IENC, INTR_ENABLE);
 391 }
 392
 393 static u32
 394 jme_linkstat_from_phy(struct jme_adapter *jme)
 395 {
 396         u32 phylink, bmsr;
 397
 398         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
 399         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
 400         if (bmsr & BMSR_ANCOMP)
 401                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
 402
 403         return phylink;
 404 }
 405
 406 static inline void
 407 jme_set_phyfifo_5level(struct jme_adapter *jme)
 408 {
 409         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 410 }
 411
 412 static inline void
 413 jme_set_phyfifo_8level(struct jme_adapter *jme)
 414 {
 415         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 416 }
 417
 418 static int
 419 jme_check_link(struct net_device *netdev, int testonly)
 420 {
 421         struct jme_adapter *jme = netdev_priv(netdev);
 422         u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
 423         char linkmsg[64];
 424         int rc = 0;
 425
 426         linkmsg[0] = '\0';
 427
 428         if (jme->fpgaver)
 429                 phylink = jme_linkstat_from_phy(jme);
 430         else
 431                 phylink = jread32(jme, JME_PHY_LINK);
 432
 433         if (phylink & PHY_LINK_UP) {
 434                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
 435                         /*
 436                          * If we did not enable AN
 437                          * Speed/Duplex Info should be obtained from SMI
 438                          */
 439                         phylink = PHY_LINK_UP;
 440
 441                         bmcr = jme_mdio_read(jme->dev,
 442                                                 jme->mii_if.phy_id,
 443                                                 MII_BMCR);
 444
 445                         phylink |= ((bmcr & BMCR_SPEED1000) &&
 446                                         (bmcr & BMCR_SPEED100) == 0) ?
 447                                         PHY_LINK_SPEED_1000M :
 448                                         (bmcr & BMCR_SPEED100) ?
 449                                         PHY_LINK_SPEED_100M :
 450                                         PHY_LINK_SPEED_10M;
 451
 452                         phylink |= (bmcr & BMCR_FULLDPLX) ?
 453                                          PHY_LINK_DUPLEX : 0;
 454
 455                         strcat(linkmsg, "Forced: ");
 456                 } else {
 457                         /*
 458                          * Keep polling for speed/duplex resolve complete
 459                          */
 460                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
 461                                 --cnt) {
 462
 463                                 udelay(1);
 464
 465                                 if (jme->fpgaver)
 466                                         phylink = jme_linkstat_from_phy(jme);
 467                                 else
 468                                         phylink = jread32(jme, JME_PHY_LINK);
 469                         }
 470                         if (!cnt)
 471                                 pr_err("Waiting speed resolve timeout\n");
 472
 473                         strcat(linkmsg, "ANed: ");
 474                 }
 475
 476                 if (jme->phylink == phylink) {
 477                         rc = 1;
 478                         goto out;
 479                 }
 480                 if (testonly)
 481                         goto out;
 482
 483                 jme->phylink = phylink;
 484
 485                 /*
 486                  * The speed/duplex setting of jme->reg_ghc already cleared
 487                  * by jme_reset_mac_processor()
 488                  */
 489                 switch (phylink & PHY_LINK_SPEED_MASK) {
 490                 case PHY_LINK_SPEED_10M:
 491                         jme->reg_ghc |= GHC_SPEED_10M;
 492                         strcat(linkmsg, "10 Mbps, ");
 493                         break;
 494                 case PHY_LINK_SPEED_100M:
 495                         jme->reg_ghc |= GHC_SPEED_100M;
 496                         strcat(linkmsg, "100 Mbps, ");
 497                         break;
 498                 case PHY_LINK_SPEED_1000M:
 499                         jme->reg_ghc |= GHC_SPEED_1000M;
 500                         strcat(linkmsg, "1000 Mbps, ");
 501                         break;
 502                 default:
 503                         break;
 504                 }
 505
 506                 if (phylink & PHY_LINK_DUPLEX) {
 507                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
 508                         jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
 509                         jme->reg_ghc |= GHC_DPX;
 510                 } else {
 511                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
 512                                                 TXMCS_BACKOFF |
 513                                                 TXMCS_CARRIERSENSE |
 514                                                 TXMCS_COLLISION);
 515                         jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
 516                 }
 517
 518                 jwrite32(jme, JME_GHC, jme->reg_ghc);
 519
 520                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 521                         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 522                                              GPREG1_RSSPATCH);
 523                         if (!(phylink & PHY_LINK_DUPLEX))
 524                                 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
 525                         switch (phylink & PHY_LINK_SPEED_MASK) {
 526                         case PHY_LINK_SPEED_10M:
 527                                 jme_set_phyfifo_8level(jme);
 528                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 529                                 break;
 530                         case PHY_LINK_SPEED_100M:
 531                                 jme_set_phyfifo_5level(jme);
 532                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 533                                 break;
 534                         case PHY_LINK_SPEED_1000M:
 535                                 jme_set_phyfifo_8level(jme);
 536                                 break;
 537                         default:
 538                                 break;
 539                         }
 540                 }
 541                 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 542
 543                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
 544                                         "Full-Duplex, " :
 545                                         "Half-Duplex, ");
 546                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
 547                                         "MDI-X" :
 548                                         "MDI");
 549                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
 550                 netif_carrier_on(netdev);
 551         } else {
 552                 if (testonly)
 553                         goto out;
 554
 555                 netif_info(jme, link, jme->dev, "Link is down\n");
 556                 jme->phylink = 0;
 557                 netif_carrier_off(netdev);
 558         }
 559
 560 out:
 561         return rc;
 562 }
 563
 564 static int
 565 jme_setup_tx_resources(struct jme_adapter *jme)
 566 {
 567         struct jme_ring *txring = &(jme->txring[0]);
 568
 569         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 570                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 571                                    &(txring->dmaalloc),
 572                                    GFP_ATOMIC);
 573
 574         if (!txring->alloc)
 575                 goto err_set_null;
 576
 577         /*
 578          * 16 Bytes align
 579          */
 580         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
 581                                                 RING_DESC_ALIGN);
 582         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
 583         txring->next_to_use     = 0;
 584         atomic_set(&txring->next_to_clean, 0);
 585         atomic_set(&txring->nr_free, jme->tx_ring_size);
 586
 587         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 588                                         jme->tx_ring_size, GFP_ATOMIC);
 589         if (unlikely(!(txring->bufinf)))
 590                 goto err_free_txring;
 591
 592         /*
 593          * Initialize Transmit Descriptors
 594          */
 595         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
 596         memset(txring->bufinf, 0,
 597                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
 598
 599         return 0;
 600
 601 err_free_txring:
 602         dma_free_coherent(&(jme->pdev->dev),
 603                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 604                           txring->alloc,
 605                           txring->dmaalloc);
 606
 607 err_set_null:
 608         txring->desc = NULL;
 609         txring->dmaalloc = 0;
 610         txring->dma = 0;
 611         txring->bufinf = NULL;
 612
 613         return -ENOMEM;
 614 }
 615
 616 static void
 617 jme_free_tx_resources(struct jme_adapter *jme)
 618 {
 619         int i;
 620         struct jme_ring *txring = &(jme->txring[0]);
 621         struct jme_buffer_info *txbi;
 622
 623         if (txring->alloc) {
 624                 if (txring->bufinf) {
 625                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
 626                                 txbi = txring->bufinf + i;
 627                                 if (txbi->skb) {
 628                                         dev_kfree_skb(txbi->skb);
 629                                         txbi->skb = NULL;
 630                                 }
 631                                 txbi->mapping           = 0;
 632                                 txbi->len               = 0;
 633                                 txbi->nr_desc           = 0;
 634                                 txbi->start_xmit        = 0;
 635                         }
 636                         kfree(txring->bufinf);
 637                 }
 638
 639                 dma_free_coherent(&(jme->pdev->dev),
 640                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 641                                   txring->alloc,
 642                                   txring->dmaalloc);
 643
 644                 txring->alloc           = NULL;
 645                 txring->desc            = NULL;
 646                 txring->dmaalloc        = 0;
 647                 txring->dma             = 0;
 648                 txring->bufinf          = NULL;
 649         }
 650         txring->next_to_use     = 0;
 651         atomic_set(&txring->next_to_clean, 0);
 652         atomic_set(&txring->nr_free, 0);
 653 }
 654
 655 static inline void
 656 jme_enable_tx_engine(struct jme_adapter *jme)
 657 {
 658         /*
 659          * Select Queue 0
 660          */
 661         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
 662         wmb();
 663
 664         /*
 665          * Setup TX Queue 0 DMA Bass Address
 666          */
 667         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 668         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
 669         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 670
 671         /*
 672          * Setup TX Descptor Count
 673          */
 674         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
 675
 676         /*
 677          * Enable TX Engine
 678          */
 679         wmb();
 680         jwrite32f(jme, JME_TXCS, jme->reg_txcs |
 681                                 TXCS_SELECT_QUEUE0 |
 682                                 TXCS_ENABLE);
 683
 684         /*
 685          * Start clock for TX MAC Processor
 686          */
 687         jme_mac_txclk_on(jme);
 688 }
 689
 690 static inline void
 691 jme_restart_tx_engine(struct jme_adapter *jme)
 692 {
 693         /*
 694          * Restart TX Engine
 695          */
 696         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 697                                 TXCS_SELECT_QUEUE0 |
 698                                 TXCS_ENABLE);
 699 }
 700
 701 static inline void
 702 jme_disable_tx_engine(struct jme_adapter *jme)
 703 {
 704         int i;
 705         u32 val;
 706
 707         /*
 708          * Disable TX Engine
 709          */
 710         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
 711         wmb();
 712
 713         val = jread32(jme, JME_TXCS);
 714         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
 715                 mdelay(1);
 716                 val = jread32(jme, JME_TXCS);
 717                 rmb();
 718         }
 719
 720         if (!i)
 721                 pr_err("Disable TX engine timeout\n");
 722
 723         /*
 724          * Stop clock for TX MAC Processor
 725          */
 726         jme_mac_txclk_off(jme);
 727 }
 728
 729 static void
 730 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
 731 {
 732         struct jme_ring *rxring = &(jme->rxring[0]);
 733         register struct rxdesc *rxdesc = rxring->desc;
 734         struct jme_buffer_info *rxbi = rxring->bufinf;
 735         rxdesc += i;
 736         rxbi += i;
 737
 738         rxdesc->dw[0] = 0;
 739         rxdesc->dw[1] = 0;
 740         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
 741         rxdesc->desc1.bufaddrl  = cpu_to_le32(
 742                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
 743         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
 744         if (jme->dev->features & NETIF_F_HIGHDMA)
 745                 rxdesc->desc1.flags = RXFLAG_64BIT;
 746         wmb();
 747         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
 748 }
 749
 750 static int
 751 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
 752 {
 753         struct jme_ring *rxring = &(jme->rxring[0]);
 754         struct jme_buffer_info *rxbi = rxring->bufinf + i;
 755         struct sk_buff *skb;
 756
 757         skb = netdev_alloc_skb(jme->dev,
 758                 jme->dev->mtu + RX_EXTRA_LEN);
 759         if (unlikely(!skb))
 760                 return -ENOMEM;
 761
 762         rxbi->skb = skb;
 763         rxbi->len = skb_tailroom(skb);
 764         rxbi->mapping = pci_map_page(jme->pdev,
 765                                         virt_to_page(skb->data),
 766                                         offset_in_page(skb->data),
 767                                         rxbi->len,
 768                                         PCI_DMA_FROMDEVICE);
 769
 770         return 0;
 771 }
 772
 773 static void
 774 jme_free_rx_buf(struct jme_adapter *jme, int i)
 775 {
 776         struct jme_ring *rxring = &(jme->rxring[0]);
 777         struct jme_buffer_info *rxbi = rxring->bufinf;
 778         rxbi += i;
 779
 780         if (rxbi->skb) {
 781                 pci_unmap_page(jme->pdev,
 782                                  rxbi->mapping,
 783                                  rxbi->len,
 784                                  PCI_DMA_FROMDEVICE);
 785                 dev_kfree_skb(rxbi->skb);
 786                 rxbi->skb = NULL;
 787                 rxbi->mapping = 0;
 788                 rxbi->len = 0;
 789         }
 790 }
 791
 792 static void
 793 jme_free_rx_resources(struct jme_adapter *jme)
 794 {
 795         int i;
 796         struct jme_ring *rxring = &(jme->rxring[0]);
 797
 798         if (rxring->alloc) {
 799                 if (rxring->bufinf) {
 800                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
 801                                 jme_free_rx_buf(jme, i);
 802                         kfree(rxring->bufinf);
 803                 }
 804
 805                 dma_free_coherent(&(jme->pdev->dev),
 806                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 807                                   rxring->alloc,
 808                                   rxring->dmaalloc);
 809                 rxring->alloc    = NULL;
 810                 rxring->desc     = NULL;
 811                 rxring->dmaalloc = 0;
 812                 rxring->dma      = 0;
 813                 rxring->bufinf   = NULL;
 814         }
 815         rxring->next_to_use   = 0;
 816         atomic_set(&rxring->next_to_clean, 0);
 817 }
 818
 819 static int
 820 jme_setup_rx_resources(struct jme_adapter *jme)
 821 {
 822         int i;
 823         struct jme_ring *rxring = &(jme->rxring[0]);
 824
 825         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 826                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 827                                    &(rxring->dmaalloc),
 828                                    GFP_ATOMIC);
 829         if (!rxring->alloc)
 830                 goto err_set_null;
 831
 832         /*
 833          * 16 Bytes align
 834          */
 835         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
 836                                                 RING_DESC_ALIGN);
 837         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
 838         rxring->next_to_use     = 0;
 839         atomic_set(&rxring->next_to_clean, 0);
 840
 841         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 842                                         jme->rx_ring_size, GFP_ATOMIC);
 843         if (unlikely(!(rxring->bufinf)))
 844                 goto err_free_rxring;
 845
 846         /*
 847          * Initiallize Receive Descriptors
 848          */
 849         memset(rxring->bufinf, 0,
 850                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
 851         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
 852                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
 853                         jme_free_rx_resources(jme);
 854                         return -ENOMEM;
 855                 }
 856
 857                 jme_set_clean_rxdesc(jme, i);
 858         }
 859
 860         return 0;
 861
 862 err_free_rxring:
 863         dma_free_coherent(&(jme->pdev->dev),
 864                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 865                           rxring->alloc,
 866                           rxring->dmaalloc);
 867 err_set_null:
 868         rxring->desc = NULL;
 869         rxring->dmaalloc = 0;
 870         rxring->dma = 0;
 871         rxring->bufinf = NULL;
 872
 873         return -ENOMEM;
 874 }
 875
 876 static inline void
 877 jme_enable_rx_engine(struct jme_adapter *jme)
 878 {
 879         /*
 880          * Select Queue 0
 881          */
 882         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 883                                 RXCS_QUEUESEL_Q0);
 884         wmb();
 885
 886         /*
 887          * Setup RX DMA Bass Address
 888          */
 889         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 890         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
 891         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 892
 893         /*
 894          * Setup RX Descriptor Count
 895          */
 896         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
 897
 898         /*
 899          * Setup Unicast Filter
 900          */
 901         jme_set_multi(jme->dev);
 902
 903         /*
 904          * Enable RX Engine
 905          */
 906         wmb();
 907         jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
 908                                 RXCS_QUEUESEL_Q0 |
 909                                 RXCS_ENABLE |
 910                                 RXCS_QST);
 911
 912         /*
 913          * Start clock for RX MAC Processor
 914          */
 915         jme_mac_rxclk_on(jme);
 916 }
 917
 918 static inline void
 919 jme_restart_rx_engine(struct jme_adapter *jme)
 920 {
 921         /*
 922          * Start RX Engine
 923          */
 924         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 925                                 RXCS_QUEUESEL_Q0 |
 926                                 RXCS_ENABLE |
 927                                 RXCS_QST);
 928 }
 929
 930 static inline void
 931 jme_disable_rx_engine(struct jme_adapter *jme)
 932 {
 933         int i;
 934         u32 val;
 935
 936         /*
 937          * Disable RX Engine
 938          */
 939         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
 940         wmb();
 941
 942         val = jread32(jme, JME_RXCS);
 943         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
 944                 mdelay(1);
 945                 val = jread32(jme, JME_RXCS);
 946                 rmb();
 947         }
 948
 949         if (!i)
 950                 pr_err("Disable RX engine timeout\n");
 951
 952         /*
 953          * Stop clock for RX MAC Processor
 954          */
 955         jme_mac_rxclk_off(jme);
 956 }
 957
 958 static int
 959 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
 960 {
 961         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
 962                 return false;
 963
 964         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
 965                         == RXWBFLAG_TCPON)) {
 966                 if (flags & RXWBFLAG_IPV4)
 967                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
 968                 return false;
 969         }
 970
 971         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
 972                         == RXWBFLAG_UDPON)) {
 973                 if (flags & RXWBFLAG_IPV4)
 974                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
 975                 return false;
 976         }
 977
 978         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
 979                         == RXWBFLAG_IPV4)) {
 980                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
 981                 return false;
 982         }
 983
 984         return true;
 985 }
 986
 987 static void
 988 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
 989 {
 990         struct jme_ring *rxring = &(jme->rxring[0]);
 991         struct rxdesc *rxdesc = rxring->desc;
 992         struct jme_buffer_info *rxbi = rxring->bufinf;
 993         struct sk_buff *skb;
 994         int framesize;
 995
 996         rxdesc += idx;
 997         rxbi += idx;
 998
 999         skb = rxbi->skb;
1000         pci_dma_sync_single_for_cpu(jme->pdev,
1001                                         rxbi->mapping,
1002                                         rxbi->len,
1003                                         PCI_DMA_FROMDEVICE);
1004
1005         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1006                 pci_dma_sync_single_for_device(jme->pdev,
1007                                                 rxbi->mapping,
1008                                                 rxbi->len,
1009                                                 PCI_DMA_FROMDEVICE);
1010
1011                 ++(NET_STAT(jme).rx_dropped);
1012         } else {
1013                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1014                                 - RX_PREPAD_SIZE;
1015
1016                 skb_reserve(skb, RX_PREPAD_SIZE);
1017                 skb_put(skb, framesize);
1018                 skb->protocol = eth_type_trans(skb, jme->dev);
1019
1020                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
1021                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1022                 else
1023                         skb_checksum_none_assert(skb);
1024
1025                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1026                         if (jme->vlgrp) {
1027                                 jme->jme_vlan_rx(skb, jme->vlgrp,
1028                                         le16_to_cpu(rxdesc->descwb.vlan));
1029                                 NET_STAT(jme).rx_bytes += 4;
1030                         } else {
1031                                 dev_kfree_skb(skb);
1032                         }
1033                 } else {
1034                         jme->jme_rx(skb);
1035                 }
1036
1037                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1038                     cpu_to_le16(RXWBFLAG_DEST_MUL))
1039                         ++(NET_STAT(jme).multicast);
1040
1041                 NET_STAT(jme).rx_bytes += framesize;
1042                 ++(NET_STAT(jme).rx_packets);
1043         }
1044
1045         jme_set_clean_rxdesc(jme, idx);
1046
1047 }
1048
1049 static int
1050 jme_process_receive(struct jme_adapter *jme, int limit)
1051 {
1052         struct jme_ring *rxring = &(jme->rxring[0]);
1053         struct rxdesc *rxdesc = rxring->desc;
1054         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1055
1056         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1057                 goto out_inc;
1058
1059         if (unlikely(atomic_read(&jme->link_changing) != 1))
1060                 goto out_inc;
1061
1062         if (unlikely(!netif_carrier_ok(jme->dev)))
1063                 goto out_inc;
1064
1065         i = atomic_read(&rxring->next_to_clean);
1066         while (limit > 0) {
1067                 rxdesc = rxring->desc;
1068                 rxdesc += i;
1069
1070                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1071                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1072                         goto out;
1073                 --limit;
1074
1075                 rmb();
1076                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1077
1078                 if (unlikely(desccnt > 1 ||
1079                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1080
1081                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1082                                 ++(NET_STAT(jme).rx_crc_errors);
1083                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1084                                 ++(NET_STAT(jme).rx_fifo_errors);
1085                         else
1086                                 ++(NET_STAT(jme).rx_errors);
1087
1088                         if (desccnt > 1)
1089                                 limit -= desccnt - 1;
1090
1091                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1092                                 jme_set_clean_rxdesc(jme, j);
1093                                 j = (j + 1) & (mask);
1094                         }
1095
1096                 } else {
1097                         jme_alloc_and_feed_skb(jme, i);
1098                 }
1099
1100                 i = (i + desccnt) & (mask);
1101         }
1102
1103 out:
1104         atomic_set(&rxring->next_to_clean, i);
1105
1106 out_inc:
1107         atomic_inc(&jme->rx_cleaning);
1108
1109         return limit > 0 ? limit : 0;
1110
1111 }
1112
1113 static void
1114 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1115 {
1116         if (likely(atmp == dpi->cur)) {
1117                 dpi->cnt = 0;
1118                 return;
1119         }
1120
1121         if (dpi->attempt == atmp) {
1122                 ++(dpi->cnt);
1123         } else {
1124                 dpi->attempt = atmp;
1125                 dpi->cnt = 0;
1126         }
1127
1128 }
1129
1130 static void
1131 jme_dynamic_pcc(struct jme_adapter *jme)
1132 {
1133         register struct dynpcc_info *dpi = &(jme->dpi);
1134
1135         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1136                 jme_attempt_pcc(dpi, PCC_P3);
1137         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1138                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1139                 jme_attempt_pcc(dpi, PCC_P2);
1140         else
1141                 jme_attempt_pcc(dpi, PCC_P1);
1142
1143         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1144                 if (dpi->attempt < dpi->cur)
1145                         tasklet_schedule(&jme->rxclean_task);
1146                 jme_set_rx_pcc(jme, dpi->attempt);
1147                 dpi->cur = dpi->attempt;
1148                 dpi->cnt = 0;
1149         }
1150 }
1151
1152 static void
1153 jme_start_pcc_timer(struct jme_adapter *jme)
1154 {
1155         struct dynpcc_info *dpi = &(jme->dpi);
1156         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1157         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1158         dpi->intr_cnt           = 0;
1159         jwrite32(jme, JME_TMCSR,
1160                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1161 }
1162
1163 static inline void
1164 jme_stop_pcc_timer(struct jme_adapter *jme)
1165 {
1166         jwrite32(jme, JME_TMCSR, 0);
1167 }
1168
1169 static void
1170 jme_shutdown_nic(struct jme_adapter *jme)
1171 {
1172         u32 phylink;
1173
1174         phylink = jme_linkstat_from_phy(jme);
1175
1176         if (!(phylink & PHY_LINK_UP)) {
1177                 /*
1178                  * Disable all interrupt before issue timer
1179                  */
1180                 jme_stop_irq(jme);
1181                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1182         }
1183 }
1184
1185 static void
1186 jme_pcc_tasklet(unsigned long arg)
1187 {
1188         struct jme_adapter *jme = (struct jme_adapter *)arg;
1189         struct net_device *netdev = jme->dev;
1190
1191         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1192                 jme_shutdown_nic(jme);
1193                 return;
1194         }
1195
1196         if (unlikely(!netif_carrier_ok(netdev) ||
1197                 (atomic_read(&jme->link_changing) != 1)
1198         )) {
1199                 jme_stop_pcc_timer(jme);
1200                 return;
1201         }
1202
1203         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1204                 jme_dynamic_pcc(jme);
1205
1206         jme_start_pcc_timer(jme);
1207 }
1208
1209 static inline void
1210 jme_polling_mode(struct jme_adapter *jme)
1211 {
1212         jme_set_rx_pcc(jme, PCC_OFF);
1213 }
1214
1215 static inline void
1216 jme_interrupt_mode(struct jme_adapter *jme)
1217 {
1218         jme_set_rx_pcc(jme, PCC_P1);
1219 }
1220
1221 static inline int
1222 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1223 {
1224         u32 apmc;
1225         apmc = jread32(jme, JME_APMC);
1226         return apmc & JME_APMC_PSEUDO_HP_EN;
1227 }
1228
1229 static void
1230 jme_start_shutdown_timer(struct jme_adapter *jme)
1231 {
1232         u32 apmc;
1233
1234         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1235         apmc &= ~JME_APMC_EPIEN_CTRL;
1236         if (!no_extplug) {
1237                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1238                 wmb();
1239         }
1240         jwrite32f(jme, JME_APMC, apmc);
1241
1242         jwrite32f(jme, JME_TIMER2, 0);
1243         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1244         jwrite32(jme, JME_TMCSR,
1245                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1246 }
1247
1248 static void
1249 jme_stop_shutdown_timer(struct jme_adapter *jme)
1250 {
1251         u32 apmc;
1252
1253         jwrite32f(jme, JME_TMCSR, 0);
1254         jwrite32f(jme, JME_TIMER2, 0);
1255         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1256
1257         apmc = jread32(jme, JME_APMC);
1258         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1259         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1260         wmb();
1261         jwrite32f(jme, JME_APMC, apmc);
1262 }
1263
1264 static void
1265 jme_link_change_tasklet(unsigned long arg)
1266 {
1267         struct jme_adapter *jme = (struct jme_adapter *)arg;
1268         struct net_device *netdev = jme->dev;
1269         int rc;
1270
1271         while (!atomic_dec_and_test(&jme->link_changing)) {
1272                 atomic_inc(&jme->link_changing);
1273                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1274                 while (atomic_read(&jme->link_changing) != 1)
1275                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1276         }
1277
1278         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1279                 goto out;
1280
1281         jme->old_mtu = netdev->mtu;
1282         netif_stop_queue(netdev);
1283         if (jme_pseudo_hotplug_enabled(jme))
1284                 jme_stop_shutdown_timer(jme);
1285
1286         jme_stop_pcc_timer(jme);
1287         tasklet_disable(&jme->txclean_task);
1288         tasklet_disable(&jme->rxclean_task);
1289         tasklet_disable(&jme->rxempty_task);
1290
1291         if (netif_carrier_ok(netdev)) {
1292                 jme_disable_rx_engine(jme);
1293                 jme_disable_tx_engine(jme);
1294                 jme_reset_mac_processor(jme);
1295                 jme_free_rx_resources(jme);
1296                 jme_free_tx_resources(jme);
1297
1298                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1299                         jme_polling_mode(jme);
1300
1301                 netif_carrier_off(netdev);
1302         }
1303
1304         jme_check_link(netdev, 0);
1305         if (netif_carrier_ok(netdev)) {
1306                 rc = jme_setup_rx_resources(jme);
1307                 if (rc) {
1308                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1309                         goto out_enable_tasklet;
1310                 }
1311
1312                 rc = jme_setup_tx_resources(jme);
1313                 if (rc) {
1314                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1315                         goto err_out_free_rx_resources;
1316                 }
1317
1318                 jme_enable_rx_engine(jme);
1319                 jme_enable_tx_engine(jme);
1320
1321                 netif_start_queue(netdev);
1322
1323                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1324                         jme_interrupt_mode(jme);
1325
1326                 jme_start_pcc_timer(jme);
1327         } else if (jme_pseudo_hotplug_enabled(jme)) {
1328                 jme_start_shutdown_timer(jme);
1329         }
1330
1331         goto out_enable_tasklet;
1332
1333 err_out_free_rx_resources:
1334         jme_free_rx_resources(jme);
1335 out_enable_tasklet:
1336         tasklet_enable(&jme->txclean_task);
1337         tasklet_hi_enable(&jme->rxclean_task);
1338         tasklet_hi_enable(&jme->rxempty_task);
1339 out:
1340         atomic_inc(&jme->link_changing);
1341 }
1342
1343 static void
1344 jme_rx_clean_tasklet(unsigned long arg)
1345 {
1346         struct jme_adapter *jme = (struct jme_adapter *)arg;
1347         struct dynpcc_info *dpi = &(jme->dpi);
1348
1349         jme_process_receive(jme, jme->rx_ring_size);
1350         ++(dpi->intr_cnt);
1351
1352 }
1353
1354 static int
1355 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1356 {
1357         struct jme_adapter *jme = jme_napi_priv(holder);
1358         int rest;
1359
1360         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1361
1362         while (atomic_read(&jme->rx_empty) > 0) {
1363                 atomic_dec(&jme->rx_empty);
1364                 ++(NET_STAT(jme).rx_dropped);
1365                 jme_restart_rx_engine(jme);
1366         }
1367         atomic_inc(&jme->rx_empty);
1368
1369         if (rest) {
1370                 JME_RX_COMPLETE(netdev, holder);
1371                 jme_interrupt_mode(jme);
1372         }
1373
1374         JME_NAPI_WEIGHT_SET(budget, rest);
1375         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1376 }
1377
1378 static void
1379 jme_rx_empty_tasklet(unsigned long arg)
1380 {
1381         struct jme_adapter *jme = (struct jme_adapter *)arg;
1382
1383         if (unlikely(atomic_read(&jme->link_changing) != 1))
1384                 return;
1385
1386         if (unlikely(!netif_carrier_ok(jme->dev)))
1387                 return;
1388
1389         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1390
1391         jme_rx_clean_tasklet(arg);
1392
1393         while (atomic_read(&jme->rx_empty) > 0) {
1394                 atomic_dec(&jme->rx_empty);
1395                 ++(NET_STAT(jme).rx_dropped);
1396                 jme_restart_rx_engine(jme);
1397         }
1398         atomic_inc(&jme->rx_empty);
1399 }
1400
1401 static void
1402 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1403 {
1404         struct jme_ring *txring = &(jme->txring[0]);
1405
1406         smp_wmb();
1407         if (unlikely(netif_queue_stopped(jme->dev) &&
1408         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1409                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1410                 netif_wake_queue(jme->dev);
1411         }
1412
1413 }
1414
1415 static void
1416 jme_tx_clean_tasklet(unsigned long arg)
1417 {
1418         struct jme_adapter *jme = (struct jme_adapter *)arg;
1419         struct jme_ring *txring = &(jme->txring[0]);
1420         struct txdesc *txdesc = txring->desc;
1421         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1422         int i, j, cnt = 0, max, err, mask;
1423
1424         tx_dbg(jme, "Into txclean\n");
1425
1426         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1427                 goto out;
1428
1429         if (unlikely(atomic_read(&jme->link_changing) != 1))
1430                 goto out;
1431
1432         if (unlikely(!netif_carrier_ok(jme->dev)))
1433                 goto out;
1434
1435         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1436         mask = jme->tx_ring_mask;
1437
1438         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1439
1440                 ctxbi = txbi + i;
1441
1442                 if (likely(ctxbi->skb &&
1443                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1444
1445                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1446                                i, ctxbi->nr_desc, jiffies);
1447
1448                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1449
1450                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1451                                 ttxbi = txbi + ((i + j) & (mask));
1452                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1453
1454                                 pci_unmap_page(jme->pdev,
1455                                                  ttxbi->mapping,
1456                                                  ttxbi->len,
1457                                                  PCI_DMA_TODEVICE);
1458
1459                                 ttxbi->mapping = 0;
1460                                 ttxbi->len = 0;
1461                         }
1462
1463                         dev_kfree_skb(ctxbi->skb);
1464
1465                         cnt += ctxbi->nr_desc;
1466
1467                         if (unlikely(err)) {
1468                                 ++(NET_STAT(jme).tx_carrier_errors);
1469                         } else {
1470                                 ++(NET_STAT(jme).tx_packets);
1471                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1472                         }
1473
1474                         ctxbi->skb = NULL;
1475                         ctxbi->len = 0;
1476                         ctxbi->start_xmit = 0;
1477
1478                 } else {
1479                         break;
1480                 }
1481
1482                 i = (i + ctxbi->nr_desc) & mask;
1483
1484                 ctxbi->nr_desc = 0;
1485         }
1486
1487         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1488         atomic_set(&txring->next_to_clean, i);
1489         atomic_add(cnt, &txring->nr_free);
1490
1491         jme_wake_queue_if_stopped(jme);
1492
1493 out:
1494         atomic_inc(&jme->tx_cleaning);
1495 }
1496
1497 static void
1498 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1499 {
1500         /*
1501          * Disable interrupt
1502          */
1503         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1504
1505         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1506                 /*
1507                  * Link change event is critical
1508                  * all other events are ignored
1509                  */
1510                 jwrite32(jme, JME_IEVE, intrstat);
1511                 tasklet_schedule(&jme->linkch_task);
1512                 goto out_reenable;
1513         }
1514
1515         if (intrstat & INTR_TMINTR) {
1516                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1517                 tasklet_schedule(&jme->pcc_task);
1518         }
1519
1520         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1521                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1522                 tasklet_schedule(&jme->txclean_task);
1523         }
1524
1525         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1526                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1527                                                      INTR_PCCRX0 |
1528                                                      INTR_RX0EMP)) |
1529                                         INTR_RX0);
1530         }
1531
1532         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1533                 if (intrstat & INTR_RX0EMP)
1534                         atomic_inc(&jme->rx_empty);
1535
1536                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1537                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1538                                 jme_polling_mode(jme);
1539                                 JME_RX_SCHEDULE(jme);
1540                         }
1541                 }
1542         } else {
1543                 if (intrstat & INTR_RX0EMP) {
1544                         atomic_inc(&jme->rx_empty);
1545                         tasklet_hi_schedule(&jme->rxempty_task);
1546                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1547                         tasklet_hi_schedule(&jme->rxclean_task);
1548                 }
1549         }
1550
1551 out_reenable:
1552         /*
1553          * Re-enable interrupt
1554          */
1555         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1556 }
1557
1558 static irqreturn_t
1559 jme_intr(int irq, void *dev_id)
1560 {
1561         struct net_device *netdev = dev_id;
1562         struct jme_adapter *jme = netdev_priv(netdev);
1563         u32 intrstat;
1564
1565         intrstat = jread32(jme, JME_IEVE);
1566
1567         /*
1568          * Check if it's really an interrupt for us
1569          */
1570         if (unlikely((intrstat & INTR_ENABLE) == 0))
1571                 return IRQ_NONE;
1572
1573         /*
1574          * Check if the device still exist
1575          */
1576         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1577                 return IRQ_NONE;
1578
1579         jme_intr_msi(jme, intrstat);
1580
1581         return IRQ_HANDLED;
1582 }
1583
1584 static irqreturn_t
1585 jme_msi(int irq, void *dev_id)
1586 {
1587         struct net_device *netdev = dev_id;
1588         struct jme_adapter *jme = netdev_priv(netdev);
1589         u32 intrstat;
1590
1591         intrstat = jread32(jme, JME_IEVE);
1592
1593         jme_intr_msi(jme, intrstat);
1594
1595         return IRQ_HANDLED;
1596 }
1597
1598 static void
1599 jme_reset_link(struct jme_adapter *jme)
1600 {
1601         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1602 }
1603
1604 static void
1605 jme_restart_an(struct jme_adapter *jme)
1606 {
1607         u32 bmcr;
1608
1609         spin_lock_bh(&jme->phy_lock);
1610         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1611         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1612         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1613         spin_unlock_bh(&jme->phy_lock);
1614 }
1615
1616 static int
1617 jme_request_irq(struct jme_adapter *jme)
1618 {
1619         int rc;
1620         struct net_device *netdev = jme->dev;
1621         irq_handler_t handler = jme_intr;
1622         int irq_flags = IRQF_SHARED;
1623
1624         if (!pci_enable_msi(jme->pdev)) {
1625                 set_bit(JME_FLAG_MSI, &jme->flags);
1626                 handler = jme_msi;
1627                 irq_flags = 0;
1628         }
1629
1630         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1631                           netdev);
1632         if (rc) {
1633                 netdev_err(netdev,
1634                            "Unable to request %s interrupt (return: %d)\n",
1635                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1636                            rc);
1637
1638                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1639                         pci_disable_msi(jme->pdev);
1640                         clear_bit(JME_FLAG_MSI, &jme->flags);
1641                 }
1642         } else {
1643                 netdev->irq = jme->pdev->irq;
1644         }
1645
1646         return rc;
1647 }
1648
1649 static void
1650 jme_free_irq(struct jme_adapter *jme)
1651 {
1652         free_irq(jme->pdev->irq, jme->dev);
1653         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1654                 pci_disable_msi(jme->pdev);
1655                 clear_bit(JME_FLAG_MSI, &jme->flags);
1656                 jme->dev->irq = jme->pdev->irq;
1657         }
1658 }
1659
1660 static inline void
1661 jme_new_phy_on(struct jme_adapter *jme)
1662 {
1663         u32 reg;
1664
1665         reg = jread32(jme, JME_PHY_PWR);
1666         reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1667                  PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1668         jwrite32(jme, JME_PHY_PWR, reg);
1669
1670         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1671         reg &= ~PE1_GPREG0_PBG;
1672         reg |= PE1_GPREG0_ENBG;
1673         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1674 }
1675
1676 static inline void
1677 jme_new_phy_off(struct jme_adapter *jme)
1678 {
1679         u32 reg;
1680
1681         reg = jread32(jme, JME_PHY_PWR);
1682         reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1683                PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1684         jwrite32(jme, JME_PHY_PWR, reg);
1685
1686         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1687         reg &= ~PE1_GPREG0_PBG;
1688         reg |= PE1_GPREG0_PDD3COLD;
1689         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1690 }
1691
1692 static inline void
1693 jme_phy_on(struct jme_adapter *jme)
1694 {
1695         u32 bmcr;
1696
1697         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1698         bmcr &= ~BMCR_PDOWN;
1699         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1700
1701         if (new_phy_power_ctrl(jme->chip_main_rev))
1702                 jme_new_phy_on(jme);
1703 }
1704
1705 static inline void
1706 jme_phy_off(struct jme_adapter *jme)
1707 {
1708         u32 bmcr;
1709
1710         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1711         bmcr |= BMCR_PDOWN;
1712         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1713
1714         if (new_phy_power_ctrl(jme->chip_main_rev))
1715                 jme_new_phy_off(jme);
1716 }
1717
1718 static int
1719 jme_open(struct net_device *netdev)
1720 {
1721         struct jme_adapter *jme = netdev_priv(netdev);
1722         int rc;
1723
1724         jme_clear_pm(jme);
1725         JME_NAPI_ENABLE(jme);
1726
1727         tasklet_enable(&jme->linkch_task);
1728         tasklet_enable(&jme->txclean_task);
1729         tasklet_hi_enable(&jme->rxclean_task);
1730         tasklet_hi_enable(&jme->rxempty_task);
1731
1732         rc = jme_request_irq(jme);
1733         if (rc)
1734                 goto err_out;
1735
1736         jme_start_irq(jme);
1737
1738         jme_phy_on(jme);
1739         if (test_bit(JME_FLAG_SSET, &jme->flags))
1740                 jme_set_settings(netdev, &jme->old_ecmd);
1741         else
1742                 jme_reset_phy_processor(jme);
1743
1744         jme_reset_link(jme);
1745
1746         return 0;
1747
1748 err_out:
1749         netif_stop_queue(netdev);
1750         netif_carrier_off(netdev);
1751         return rc;
1752 }
1753
1754 static void
1755 jme_set_100m_half(struct jme_adapter *jme)
1756 {
1757         u32 bmcr, tmp;
1758
1759         jme_phy_on(jme);
1760         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1761         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1762                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1763         tmp |= BMCR_SPEED100;
1764
1765         if (bmcr != tmp)
1766                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1767
1768         if (jme->fpgaver)
1769                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1770         else
1771                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1772 }
1773
1774 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1775 static void
1776 jme_wait_link(struct jme_adapter *jme)
1777 {
1778         u32 phylink, to = JME_WAIT_LINK_TIME;
1779
1780         mdelay(1000);
1781         phylink = jme_linkstat_from_phy(jme);
1782         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1783                 mdelay(10);
1784                 phylink = jme_linkstat_from_phy(jme);
1785         }
1786 }
1787
1788 static void
1789 jme_powersave_phy(struct jme_adapter *jme)
1790 {
1791         if (jme->reg_pmcs) {
1792                 jme_set_100m_half(jme);
1793
1794                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1795                         jme_wait_link(jme);
1796
1797                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1798         } else {
1799                 jme_phy_off(jme);
1800         }
1801 }
1802
1803 static int
1804 jme_close(struct net_device *netdev)
1805 {
1806         struct jme_adapter *jme = netdev_priv(netdev);
1807
1808         netif_stop_queue(netdev);
1809         netif_carrier_off(netdev);
1810
1811         jme_stop_irq(jme);
1812         jme_free_irq(jme);
1813
1814         JME_NAPI_DISABLE(jme);
1815
1816         tasklet_disable(&jme->linkch_task);
1817         tasklet_disable(&jme->txclean_task);
1818         tasklet_disable(&jme->rxclean_task);
1819         tasklet_disable(&jme->rxempty_task);
1820
1821         jme_disable_rx_engine(jme);
1822         jme_disable_tx_engine(jme);
1823         jme_reset_mac_processor(jme);
1824         jme_free_rx_resources(jme);
1825         jme_free_tx_resources(jme);
1826         jme->phylink = 0;
1827         jme_phy_off(jme);
1828
1829         return 0;
1830 }
1831
1832 static int
1833 jme_alloc_txdesc(struct jme_adapter *jme,
1834                         struct sk_buff *skb)
1835 {
1836         struct jme_ring *txring = &(jme->txring[0]);
1837         int idx, nr_alloc, mask = jme->tx_ring_mask;
1838
1839         idx = txring->next_to_use;
1840         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1841
1842         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1843                 return -1;
1844
1845         atomic_sub(nr_alloc, &txring->nr_free);
1846
1847         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1848
1849         return idx;
1850 }
1851
1852 static void
1853 jme_fill_tx_map(struct pci_dev *pdev,
1854                 struct txdesc *txdesc,
1855                 struct jme_buffer_info *txbi,
1856                 struct page *page,
1857                 u32 page_offset,
1858                 u32 len,
1859                 u8 hidma)
1860 {
1861         dma_addr_t dmaaddr;
1862
1863         dmaaddr = pci_map_page(pdev,
1864                                 page,
1865                                 page_offset,
1866                                 len,
1867                                 PCI_DMA_TODEVICE);
1868
1869         pci_dma_sync_single_for_device(pdev,
1870                                        dmaaddr,
1871                                        len,
1872                                        PCI_DMA_TODEVICE);
1873
1874         txdesc->dw[0] = 0;
1875         txdesc->dw[1] = 0;
1876         txdesc->desc2.flags     = TXFLAG_OWN;
1877         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1878         txdesc->desc2.datalen   = cpu_to_le16(len);
1879         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1880         txdesc->desc2.bufaddrl  = cpu_to_le32(
1881                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1882
1883         txbi->mapping = dmaaddr;
1884         txbi->len = len;
1885 }
1886
1887 static void
1888 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1889 {
1890         struct jme_ring *txring = &(jme->txring[0]);
1891         struct txdesc *txdesc = txring->desc, *ctxdesc;
1892         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1893         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1894         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1895         int mask = jme->tx_ring_mask;
1896         struct skb_frag_struct *frag;
1897         u32 len;
1898
1899         for (i = 0 ; i < nr_frags ; ++i) {
1900                 frag = &skb_shinfo(skb)->frags[i];
1901                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1902                 ctxbi = txbi + ((idx + i + 2) & (mask));
1903
1904                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1905                                  frag->page_offset, frag->size, hidma);
1906         }
1907
1908         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1909         ctxdesc = txdesc + ((idx + 1) & (mask));
1910         ctxbi = txbi + ((idx + 1) & (mask));
1911         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1912                         offset_in_page(skb->data), len, hidma);
1913
1914 }
1915
1916 static int
1917 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1918 {
1919         if (unlikely(skb_shinfo(skb)->gso_size &&
1920                         skb_header_cloned(skb) &&
1921                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1922                 dev_kfree_skb(skb);
1923                 return -1;
1924         }
1925
1926         return 0;
1927 }
1928
1929 static int
1930 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1931 {
1932         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1933         if (*mss) {
1934                 *flags |= TXFLAG_LSEN;
1935
1936                 if (skb->protocol == htons(ETH_P_IP)) {
1937                         struct iphdr *iph = ip_hdr(skb);
1938
1939                         iph->check = 0;
1940                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1941                                                                 iph->daddr, 0,
1942                                                                 IPPROTO_TCP,
1943                                                                 0);
1944                 } else {
1945                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1946
1947                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1948                                                                 &ip6h->daddr, 0,
1949                                                                 IPPROTO_TCP,
1950                                                                 0);
1951                 }
1952
1953                 return 0;
1954         }
1955
1956         return 1;
1957 }
1958
1959 static void
1960 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1961 {
1962         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1963                 u8 ip_proto;
1964
1965                 switch (skb->protocol) {
1966                 case htons(ETH_P_IP):
1967                         ip_proto = ip_hdr(skb)->protocol;
1968                         break;
1969                 case htons(ETH_P_IPV6):
1970                         ip_proto = ipv6_hdr(skb)->nexthdr;
1971                         break;
1972                 default:
1973                         ip_proto = 0;
1974                         break;
1975                 }
1976
1977                 switch (ip_proto) {
1978                 case IPPROTO_TCP:
1979                         *flags |= TXFLAG_TCPCS;
1980                         break;
1981                 case IPPROTO_UDP:
1982                         *flags |= TXFLAG_UDPCS;
1983                         break;
1984                 default:
1985                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1986                         break;
1987                 }
1988         }
1989 }
1990
1991 static inline void
1992 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1993 {
1994         if (vlan_tx_tag_present(skb)) {
1995                 *flags |= TXFLAG_TAGON;
1996                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1997         }
1998 }
1999
2000 static int
2001 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2002 {
2003         struct jme_ring *txring = &(jme->txring[0]);
2004         struct txdesc *txdesc;
2005         struct jme_buffer_info *txbi;
2006         u8 flags;
2007
2008         txdesc = (struct txdesc *)txring->desc + idx;
2009         txbi = txring->bufinf + idx;
2010
2011         txdesc->dw[0] = 0;
2012         txdesc->dw[1] = 0;
2013         txdesc->dw[2] = 0;
2014         txdesc->dw[3] = 0;
2015         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2016         /*
2017          * Set OWN bit at final.
2018          * When kernel transmit faster than NIC.
2019          * And NIC trying to send this descriptor before we tell
2020          * it to start sending this TX queue.
2021          * Other fields are already filled correctly.
2022          */
2023         wmb();
2024         flags = TXFLAG_OWN | TXFLAG_INT;
2025         /*
2026          * Set checksum flags while not tso
2027          */
2028         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2029                 jme_tx_csum(jme, skb, &flags);
2030         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2031         jme_map_tx_skb(jme, skb, idx);
2032         txdesc->desc1.flags = flags;
2033         /*
2034          * Set tx buffer info after telling NIC to send
2035          * For better tx_clean timing
2036          */
2037         wmb();
2038         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2039         txbi->skb = skb;
2040         txbi->len = skb->len;
2041         txbi->start_xmit = jiffies;
2042         if (!txbi->start_xmit)
2043                 txbi->start_xmit = (0UL-1);
2044
2045         return 0;
2046 }
2047
2048 static void
2049 jme_stop_queue_if_full(struct jme_adapter *jme)
2050 {
2051         struct jme_ring *txring = &(jme->txring[0]);
2052         struct jme_buffer_info *txbi = txring->bufinf;
2053         int idx = atomic_read(&txring->next_to_clean);
2054
2055         txbi += idx;
2056
2057         smp_wmb();
2058         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2059                 netif_stop_queue(jme->dev);
2060                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2061                 smp_wmb();
2062                 if (atomic_read(&txring->nr_free)
2063                         >= (jme->tx_wake_threshold)) {
2064                         netif_wake_queue(jme->dev);
2065                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2066                 }
2067         }
2068
2069         if (unlikely(txbi->start_xmit &&
2070                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2071                         txbi->skb)) {
2072                 netif_stop_queue(jme->dev);
2073                 netif_info(jme, tx_queued, jme->dev,
2074                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
2075         }
2076 }
2077
2078 /*
2079  * This function is already protected by netif_tx_lock()
2080  */
2081
2082 static netdev_tx_t
2083 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2084 {
2085         struct jme_adapter *jme = netdev_priv(netdev);
2086         int idx;
2087
2088         if (unlikely(jme_expand_header(jme, skb))) {
2089                 ++(NET_STAT(jme).tx_dropped);
2090                 return NETDEV_TX_OK;
2091         }
2092
2093         idx = jme_alloc_txdesc(jme, skb);
2094
2095         if (unlikely(idx < 0)) {
2096                 netif_stop_queue(netdev);
2097                 netif_err(jme, tx_err, jme->dev,
2098                           "BUG! Tx ring full when queue awake!\n");
2099
2100                 return NETDEV_TX_BUSY;
2101         }
2102
2103         jme_fill_tx_desc(jme, skb, idx);
2104
2105         jwrite32(jme, JME_TXCS, jme->reg_txcs |
2106                                 TXCS_SELECT_QUEUE0 |
2107                                 TXCS_QUEUE0S |
2108                                 TXCS_ENABLE);
2109
2110         tx_dbg(jme, "xmit: %d+%d@%lu\n",
2111                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2112         jme_stop_queue_if_full(jme);
2113
2114         return NETDEV_TX_OK;
2115 }
2116
2117 static int
2118 jme_set_macaddr(struct net_device *netdev, void *p)
2119 {
2120         struct jme_adapter *jme = netdev_priv(netdev);
2121         struct sockaddr *addr = p;
2122         u32 val;
2123
2124         if (netif_running(netdev))
2125                 return -EBUSY;
2126
2127         spin_lock_bh(&jme->macaddr_lock);
2128         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2129
2130         val = (addr->sa_data[3] & 0xff) << 24 |
2131               (addr->sa_data[2] & 0xff) << 16 |
2132               (addr->sa_data[1] & 0xff) <<  8 |
2133               (addr->sa_data[0] & 0xff);
2134         jwrite32(jme, JME_RXUMA_LO, val);
2135         val = (addr->sa_data[5] & 0xff) << 8 |
2136               (addr->sa_data[4] & 0xff);
2137         jwrite32(jme, JME_RXUMA_HI, val);
2138         spin_unlock_bh(&jme->macaddr_lock);
2139
2140         return 0;
2141 }
2142
2143 static void
2144 jme_set_multi(struct net_device *netdev)
2145 {
2146         struct jme_adapter *jme = netdev_priv(netdev);
2147         u32 mc_hash[2] = {};
2148
2149         spin_lock_bh(&jme->rxmcs_lock);
2150
2151         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2152
2153         if (netdev->flags & IFF_PROMISC) {
2154                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2155         } else if (netdev->flags & IFF_ALLMULTI) {
2156                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2157         } else if (netdev->flags & IFF_MULTICAST) {
2158                 struct netdev_hw_addr *ha;
2159                 int bit_nr;
2160
2161                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2162                 netdev_for_each_mc_addr(ha, netdev) {
2163                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2164                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2165                 }
2166
2167                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2168                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2169         }
2170
2171         wmb();
2172         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2173
2174         spin_unlock_bh(&jme->rxmcs_lock);
2175 }
2176
2177 static int
2178 jme_change_mtu(struct net_device *netdev, int new_mtu)
2179 {
2180         struct jme_adapter *jme = netdev_priv(netdev);
2181
2182         if (new_mtu == jme->old_mtu)
2183                 return 0;
2184
2185         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2186                 ((new_mtu) < IPV6_MIN_MTU))
2187                 return -EINVAL;
2188
2189         if (new_mtu > 4000) {
2190                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2191                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2192                 jme_restart_rx_engine(jme);
2193         } else {
2194                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2195                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2196                 jme_restart_rx_engine(jme);
2197         }
2198
2199         if (new_mtu > 1900) {
2200                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2201                                 NETIF_F_TSO | NETIF_F_TSO6);
2202         } else {
2203                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2204                         netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2205                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2206                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2207         }
2208
2209         netdev->mtu = new_mtu;
2210         jme_reset_link(jme);
2211
2212         return 0;
2213 }
2214
2215 static void
2216 jme_tx_timeout(struct net_device *netdev)
2217 {
2218         struct jme_adapter *jme = netdev_priv(netdev);
2219
2220         jme->phylink = 0;
2221         jme_reset_phy_processor(jme);
2222         if (test_bit(JME_FLAG_SSET, &jme->flags))
2223                 jme_set_settings(netdev, &jme->old_ecmd);
2224
2225         /*
2226          * Force to Reset the link again
2227          */
2228         jme_reset_link(jme);
2229 }
2230
2231 static inline void jme_pause_rx(struct jme_adapter *jme)
2232 {
2233         atomic_dec(&jme->link_changing);
2234
2235         jme_set_rx_pcc(jme, PCC_OFF);
2236         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2237                 JME_NAPI_DISABLE(jme);
2238         } else {
2239                 tasklet_disable(&jme->rxclean_task);
2240                 tasklet_disable(&jme->rxempty_task);
2241         }
2242 }
2243
2244 static inline void jme_resume_rx(struct jme_adapter *jme)
2245 {
2246         struct dynpcc_info *dpi = &(jme->dpi);
2247
2248         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2249                 JME_NAPI_ENABLE(jme);
2250         } else {
2251                 tasklet_hi_enable(&jme->rxclean_task);
2252                 tasklet_hi_enable(&jme->rxempty_task);
2253         }
2254         dpi->cur                = PCC_P1;
2255         dpi->attempt            = PCC_P1;
2256         dpi->cnt                = 0;
2257         jme_set_rx_pcc(jme, PCC_P1);
2258
2259         atomic_inc(&jme->link_changing);
2260 }
2261
2262 static void
2263 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2264 {
2265         struct jme_adapter *jme = netdev_priv(netdev);
2266
2267         jme_pause_rx(jme);
2268         jme->vlgrp = grp;
2269         jme_resume_rx(jme);
2270 }
2271
2272 static void
2273 jme_get_drvinfo(struct net_device *netdev,
2274                      struct ethtool_drvinfo *info)
2275 {
2276         struct jme_adapter *jme = netdev_priv(netdev);
2277
2278         strcpy(info->driver, DRV_NAME);
2279         strcpy(info->version, DRV_VERSION);
2280         strcpy(info->bus_info, pci_name(jme->pdev));
2281 }
2282
2283 static int
2284 jme_get_regs_len(struct net_device *netdev)
2285 {
2286         return JME_REG_LEN;
2287 }
2288
2289 static void
2290 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2291 {
2292         int i;
2293
2294         for (i = 0 ; i < len ; i += 4)
2295                 p[i >> 2] = jread32(jme, reg + i);
2296 }
2297
2298 static void
2299 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2300 {
2301         int i;
2302         u16 *p16 = (u16 *)p;
2303
2304         for (i = 0 ; i < reg_nr ; ++i)
2305                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2306 }
2307
2308 static void
2309 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2310 {
2311         struct jme_adapter *jme = netdev_priv(netdev);
2312         u32 *p32 = (u32 *)p;
2313
2314         memset(p, 0xFF, JME_REG_LEN);
2315
2316         regs->version = 1;
2317         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2318
2319         p32 += 0x100 >> 2;
2320         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2321
2322         p32 += 0x100 >> 2;
2323         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2324
2325         p32 += 0x100 >> 2;
2326         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2327
2328         p32 += 0x100 >> 2;
2329         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2330 }
2331
2332 static int
2333 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2334 {
2335         struct jme_adapter *jme = netdev_priv(netdev);
2336
2337         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2338         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2339
2340         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2341                 ecmd->use_adaptive_rx_coalesce = false;
2342                 ecmd->rx_coalesce_usecs = 0;
2343                 ecmd->rx_max_coalesced_frames = 0;
2344                 return 0;
2345         }
2346
2347         ecmd->use_adaptive_rx_coalesce = true;
2348
2349         switch (jme->dpi.cur) {
2350         case PCC_P1:
2351                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2352                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2353                 break;
2354         case PCC_P2:
2355                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2356                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2357                 break;
2358         case PCC_P3:
2359                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2360                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2361                 break;
2362         default:
2363                 break;
2364         }
2365
2366         return 0;
2367 }
2368
2369 static int
2370 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2371 {
2372         struct jme_adapter *jme = netdev_priv(netdev);
2373         struct dynpcc_info *dpi = &(jme->dpi);
2374
2375         if (netif_running(netdev))
2376                 return -EBUSY;
2377
2378         if (ecmd->use_adaptive_rx_coalesce &&
2379             test_bit(JME_FLAG_POLL, &jme->flags)) {
2380                 clear_bit(JME_FLAG_POLL, &jme->flags);
2381                 jme->jme_rx = netif_rx;
2382                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2383                 dpi->cur                = PCC_P1;
2384                 dpi->attempt            = PCC_P1;
2385                 dpi->cnt                = 0;
2386                 jme_set_rx_pcc(jme, PCC_P1);
2387                 jme_interrupt_mode(jme);
2388         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2389                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2390                 set_bit(JME_FLAG_POLL, &jme->flags);
2391                 jme->jme_rx = netif_receive_skb;
2392                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2393                 jme_interrupt_mode(jme);
2394         }
2395
2396         return 0;
2397 }
2398
2399 static void
2400 jme_get_pauseparam(struct net_device *netdev,
2401                         struct ethtool_pauseparam *ecmd)
2402 {
2403         struct jme_adapter *jme = netdev_priv(netdev);
2404         u32 val;
2405
2406         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2407         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2408
2409         spin_lock_bh(&jme->phy_lock);
2410         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2411         spin_unlock_bh(&jme->phy_lock);
2412
2413         ecmd->autoneg =
2414                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2415 }
2416
2417 static int
2418 jme_set_pauseparam(struct net_device *netdev,
2419                         struct ethtool_pauseparam *ecmd)
2420 {
2421         struct jme_adapter *jme = netdev_priv(netdev);
2422         u32 val;
2423
2424         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2425                 (ecmd->tx_pause != 0)) {
2426
2427                 if (ecmd->tx_pause)
2428                         jme->reg_txpfc |= TXPFC_PF_EN;
2429                 else
2430                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2431
2432                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2433         }
2434
2435         spin_lock_bh(&jme->rxmcs_lock);
2436         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2437                 (ecmd->rx_pause != 0)) {
2438
2439                 if (ecmd->rx_pause)
2440                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2441                 else
2442                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2443
2444                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2445         }
2446         spin_unlock_bh(&jme->rxmcs_lock);
2447
2448         spin_lock_bh(&jme->phy_lock);
2449         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2450         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2451                 (ecmd->autoneg != 0)) {
2452
2453                 if (ecmd->autoneg)
2454                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2455                 else
2456                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2457
2458                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2459                                 MII_ADVERTISE, val);
2460         }
2461         spin_unlock_bh(&jme->phy_lock);
2462
2463         return 0;
2464 }
2465
2466 static void
2467 jme_get_wol(struct net_device *netdev,
2468                 struct ethtool_wolinfo *wol)
2469 {
2470         struct jme_adapter *jme = netdev_priv(netdev);
2471
2472         wol->supported = WAKE_MAGIC | WAKE_PHY;
2473
2474         wol->wolopts = 0;
2475
2476         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2477                 wol->wolopts |= WAKE_PHY;
2478
2479         if (jme->reg_pmcs & PMCS_MFEN)
2480                 wol->wolopts |= WAKE_MAGIC;
2481
2482 }
2483
2484 static int
2485 jme_set_wol(struct net_device *netdev,
2486                 struct ethtool_wolinfo *wol)
2487 {
2488         struct jme_adapter *jme = netdev_priv(netdev);
2489
2490         if (wol->wolopts & (WAKE_MAGICSECURE |
2491                                 WAKE_UCAST |
2492                                 WAKE_MCAST |
2493                                 WAKE_BCAST |
2494                                 WAKE_ARP))
2495                 return -EOPNOTSUPP;
2496
2497         jme->reg_pmcs = 0;
2498
2499         if (wol->wolopts & WAKE_PHY)
2500                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2501
2502         if (wol->wolopts & WAKE_MAGIC)
2503                 jme->reg_pmcs |= PMCS_MFEN;
2504
2505         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2506
2507         return 0;
2508 }
2509
2510 static int
2511 jme_get_settings(struct net_device *netdev,
2512                      struct ethtool_cmd *ecmd)
2513 {
2514         struct jme_adapter *jme = netdev_priv(netdev);
2515         int rc;
2516
2517         spin_lock_bh(&jme->phy_lock);
2518         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2519         spin_unlock_bh(&jme->phy_lock);
2520         return rc;
2521 }
2522
2523 static int
2524 jme_set_settings(struct net_device *netdev,
2525                      struct ethtool_cmd *ecmd)
2526 {
2527         struct jme_adapter *jme = netdev_priv(netdev);
2528         int rc, fdc = 0;
2529
2530         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2531                 return -EINVAL;
2532
2533         /*
2534          * Check If user changed duplex only while force_media.
2535          * Hardware would not generate link change interrupt.
2536          */
2537         if (jme->mii_if.force_media &&
2538         ecmd->autoneg != AUTONEG_ENABLE &&
2539         (jme->mii_if.full_duplex != ecmd->duplex))
2540                 fdc = 1;
2541
2542         spin_lock_bh(&jme->phy_lock);
2543         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2544         spin_unlock_bh(&jme->phy_lock);
2545
2546         if (!rc) {
2547                 if (fdc)
2548                         jme_reset_link(jme);
2549                 jme->old_ecmd = *ecmd;
2550                 set_bit(JME_FLAG_SSET, &jme->flags);
2551         }
2552
2553         return rc;
2554 }
2555
2556 static int
2557 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2558 {
2559         int rc;
2560         struct jme_adapter *jme = netdev_priv(netdev);
2561         struct mii_ioctl_data *mii_data = if_mii(rq);
2562         unsigned int duplex_chg;
2563
2564         if (cmd == SIOCSMIIREG) {
2565                 u16 val = mii_data->val_in;
2566                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2567                     (val & BMCR_SPEED1000))
2568                         return -EINVAL;
2569         }
2570
2571         spin_lock_bh(&jme->phy_lock);
2572         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2573         spin_unlock_bh(&jme->phy_lock);
2574
2575         if (!rc && (cmd == SIOCSMIIREG)) {
2576                 if (duplex_chg)
2577                         jme_reset_link(jme);
2578                 jme_get_settings(netdev, &jme->old_ecmd);
2579                 set_bit(JME_FLAG_SSET, &jme->flags);
2580         }
2581
2582         return rc;
2583 }
2584
2585 static u32
2586 jme_get_link(struct net_device *netdev)
2587 {
2588         struct jme_adapter *jme = netdev_priv(netdev);
2589         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2590 }
2591
2592 static u32
2593 jme_get_msglevel(struct net_device *netdev)
2594 {
2595         struct jme_adapter *jme = netdev_priv(netdev);
2596         return jme->msg_enable;
2597 }
2598
2599 static void
2600 jme_set_msglevel(struct net_device *netdev, u32 value)
2601 {
2602         struct jme_adapter *jme = netdev_priv(netdev);
2603         jme->msg_enable = value;
2604 }
2605
2606 static u32
2607 jme_get_rx_csum(struct net_device *netdev)
2608 {
2609         struct jme_adapter *jme = netdev_priv(netdev);
2610         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2611 }
2612
2613 static int
2614 jme_set_rx_csum(struct net_device *netdev, u32 on)
2615 {
2616         struct jme_adapter *jme = netdev_priv(netdev);
2617
2618         spin_lock_bh(&jme->rxmcs_lock);
2619         if (on)
2620                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2621         else
2622                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2623         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2624         spin_unlock_bh(&jme->rxmcs_lock);
2625
2626         return 0;
2627 }
2628
2629 static int
2630 jme_set_tx_csum(struct net_device *netdev, u32 on)
2631 {
2632         struct jme_adapter *jme = netdev_priv(netdev);
2633
2634         if (on) {
2635                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2636                 if (netdev->mtu <= 1900)
2637                         netdev->features |=
2638                                 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2639         } else {
2640                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2641                 netdev->features &=
2642                                 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2643         }
2644
2645         return 0;
2646 }
2647
2648 static int
2649 jme_set_tso(struct net_device *netdev, u32 on)
2650 {
2651         struct jme_adapter *jme = netdev_priv(netdev);
2652
2653         if (on) {
2654                 set_bit(JME_FLAG_TSO, &jme->flags);
2655                 if (netdev->mtu <= 1900)
2656                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2657         } else {
2658                 clear_bit(JME_FLAG_TSO, &jme->flags);
2659                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2660         }
2661
2662         return 0;
2663 }
2664
2665 static int
2666 jme_nway_reset(struct net_device *netdev)
2667 {
2668         struct jme_adapter *jme = netdev_priv(netdev);
2669         jme_restart_an(jme);
2670         return 0;
2671 }
2672
2673 static u8
2674 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2675 {
2676         u32 val;
2677         int to;
2678
2679         val = jread32(jme, JME_SMBCSR);
2680         to = JME_SMB_BUSY_TIMEOUT;
2681         while ((val & SMBCSR_BUSY) && --to) {
2682                 msleep(1);
2683                 val = jread32(jme, JME_SMBCSR);
2684         }
2685         if (!to) {
2686                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2687                 return 0xFF;
2688         }
2689
2690         jwrite32(jme, JME_SMBINTF,
2691                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2692                 SMBINTF_HWRWN_READ |
2693                 SMBINTF_HWCMD);
2694
2695         val = jread32(jme, JME_SMBINTF);
2696         to = JME_SMB_BUSY_TIMEOUT;
2697         while ((val & SMBINTF_HWCMD) && --to) {
2698                 msleep(1);
2699                 val = jread32(jme, JME_SMBINTF);
2700         }
2701         if (!to) {
2702                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2703                 return 0xFF;
2704         }
2705
2706         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2707 }
2708
2709 static void
2710 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2711 {
2712         u32 val;
2713         int to;
2714
2715         val = jread32(jme, JME_SMBCSR);
2716         to = JME_SMB_BUSY_TIMEOUT;
2717         while ((val & SMBCSR_BUSY) && --to) {
2718                 msleep(1);
2719                 val = jread32(jme, JME_SMBCSR);
2720         }
2721         if (!to) {
2722                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2723                 return;
2724         }
2725
2726         jwrite32(jme, JME_SMBINTF,
2727                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2728                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2729                 SMBINTF_HWRWN_WRITE |
2730                 SMBINTF_HWCMD);
2731
2732         val = jread32(jme, JME_SMBINTF);
2733         to = JME_SMB_BUSY_TIMEOUT;
2734         while ((val & SMBINTF_HWCMD) && --to) {
2735                 msleep(1);
2736                 val = jread32(jme, JME_SMBINTF);
2737         }
2738         if (!to) {
2739                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2740                 return;
2741         }
2742
2743         mdelay(2);
2744 }
2745
2746 static int
2747 jme_get_eeprom_len(struct net_device *netdev)
2748 {
2749         struct jme_adapter *jme = netdev_priv(netdev);
2750         u32 val;
2751         val = jread32(jme, JME_SMBCSR);
2752         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2753 }
2754
2755 static int
2756 jme_get_eeprom(struct net_device *netdev,
2757                 struct ethtool_eeprom *eeprom, u8 *data)
2758 {
2759         struct jme_adapter *jme = netdev_priv(netdev);
2760         int i, offset = eeprom->offset, len = eeprom->len;
2761
2762         /*
2763          * ethtool will check the boundary for us
2764          */
2765         eeprom->magic = JME_EEPROM_MAGIC;
2766         for (i = 0 ; i < len ; ++i)
2767                 data[i] = jme_smb_read(jme, i + offset);
2768
2769         return 0;
2770 }
2771
2772 static int
2773 jme_set_eeprom(struct net_device *netdev,
2774                 struct ethtool_eeprom *eeprom, u8 *data)
2775 {
2776         struct jme_adapter *jme = netdev_priv(netdev);
2777         int i, offset = eeprom->offset, len = eeprom->len;
2778
2779         if (eeprom->magic != JME_EEPROM_MAGIC)
2780                 return -EINVAL;
2781
2782         /*
2783          * ethtool will check the boundary for us
2784          */
2785         for (i = 0 ; i < len ; ++i)
2786                 jme_smb_write(jme, i + offset, data[i]);
2787
2788         return 0;
2789 }
2790
2791 static const struct ethtool_ops jme_ethtool_ops = {
2792         .get_drvinfo            = jme_get_drvinfo,
2793         .get_regs_len           = jme_get_regs_len,
2794         .get_regs               = jme_get_regs,
2795         .get_coalesce           = jme_get_coalesce,
2796         .set_coalesce           = jme_set_coalesce,
2797         .get_pauseparam         = jme_get_pauseparam,
2798         .set_pauseparam         = jme_set_pauseparam,
2799         .get_wol                = jme_get_wol,
2800         .set_wol                = jme_set_wol,
2801         .get_settings           = jme_get_settings,
2802         .set_settings           = jme_set_settings,
2803         .get_link               = jme_get_link,
2804         .get_msglevel           = jme_get_msglevel,
2805         .set_msglevel           = jme_set_msglevel,
2806         .get_rx_csum            = jme_get_rx_csum,
2807         .set_rx_csum            = jme_set_rx_csum,
2808         .set_tx_csum            = jme_set_tx_csum,
2809         .set_tso                = jme_set_tso,
2810         .set_sg                 = ethtool_op_set_sg,
2811         .nway_reset             = jme_nway_reset,
2812         .get_eeprom_len         = jme_get_eeprom_len,
2813         .get_eeprom             = jme_get_eeprom,
2814         .set_eeprom             = jme_set_eeprom,
2815 };
2816
2817 static int
2818 jme_pci_dma64(struct pci_dev *pdev)
2819 {
2820         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2821             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2822                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2823                         return 1;
2824
2825         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2826             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2827                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2828                         return 1;
2829
2830         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2831                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2832                         return 0;
2833
2834         return -1;
2835 }
2836
2837 static inline void
2838 jme_phy_init(struct jme_adapter *jme)
2839 {
2840         u16 reg26;
2841
2842         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2843         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2844 }
2845
2846 static inline void
2847 jme_check_hw_ver(struct jme_adapter *jme)
2848 {
2849         u32 chipmode;
2850
2851         chipmode = jread32(jme, JME_CHIPMODE);
2852
2853         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2854         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2855         jme->chip_main_rev = jme->chiprev & 0xF;
2856         jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2857 }
2858
2859 static const struct net_device_ops jme_netdev_ops = {
2860         .ndo_open               = jme_open,
2861         .ndo_stop               = jme_close,
2862         .ndo_validate_addr      = eth_validate_addr,
2863         .ndo_do_ioctl           = jme_ioctl,
2864         .ndo_start_xmit         = jme_start_xmit,
2865         .ndo_set_mac_address    = jme_set_macaddr,
2866         .ndo_set_multicast_list = jme_set_multi,
2867         .ndo_change_mtu         = jme_change_mtu,
2868         .ndo_tx_timeout         = jme_tx_timeout,
2869         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2870 };
2871
2872 static int __devinit
2873 jme_init_one(struct pci_dev *pdev,
2874              const struct pci_device_id *ent)
2875 {
2876         int rc = 0, using_dac, i;
2877         struct net_device *netdev;
2878         struct jme_adapter *jme;
2879         u16 bmcr, bmsr;
2880         u32 apmc;
2881
2882         /*
2883          * set up PCI device basics
2884          */
2885         rc = pci_enable_device(pdev);
2886         if (rc) {
2887                 pr_err("Cannot enable PCI device\n");
2888                 goto err_out;
2889         }
2890
2891         using_dac = jme_pci_dma64(pdev);
2892         if (using_dac < 0) {
2893                 pr_err("Cannot set PCI DMA Mask\n");
2894                 rc = -EIO;
2895                 goto err_out_disable_pdev;
2896         }
2897
2898         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2899                 pr_err("No PCI resource region found\n");
2900                 rc = -ENOMEM;
2901                 goto err_out_disable_pdev;
2902         }
2903
2904         rc = pci_request_regions(pdev, DRV_NAME);
2905         if (rc) {
2906                 pr_err("Cannot obtain PCI resource region\n");
2907                 goto err_out_disable_pdev;
2908         }
2909
2910         pci_set_master(pdev);
2911
2912         /*
2913          * alloc and init net device
2914          */
2915         netdev = alloc_etherdev(sizeof(*jme));
2916         if (!netdev) {
2917                 pr_err("Cannot allocate netdev structure\n");
2918                 rc = -ENOMEM;
2919                 goto err_out_release_regions;
2920         }
2921         netdev->netdev_ops = &jme_netdev_ops;
2922         netdev->ethtool_ops             = &jme_ethtool_ops;
2923         netdev->watchdog_timeo          = TX_TIMEOUT;
2924         netdev->features                =       NETIF_F_IP_CSUM |
2925                                                 NETIF_F_IPV6_CSUM |
2926                                                 NETIF_F_SG |
2927                                                 NETIF_F_TSO |
2928                                                 NETIF_F_TSO6 |
2929                                                 NETIF_F_HW_VLAN_TX |
2930                                                 NETIF_F_HW_VLAN_RX;
2931         if (using_dac)
2932                 netdev->features        |=      NETIF_F_HIGHDMA;
2933
2934         SET_NETDEV_DEV(netdev, &pdev->dev);
2935         pci_set_drvdata(pdev, netdev);
2936
2937         /*
2938          * init adapter info
2939          */
2940         jme = netdev_priv(netdev);
2941         jme->pdev = pdev;
2942         jme->dev = netdev;
2943         jme->jme_rx = netif_rx;
2944         jme->jme_vlan_rx = vlan_hwaccel_rx;
2945         jme->old_mtu = netdev->mtu = 1500;
2946         jme->phylink = 0;
2947         jme->tx_ring_size = 1 << 10;
2948         jme->tx_ring_mask = jme->tx_ring_size - 1;
2949         jme->tx_wake_threshold = 1 << 9;
2950         jme->rx_ring_size = 1 << 9;
2951         jme->rx_ring_mask = jme->rx_ring_size - 1;
2952         jme->msg_enable = JME_DEF_MSG_ENABLE;
2953         jme->regs = ioremap(pci_resource_start(pdev, 0),
2954                              pci_resource_len(pdev, 0));
2955         if (!(jme->regs)) {
2956                 pr_err("Mapping PCI resource region error\n");
2957                 rc = -ENOMEM;
2958                 goto err_out_free_netdev;
2959         }
2960
2961         if (no_pseudohp) {
2962                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2963                 jwrite32(jme, JME_APMC, apmc);
2964         } else if (force_pseudohp) {
2965                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2966                 jwrite32(jme, JME_APMC, apmc);
2967         }
2968
2969         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2970
2971         spin_lock_init(&jme->phy_lock);
2972         spin_lock_init(&jme->macaddr_lock);
2973         spin_lock_init(&jme->rxmcs_lock);
2974
2975         atomic_set(&jme->link_changing, 1);
2976         atomic_set(&jme->rx_cleaning, 1);
2977         atomic_set(&jme->tx_cleaning, 1);
2978         atomic_set(&jme->rx_empty, 1);
2979
2980         tasklet_init(&jme->pcc_task,
2981                      jme_pcc_tasklet,
2982                      (unsigned long) jme);
2983         tasklet_init(&jme->linkch_task,
2984                      jme_link_change_tasklet,
2985                      (unsigned long) jme);
2986         tasklet_init(&jme->txclean_task,
2987                      jme_tx_clean_tasklet,
2988                      (unsigned long) jme);
2989         tasklet_init(&jme->rxclean_task,
2990                      jme_rx_clean_tasklet,
2991                      (unsigned long) jme);
2992         tasklet_init(&jme->rxempty_task,
2993                      jme_rx_empty_tasklet,
2994                      (unsigned long) jme);
2995         tasklet_disable_nosync(&jme->linkch_task);
2996         tasklet_disable_nosync(&jme->txclean_task);
2997         tasklet_disable_nosync(&jme->rxclean_task);
2998         tasklet_disable_nosync(&jme->rxempty_task);
2999         jme->dpi.cur = PCC_P1;
3000
3001         jme->reg_ghc = 0;
3002         jme->reg_rxcs = RXCS_DEFAULT;
3003         jme->reg_rxmcs = RXMCS_DEFAULT;
3004         jme->reg_txpfc = 0;
3005         jme->reg_pmcs = PMCS_MFEN;
3006         jme->reg_gpreg1 = GPREG1_DEFAULT;
3007         set_bit(JME_FLAG_TXCSUM, &jme->flags);
3008         set_bit(JME_FLAG_TSO, &jme->flags);
3009
3010         /*
3011          * Get Max Read Req Size from PCI Config Space
3012          */
3013         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3014         jme->mrrs &= PCI_DCSR_MRRS_MASK;
3015         switch (jme->mrrs) {
3016         case MRRS_128B:
3017                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3018                 break;
3019         case MRRS_256B:
3020                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3021                 break;
3022         default:
3023                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3024                 break;
3025         }
3026
3027         /*
3028          * Must check before reset_mac_processor
3029          */
3030         jme_check_hw_ver(jme);
3031         jme->mii_if.dev = netdev;
3032         if (jme->fpgaver) {
3033                 jme->mii_if.phy_id = 0;
3034                 for (i = 1 ; i < 32 ; ++i) {
3035                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3036                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3037                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3038                                 jme->mii_if.phy_id = i;
3039                                 break;
3040                         }
3041                 }
3042
3043                 if (!jme->mii_if.phy_id) {
3044                         rc = -EIO;
3045                         pr_err("Can not find phy_id\n");
3046                         goto err_out_unmap;
3047                 }
3048
3049                 jme->reg_ghc |= GHC_LINK_POLL;
3050         } else {
3051                 jme->mii_if.phy_id = 1;
3052         }
3053         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3054                 jme->mii_if.supports_gmii = true;
3055         else
3056                 jme->mii_if.supports_gmii = false;
3057         jme->mii_if.phy_id_mask = 0x1F;
3058         jme->mii_if.reg_num_mask = 0x1F;
3059         jme->mii_if.mdio_read = jme_mdio_read;
3060         jme->mii_if.mdio_write = jme_mdio_write;
3061
3062         jme_clear_pm(jme);
3063         jme_set_phyfifo_5level(jme);
3064         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3065         if (!jme->fpgaver)
3066                 jme_phy_init(jme);
3067         jme_phy_off(jme);
3068
3069         /*
3070          * Reset MAC processor and reload EEPROM for MAC Address
3071          */
3072         jme_reset_mac_processor(jme);
3073         rc = jme_reload_eeprom(jme);
3074         if (rc) {
3075                 pr_err("Reload eeprom for reading MAC Address error\n");
3076                 goto err_out_unmap;
3077         }
3078         jme_load_macaddr(netdev);
3079
3080         /*
3081          * Tell stack that we are not ready to work until open()
3082          */
3083         netif_carrier_off(netdev);
3084
3085         rc = register_netdev(netdev);
3086         if (rc) {
3087                 pr_err("Cannot register net device\n");
3088                 goto err_out_unmap;
3089         }
3090
3091         netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3092                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3093                    "JMC250 Gigabit Ethernet" :
3094                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3095                    "JMC260 Fast Ethernet" : "Unknown",
3096                    (jme->fpgaver != 0) ? " (FPGA)" : "",
3097                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3098                    jme->pcirev, netdev->dev_addr);
3099
3100         return 0;
3101
3102 err_out_unmap:
3103         iounmap(jme->regs);
3104 err_out_free_netdev:
3105         pci_set_drvdata(pdev, NULL);
3106         free_netdev(netdev);
3107 err_out_release_regions:
3108         pci_release_regions(pdev);
3109 err_out_disable_pdev:
3110         pci_disable_device(pdev);
3111 err_out:
3112         return rc;
3113 }
3114
3115 static void __devexit
3116 jme_remove_one(struct pci_dev *pdev)
3117 {
3118         struct net_device *netdev = pci_get_drvdata(pdev);
3119         struct jme_adapter *jme = netdev_priv(netdev);
3120
3121         unregister_netdev(netdev);
3122         iounmap(jme->regs);
3123         pci_set_drvdata(pdev, NULL);
3124         free_netdev(netdev);
3125         pci_release_regions(pdev);
3126         pci_disable_device(pdev);
3127
3128 }
3129
3130 static void
3131 jme_shutdown(struct pci_dev *pdev)
3132 {
3133         struct net_device *netdev = pci_get_drvdata(pdev);
3134         struct jme_adapter *jme = netdev_priv(netdev);
3135
3136         jme_powersave_phy(jme);
3137         pci_pme_active(pdev, true);
3138 }
3139
3140 #ifdef CONFIG_PM
3141 static int
3142 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3143 {
3144         struct net_device *netdev = pci_get_drvdata(pdev);
3145         struct jme_adapter *jme = netdev_priv(netdev);
3146
3147         atomic_dec(&jme->link_changing);
3148
3149         netif_device_detach(netdev);
3150         netif_stop_queue(netdev);
3151         jme_stop_irq(jme);
3152
3153         tasklet_disable(&jme->txclean_task);
3154         tasklet_disable(&jme->rxclean_task);
3155         tasklet_disable(&jme->rxempty_task);
3156
3157         if (netif_carrier_ok(netdev)) {
3158                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3159                         jme_polling_mode(jme);
3160
3161                 jme_stop_pcc_timer(jme);
3162                 jme_disable_rx_engine(jme);
3163                 jme_disable_tx_engine(jme);
3164                 jme_reset_mac_processor(jme);
3165                 jme_free_rx_resources(jme);
3166                 jme_free_tx_resources(jme);
3167                 netif_carrier_off(netdev);
3168                 jme->phylink = 0;
3169         }
3170
3171         tasklet_enable(&jme->txclean_task);
3172         tasklet_hi_enable(&jme->rxclean_task);
3173         tasklet_hi_enable(&jme->rxempty_task);
3174
3175         pci_save_state(pdev);
3176         jme_powersave_phy(jme);
3177         pci_enable_wake(jme->pdev, PCI_D3hot, true);
3178         pci_set_power_state(pdev, PCI_D3hot);
3179
3180         return 0;
3181 }
3182
3183 static int
3184 jme_resume(struct pci_dev *pdev)
3185 {
3186         struct net_device *netdev = pci_get_drvdata(pdev);
3187         struct jme_adapter *jme = netdev_priv(netdev);
3188
3189         jme_clear_pm(jme);
3190         pci_restore_state(pdev);
3191
3192         jme_phy_on(jme);
3193         if (test_bit(JME_FLAG_SSET, &jme->flags))
3194                 jme_set_settings(netdev, &jme->old_ecmd);
3195         else
3196                 jme_reset_phy_processor(jme);
3197
3198         jme_start_irq(jme);
3199         netif_device_attach(netdev);
3200
3201         atomic_inc(&jme->link_changing);
3202
3203         jme_reset_link(jme);
3204
3205         return 0;
3206 }
3207 #endif
3208
3209 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3210         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3211         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3212         { }
3213 };
3214
3215 static struct pci_driver jme_driver = {
3216         .name           = DRV_NAME,
3217         .id_table       = jme_pci_tbl,
3218         .probe          = jme_init_one,
3219         .remove         = __devexit_p(jme_remove_one),
3220 #ifdef CONFIG_PM
3221         .suspend        = jme_suspend,
3222         .resume         = jme_resume,
3223 #endif /* CONFIG_PM */
3224         .shutdown       = jme_shutdown,
3225 };
3226
3227 static int __init
3228 jme_init_module(void)
3229 {
3230         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3231         return pci_register_driver(&jme_driver);
3232 }
3233
3234 static void __exit
3235 jme_cleanup_module(void)
3236 {
3237         pci_unregister_driver(&jme_driver);
3238 }
3239
3240 module_init(jme_init_module);
3241 module_exit(jme_cleanup_module);
3242
3243 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3244 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3245 MODULE_LICENSE("GPL");
3246 MODULE_VERSION(DRV_VERSION);
3247 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3248