2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Timeline before release:
26 * Stage 4: Basic feature support.
27 * - Implement scatter-gather offloading.
28 * Use pci_map_page on scattered sk_buff for HIGHMEM support
29 * - Implement Power Managemt related functions.
30 * - Implement Jumboframe.
33 * Stage 5: Advanced offloading support.
34 * - Implement VLAN offloading.
35 * - Implement TCP Segement offloading.
37 * Stage 6: CPU Load balancing.
39 * Along with multiple RX queue, for CPU load balancing.
42 * - Cleanup/re-orginize code, performence tuneing(alignment etc...).
43 * - Test and Release 1.0
46 * - Use NAPI instead of rx_tasklet?
47 * PCC Support Both Packet Counter and Timeout Interrupt for
48 * receive and transmit complete, does NAPI really needed?
49 * - Decode register dump for ethtool.
52 #include <linux/version.h>
53 #include <linux/module.h>
54 #include <linux/kernel.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/ethtool.h>
59 #include <linux/mii.h>
60 #include <linux/crc32.h>
61 #include <linux/delay.h>
66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
67 static struct net_device_stats *
68 jme_get_stats(struct net_device *netdev)
70 struct jme_adapter *jme = netdev_priv(netdev);
76 jme_mdio_read(struct net_device *netdev, int phy, int reg)
78 struct jme_adapter *jme = netdev_priv(netdev);
81 jwrite32(jme, JME_SMI, SMI_OP_REQ |
86 for (i = JME_PHY_TIMEOUT; i > 0; --i) {
88 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
93 jeprintk(netdev->name, "phy read timeout : %d\n", reg);
97 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
101 jme_mdio_write(struct net_device *netdev,
102 int phy, int reg, int val)
104 struct jme_adapter *jme = netdev_priv(netdev);
107 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
108 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
109 smi_phy_addr(phy) | smi_reg_addr(reg));
112 for (i = JME_PHY_TIMEOUT ; i > 0 ; --i) {
114 if (((val = jread32(jme, JME_SMI)) & SMI_OP_REQ) == 0)
119 jeprintk(netdev->name, "phy write timeout : %d\n", reg);
124 __always_inline static void
125 jme_reset_phy_processor(struct jme_adapter *jme)
129 jme_mdio_write(jme->dev,
131 MII_ADVERTISE, ADVERTISE_ALL |
132 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
134 jme_mdio_write(jme->dev,
137 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
139 val = jme_mdio_read(jme->dev,
143 jme_mdio_write(jme->dev,
145 MII_BMCR, val | BMCR_RESET);
151 __always_inline static void
152 jme_reset_mac_processor(struct jme_adapter *jme)
154 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
156 jwrite32(jme, JME_GHC, jme->reg_ghc);
157 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
158 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
159 jwrite32(jme, JME_WFODP, 0);
160 jwrite32(jme, JME_WFOI, 0);
161 jwrite32(jme, JME_GPREG0, GPREG0_DEFAULT);
162 jwrite32(jme, JME_GPREG1, 0);
165 __always_inline static void
166 jme_clear_pm(struct jme_adapter *jme)
168 jwrite32(jme, JME_PMCS, 0xFFFF0000);
169 pci_set_power_state(jme->pdev, PCI_D0);
173 jme_reload_eeprom(struct jme_adapter *jme)
178 val = jread32(jme, JME_SMBCSR);
180 if(val & SMBCSR_EEPROMD)
183 jwrite32(jme, JME_SMBCSR, val);
184 val |= SMBCSR_RELOAD;
185 jwrite32(jme, JME_SMBCSR, val);
188 for (i = JME_SMB_TIMEOUT; i > 0; --i)
191 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
196 jeprintk(jme->dev->name, "eeprom reload timeout\n");
207 jme_load_macaddr(struct net_device *netdev)
209 struct jme_adapter *jme = netdev_priv(netdev);
210 unsigned char macaddr[6];
213 spin_lock(&jme->macaddr_lock);
214 val = jread32(jme, JME_RXUMA_LO);
215 macaddr[0] = (val >> 0) & 0xFF;
216 macaddr[1] = (val >> 8) & 0xFF;
217 macaddr[2] = (val >> 16) & 0xFF;
218 macaddr[3] = (val >> 24) & 0xFF;
219 val = jread32(jme, JME_RXUMA_HI);
220 macaddr[4] = (val >> 0) & 0xFF;
221 macaddr[5] = (val >> 8) & 0xFF;
222 memcpy(netdev->dev_addr, macaddr, 6);
223 spin_unlock(&jme->macaddr_lock);
226 __always_inline static void
227 jme_set_rx_pcc(struct jme_adapter *jme, int p)
231 jwrite32(jme, JME_PCCRX0,
232 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
233 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
236 jwrite32(jme, JME_PCCRX0,
237 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
238 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
241 jwrite32(jme, JME_PCCRX0,
242 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
243 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
249 dprintk(jme->dev->name, "Switched to PCC_P%d\n", p);
253 jme_start_irq(struct jme_adapter *jme)
255 register struct dynpcc_info *dpi = &(jme->dpi);
257 jme_set_rx_pcc(jme, PCC_P1);
259 dpi->check_point = jiffies + PCC_INTERVAL;
260 dpi->last_bytes = NET_STAT(jme).rx_bytes;
261 dpi->last_pkts = NET_STAT(jme).rx_packets;
263 dpi->attempt = PCC_P1;
266 jwrite32(jme, JME_PCCTX,
267 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
268 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
275 jwrite32(jme, JME_IENS, INTR_ENABLE);
278 __always_inline static void
279 jme_stop_irq(struct jme_adapter *jme)
284 jwrite32(jme, JME_IENC, INTR_ENABLE);
288 __always_inline static void
289 jme_enable_shadow(struct jme_adapter *jme)
293 ((__u32)jme->shadow_dma & ~((__u32)0x1F)) | SHBA_POSTEN);
296 __always_inline static void
297 jme_disable_shadow(struct jme_adapter *jme)
299 jwrite32(jme, JME_SHBA_LO, 0x0);
303 jme_check_link(struct net_device *netdev, int testonly)
305 struct jme_adapter *jme = netdev_priv(netdev);
306 __u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr;
310 phylink = jread32(jme, JME_PHY_LINK);
312 if (phylink & PHY_LINK_UP) {
313 if(!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
315 * If we did not enable AN
316 * Speed/Duplex Info should be obtained from SMI
318 phylink = PHY_LINK_UP;
320 bmcr = jme_mdio_read(jme->dev,
324 phylink |= ((bmcr & BMCR_SPEED1000) &&
325 (bmcr & BMCR_SPEED100) == 0) ?
326 PHY_LINK_SPEED_1000M :
327 (bmcr & BMCR_SPEED100) ?
328 PHY_LINK_SPEED_100M :
331 phylink |= (bmcr & BMCR_FULLDPLX) ?
336 * Keep polling for speed/duplex resolve complete
338 while(!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
342 phylink = jread32(jme, JME_PHY_LINK);
347 jeprintk(netdev->name,
348 "Waiting speed resolve timeout.\n");
351 if(jme->phylink == phylink) {
358 jme->phylink = phylink;
360 switch(phylink & PHY_LINK_SPEED_MASK) {
361 case PHY_LINK_SPEED_10M:
363 strcpy(linkmsg, "10 Mbps, ");
365 case PHY_LINK_SPEED_100M:
366 ghc = GHC_SPEED_100M;
367 strcpy(linkmsg, "100 Mbps, ");
369 case PHY_LINK_SPEED_1000M:
370 ghc = GHC_SPEED_1000M;
371 strcpy(linkmsg, "1000 Mbps, ");
377 ghc |= (phylink & PHY_LINK_DUPLEX) ? GHC_DPX : 0;
379 strcat(linkmsg, (phylink &PHY_LINK_DUPLEX) ?
383 if(phylink & PHY_LINK_MDI_STAT)
384 strcat(linkmsg, "MDI-X");
386 strcat(linkmsg, "MDI");
388 if(phylink & PHY_LINK_DUPLEX)
389 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
391 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
395 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
396 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
398 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
402 jwrite32(jme, JME_GHC, ghc);
404 jprintk(netdev->name, "Link is up at %s.\n", linkmsg);
405 netif_carrier_on(netdev);
411 jprintk(netdev->name, "Link is down.\n");
413 netif_carrier_off(netdev);
422 jme_alloc_txdesc(struct jme_adapter *jme,
425 struct jme_ring *txring = jme->txring;
428 idx = txring->next_to_use;
430 if(unlikely(txring->nr_free < nr_alloc))
433 spin_lock(&jme->tx_lock);
434 txring->nr_free -= nr_alloc;
436 if((txring->next_to_use += nr_alloc) >= RING_DESC_NR)
437 txring->next_to_use -= RING_DESC_NR;
438 spin_unlock(&jme->tx_lock);
444 jme_set_new_txdesc(struct jme_adapter *jme,
447 struct jme_ring *txring = jme->txring;
448 volatile struct txdesc *txdesc = txring->desc, *ctxdesc;
449 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
455 idx = jme_alloc_txdesc(jme, nr_desc);
458 return NETDEV_TX_BUSY;
460 for(i = 1 ; i < nr_desc ; ++i) {
461 ctxdesc = txdesc + ((idx + i) & (RING_DESC_NR-1));
462 ctxbi = txbi + ((idx + i) & (RING_DESC_NR-1));
464 dmaaddr = pci_map_single(jme->pdev,
469 pci_dma_sync_single_for_device(jme->pdev,
476 ctxdesc->desc2.flags = TXFLAG_OWN;
477 if(jme->dev->features & NETIF_F_HIGHDMA)
478 ctxdesc->desc2.flags |= TXFLAG_64BIT;
479 ctxdesc->desc2.datalen = cpu_to_le16(skb->len);
480 ctxdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
481 ctxdesc->desc2.bufaddrl = cpu_to_le32(
482 (__u64)dmaaddr & 0xFFFFFFFFUL);
484 ctxbi->mapping = dmaaddr;
485 ctxbi->len = skb->len;
488 ctxdesc = txdesc + idx;
495 ctxdesc->desc1.pktsize = cpu_to_le16(skb->len);
497 * Set OWN bit at final.
498 * When kernel transmit faster than NIC.
499 * And NIC trying to send this descriptor before we tell
500 * it to start sending this TX queue.
501 * Other fields are already filled correctly.
504 flags = TXFLAG_OWN | TXFLAG_INT;
505 if(skb->ip_summed == CHECKSUM_PARTIAL) {
506 //flags |= TXFLAG_IPCS;
508 switch(ip_hdr(skb)->protocol) {
510 flags |= TXFLAG_TCPCS;
513 flags |= TXFLAG_UDPCS;
519 ctxdesc->desc1.flags = flags;
521 * Set tx buffer info after telling NIC to send
522 * For better tx_clean timing
525 ctxbi->nr_desc = nr_desc;
528 tx_dbg(jme->dev->name, "Xmit: %d+%d\n", idx, nr_desc);
535 jme_setup_tx_resources(struct jme_adapter *jme)
537 struct jme_ring *txring = &(jme->txring[0]);
539 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
546 txring->dmaalloc = 0;
554 txring->desc = (void*)ALIGN((unsigned long)(txring->alloc),
556 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
557 txring->next_to_use = 0;
558 txring->next_to_clean = 0;
559 txring->nr_free = RING_DESC_NR;
562 * Initiallize Transmit Descriptors
564 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE);
565 memset(txring->bufinf, 0,
566 sizeof(struct jme_buffer_info) * RING_DESC_NR);
572 jme_free_tx_resources(struct jme_adapter *jme)
575 struct jme_ring *txring = &(jme->txring[0]);
576 struct jme_buffer_info *txbi = txring->bufinf;
579 for(i = 0 ; i < RING_DESC_NR ; ++i) {
580 txbi = txring->bufinf + i;
582 dev_kfree_skb(txbi->skb);
590 dma_free_coherent(&(jme->pdev->dev),
595 txring->alloc = NULL;
597 txring->dmaalloc = 0;
600 txring->next_to_use = 0;
601 txring->next_to_clean = 0;
606 __always_inline static void
607 jme_enable_tx_engine(struct jme_adapter *jme)
612 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
615 * Setup TX Queue 0 DMA Bass Address
617 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
618 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
619 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
622 * Setup TX Descptor Count
624 jwrite32(jme, JME_TXQDC, RING_DESC_NR);
630 jwrite32(jme, JME_TXCS, jme->reg_txcs |
636 __always_inline static void
637 jme_disable_tx_engine(struct jme_adapter *jme)
645 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
647 val = jread32(jme, JME_TXCS);
648 for(i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i)
651 val = jread32(jme, JME_TXCS);
655 jeprintk(jme->dev->name, "Disable TX engine timeout.\n");
656 jme_reset_mac_processor(jme);
663 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
665 struct jme_ring *rxring = jme->rxring;
666 register volatile struct rxdesc* rxdesc = rxring->desc;
667 struct jme_buffer_info *rxbi = rxring->bufinf;
673 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
674 rxdesc->desc1.bufaddrl = cpu_to_le32(
675 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
676 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
677 if(jme->dev->features & NETIF_F_HIGHDMA)
678 rxdesc->desc1.flags = RXFLAG_64BIT;
680 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
684 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
686 struct jme_ring *rxring = &(jme->rxring[0]);
687 struct jme_buffer_info *rxbi = rxring->bufinf;
688 unsigned long offset;
691 skb = netdev_alloc_skb(jme->dev, RX_BUF_ALLOC_SIZE);
695 if(unlikely(skb_is_nonlinear(skb))) {
696 dprintk(jme->dev->name,
697 "Allocated skb fragged(%d).\n",
698 skb_shinfo(skb)->nr_frags);
704 (unsigned long)(skb->data)
705 & (unsigned long)(RX_BUF_DMA_ALIGN - 1)))
706 skb_reserve(skb, RX_BUF_DMA_ALIGN - offset);
710 rxbi->len = skb_tailroom(skb);
711 rxbi->mapping = pci_map_single(jme->pdev,
720 jme_free_rx_buf(struct jme_adapter *jme, int i)
722 struct jme_ring *rxring = &(jme->rxring[0]);
723 struct jme_buffer_info *rxbi = rxring->bufinf;
727 pci_unmap_single(jme->pdev,
731 dev_kfree_skb(rxbi->skb);
739 jme_free_rx_resources(struct jme_adapter *jme)
742 struct jme_ring *rxring = &(jme->rxring[0]);
745 for(i = 0 ; i < RING_DESC_NR ; ++i)
746 jme_free_rx_buf(jme, i);
748 dma_free_coherent(&(jme->pdev->dev),
752 rxring->alloc = NULL;
754 rxring->dmaalloc = 0;
757 rxring->next_to_use = 0;
758 rxring->next_to_clean = 0;
762 jme_setup_rx_resources(struct jme_adapter *jme)
765 struct jme_ring *rxring = &(jme->rxring[0]);
767 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
773 rxring->dmaalloc = 0;
781 rxring->desc = (void*)ALIGN((unsigned long)(rxring->alloc),
783 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
784 rxring->next_to_use = 0;
785 rxring->next_to_clean = 0;
788 * Initiallize Receive Descriptors
790 for(i = 0 ; i < RING_DESC_NR ; ++i) {
791 if(unlikely(jme_make_new_rx_buf(jme, i))) {
792 jme_free_rx_resources(jme);
796 jme_set_clean_rxdesc(jme, i);
802 __always_inline static void
803 jme_enable_rx_engine(struct jme_adapter *jme)
806 * Setup RX DMA Bass Address
808 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
809 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
810 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
813 * Setup RX Descptor Count
815 jwrite32(jme, JME_RXQDC, RING_DESC_NR);
818 * Setup Unicast Filter
820 jme_set_multi(jme->dev);
826 jwrite32(jme, JME_RXCS, RXCS_DEFAULT |
832 __always_inline static void
833 jme_restart_rx_engine(struct jme_adapter *jme)
838 jwrite32(jme, JME_RXCS, RXCS_DEFAULT |
845 __always_inline static void
846 jme_disable_rx_engine(struct jme_adapter *jme)
854 val = jread32(jme, JME_RXCS);
856 jwrite32(jme, JME_RXCS, val);
858 val = jread32(jme, JME_RXCS);
859 for(i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i)
862 val = jread32(jme, JME_RXCS);
866 jeprintk(jme->dev->name, "Disable RX engine timeout.\n");
871 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
873 if(dpi->attempt == atmp) {
883 jme_dynamic_pcc(struct jme_adapter *jme)
885 register struct dynpcc_info *dpi = &(jme->dpi);
887 if(jiffies >= dpi->check_point) {
888 if(jiffies > (dpi->check_point + PCC_INTERVAL))
889 jme_attempt_pcc(dpi, PCC_P1);
890 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) >
892 jme_attempt_pcc(dpi, PCC_P3);
893 else if((NET_STAT(jme).rx_bytes - dpi->last_bytes) >
895 jme_attempt_pcc(dpi, PCC_P2);
897 jme_attempt_pcc(dpi, PCC_P1);
899 if(unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
900 jme_set_rx_pcc(jme, dpi->attempt);
901 dpi->cur = dpi->attempt;
905 dpi->last_bytes = NET_STAT(jme).rx_bytes;
906 dpi->last_pkts = NET_STAT(jme).rx_packets;
907 dpi->check_point = jiffies + PCC_INTERVAL;
912 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
914 struct jme_ring *rxring = &(jme->rxring[0]);
915 volatile struct rxdesc *rxdesc = rxring->desc;
916 struct jme_buffer_info *rxbi = rxring->bufinf;
924 pci_dma_sync_single_for_cpu(jme->pdev,
929 if(unlikely(jme_make_new_rx_buf(jme, idx))) {
930 pci_dma_sync_single_for_device(jme->pdev,
935 ++(NET_STAT(jme).rx_dropped);
938 framesize = le16_to_cpu(rxdesc->descwb.framesize)
941 skb_reserve(skb, RX_PREPAD_SIZE);
942 skb_put(skb, framesize);
943 skb->protocol = eth_type_trans(skb, jme->dev);
945 if(jme->reg_rxmcs & RXMCS_CHECKSUM)
946 skb->ip_summed = CHECKSUM_UNNECESSARY;
950 if(le16_to_cpu(rxdesc->descwb.flags) & RXWBFLAG_DEST_MUL)
951 ++(NET_STAT(jme).multicast);
953 jme->dev->last_rx = jiffies;
954 NET_STAT(jme).rx_bytes += framesize;
955 ++(NET_STAT(jme).rx_packets);
958 jme_set_clean_rxdesc(jme, idx);
960 jme_dynamic_pcc(jme);
965 jme_rxsum_bad(struct jme_adapter *jme, __u16 flags)
967 if(jme->reg_rxmcs & RXMCS_CHECKSUM) {
968 return ((flags & RXWBFLAG_IPV4) &&
969 !(flags & RXWBFLAG_IPCS)) ||
970 ((flags & RXWBFLAG_IPV6) &&
971 !(flags & RXWBFLAG_IPCS)) ||
972 ((flags & RXWBFLAG_TCPON) &&
973 !(flags & RXWBFLAG_TCPCS)) ||
974 ((flags & RXWBFLAG_UDPON) &&
975 !(flags & RXWBFLAG_UDPCS));
983 jme_process_receive(struct jme_adapter *jme, int limit)
985 struct jme_ring *rxring = &(jme->rxring[0]);
986 volatile struct rxdesc *rxdesc = rxring->desc;
987 int i, j, ccnt, desccnt;
989 i = rxring->next_to_clean;
992 rxdesc = rxring->desc;
995 if((rxdesc->descwb.flags & RXWBFLAG_OWN) ||
996 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
999 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1001 rx_dbg(jme->dev->name, "RX: Cleaning %d\n", i);
1003 if(unlikely(desccnt > 1 ||
1004 rxdesc->descwb.errstat & RXWBERR_ALLERR ||
1005 jme_rxsum_bad(jme, rxdesc->descwb.flags))) {
1007 if(rxdesc->descwb.errstat & RXWBERR_CRCERR)
1008 ++(NET_STAT(jme).rx_crc_errors);
1009 else if(rxdesc->descwb.errstat & RXWBERR_OVERUN)
1010 ++(NET_STAT(jme).rx_fifo_errors);
1012 ++(NET_STAT(jme).rx_errors);
1015 limit -= desccnt - 1;
1017 for(j = i, ccnt = desccnt ; ccnt-- ; ) {
1018 jme_set_clean_rxdesc(jme, j);
1020 if(unlikely(++j == RING_DESC_NR))
1026 jme_alloc_and_feed_skb(jme, i);
1030 if((i += desccnt) >= RING_DESC_NR)
1035 rx_dbg(jme->dev->name, "RX: Stop at %d\n", i);
1036 rx_dbg(jme->dev->name, "RX: RXNDA offset %d\n",
1037 (jread32(jme, JME_RXNDA) - jread32(jme, JME_RXDBA_LO))
1040 rxring->next_to_clean = i;
1042 return limit > 0 ? limit : 0;
1047 jme_link_change_tasklet(unsigned long arg)
1049 struct jme_adapter *jme = (struct jme_adapter*)arg;
1050 struct net_device *netdev = jme->dev;
1051 int timeout = WAIT_TASKLET_TIMEOUT;
1054 if(!atomic_dec_and_test(&jme->link_changing))
1057 if(jme_check_link(netdev, 1))
1060 netif_stop_queue(netdev);
1062 while(--timeout > 0 &&
1064 atomic_read(&jme->rx_cleaning) != 1 ||
1065 atomic_read(&jme->tx_cleaning) != 1
1071 if(netif_carrier_ok(netdev)) {
1072 jme_reset_mac_processor(jme);
1073 jme_free_rx_resources(jme);
1074 jme_free_tx_resources(jme);
1077 jme_check_link(netdev, 0);
1078 if(netif_carrier_ok(netdev)) {
1079 rc = jme_setup_rx_resources(jme);
1081 jeprintk(netdev->name,
1082 "Allocating resources for RX error"
1083 ", Device STOPPED!\n");
1088 rc = jme_setup_tx_resources(jme);
1090 jeprintk(netdev->name,
1091 "Allocating resources for TX error"
1092 ", Device STOPPED!\n");
1093 goto err_out_free_rx_resources;
1096 jme_enable_rx_engine(jme);
1097 jme_enable_tx_engine(jme);
1099 netif_start_queue(netdev);
1104 err_out_free_rx_resources:
1105 jme_free_rx_resources(jme);
1107 atomic_inc(&jme->link_changing);
1111 jme_rx_clean_tasklet(unsigned long arg)
1113 struct jme_adapter *jme = (struct jme_adapter*)arg;
1115 if(!atomic_dec_and_test(&jme->rx_cleaning))
1118 if(atomic_read(&jme->link_changing) != 1)
1121 if(unlikely(netif_queue_stopped(jme->dev)))
1124 jme_process_receive(jme, RING_DESC_NR);
1127 atomic_inc(&jme->rx_cleaning);
1131 jme_rx_empty_tasklet(unsigned long arg)
1133 struct jme_adapter *jme = (struct jme_adapter*)arg;
1135 if(atomic_read(&jme->link_changing) != 1)
1138 if(unlikely(netif_queue_stopped(jme->dev)))
1141 jme_rx_clean_tasklet(arg);
1142 jme_restart_rx_engine(jme);
1146 jme_tx_clean_tasklet(unsigned long arg)
1148 struct jme_adapter *jme = (struct jme_adapter*)arg;
1149 struct jme_ring *txring = &(jme->txring[0]);
1150 volatile struct txdesc *txdesc = txring->desc;
1151 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1152 int i, j, cnt = 0, max, err;
1154 if(!atomic_dec_and_test(&jme->tx_cleaning))
1157 if(atomic_read(&jme->link_changing) != 1)
1160 if(unlikely(netif_queue_stopped(jme->dev)))
1163 spin_lock(&jme->tx_lock);
1164 max = RING_DESC_NR - txring->nr_free;
1165 spin_unlock(&jme->tx_lock);
1167 tx_dbg(jme->dev->name, "Tx Tasklet: In\n");
1169 for(i = txring->next_to_clean ; cnt < max ; ) {
1173 if(ctxbi->skb && !(txdesc[i].descwb.flags & TXWBFLAG_OWN)) {
1175 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1177 tx_dbg(jme->dev->name,
1178 "Tx Tasklet: Clean %d+%d\n",
1181 for(j = 1 ; j < ctxbi->nr_desc ; ++j) {
1182 ttxbi = txbi + ((i + j) & (RING_DESC_NR - 1));
1183 txdesc[(i+j)&(RING_DESC_NR-1)].dw[0] = 0;
1185 pci_unmap_single(jme->pdev,
1191 NET_STAT(jme).tx_bytes += ttxbi->len;
1197 dev_kfree_skb(ctxbi->skb);
1200 cnt += ctxbi->nr_desc;
1203 ++(NET_STAT(jme).tx_carrier_errors);
1205 ++(NET_STAT(jme).tx_packets);
1209 tx_dbg(jme->dev->name,
1211 " Stoped due to no skb.\n");
1213 tx_dbg(jme->dev->name,
1215 "Stoped due to not done.\n");
1219 if(unlikely((i += ctxbi->nr_desc) >= RING_DESC_NR))
1225 tx_dbg(jme->dev->name,
1226 "Tx Tasklet: Stop %d Jiffies %lu\n",
1228 txring->next_to_clean = i;
1230 spin_lock(&jme->tx_lock);
1231 txring->nr_free += cnt;
1232 spin_unlock(&jme->tx_lock);
1235 atomic_inc(&jme->tx_cleaning);
1239 jme_intr(int irq, void *dev_id)
1241 struct net_device *netdev = dev_id;
1242 struct jme_adapter *jme = netdev_priv(netdev);
1243 irqreturn_t rc = IRQ_HANDLED;
1247 pci_dma_sync_single_for_cpu(jme->pdev,
1249 sizeof(__u32) * SHADOW_REG_NR,
1250 PCI_DMA_FROMDEVICE);
1251 intrstat = jme->shadow_regs[SHADOW_IEVE];
1252 jme->shadow_regs[SHADOW_IEVE] = 0;
1254 intrstat = jread32(jme, JME_IEVE);
1258 * Check if it's really an interrupt for us
1266 * Check if the device still exist
1268 if(unlikely(intrstat == ~((typeof(intrstat))0))) {
1274 * Allow one interrupt handling at a time
1276 if(unlikely(!atomic_dec_and_test(&jme->intr_sem)))
1282 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1284 if(intrstat & INTR_LINKCH) {
1285 tasklet_schedule(&jme->linkch_task);
1289 if(intrstat & INTR_RX0EMP)
1290 tasklet_schedule(&jme->rxempty_task);
1292 if(intrstat & (INTR_PCCRX0TO | INTR_PCCRX0))
1293 tasklet_schedule(&jme->rxclean_task);
1295 if(intrstat & (INTR_PCCTXTO | INTR_PCCTX))
1296 tasklet_schedule(&jme->txclean_task);
1298 if((intrstat & ~INTR_ENABLE) != 0) {
1300 * Some interrupt not handled
1301 * but not enabled also (for debug)
1307 * Deassert interrupts
1309 jwrite32f(jme, JME_IEVE, intrstat);
1312 * Re-enable interrupt
1314 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1318 * Enable next interrupt handling
1320 atomic_inc(&jme->intr_sem);
1327 jme_restart_an(struct jme_adapter *jme)
1331 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1332 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1333 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1337 jme_open(struct net_device *netdev)
1339 struct jme_adapter *jme = netdev_priv(netdev);
1340 int rc, timeout = 100;
1345 atomic_read(&jme->link_changing) != 1 ||
1346 atomic_read(&jme->rx_cleaning) != 1 ||
1347 atomic_read(&jme->tx_cleaning) != 1
1352 jme_reset_mac_processor(jme);
1354 rc = request_irq(jme->pdev->irq, jme_intr,
1355 IRQF_SHARED, netdev->name, netdev);
1357 printk(KERN_ERR PFX "Requesting IRQ error.\n");
1360 jme_enable_shadow(jme);
1362 jme_restart_an(jme);
1367 netif_stop_queue(netdev);
1368 netif_carrier_off(netdev);
1373 jme_close(struct net_device *netdev)
1375 struct jme_adapter *jme = netdev_priv(netdev);
1377 netif_stop_queue(netdev);
1378 netif_carrier_off(netdev);
1381 jme_disable_shadow(jme);
1382 free_irq(jme->pdev->irq, jme->dev);
1384 tasklet_kill(&jme->linkch_task);
1385 tasklet_kill(&jme->txclean_task);
1386 tasklet_kill(&jme->rxclean_task);
1387 tasklet_kill(&jme->rxempty_task);
1389 jme_reset_mac_processor(jme);
1390 jme_free_rx_resources(jme);
1391 jme_free_tx_resources(jme);
1397 * This function is already protected by netif_tx_lock()
1400 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1402 struct jme_adapter *jme = netdev_priv(netdev);
1405 if(unlikely(netif_queue_stopped(jme->dev)))
1406 return NETDEV_TX_BUSY;
1408 rc = jme_set_new_txdesc(jme, skb);
1410 if(unlikely(rc != NETDEV_TX_OK))
1413 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1414 TXCS_SELECT_QUEUE0 |
1417 netdev->trans_start = jiffies;
1419 return NETDEV_TX_OK;
1423 jme_set_macaddr(struct net_device *netdev, void *p)
1425 struct jme_adapter *jme = netdev_priv(netdev);
1426 struct sockaddr *addr = p;
1429 if(netif_running(netdev))
1432 spin_lock(&jme->macaddr_lock);
1433 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1435 val = addr->sa_data[3] << 24 |
1436 addr->sa_data[2] << 16 |
1437 addr->sa_data[1] << 8 |
1439 jwrite32(jme, JME_RXUMA_LO, val);
1440 val = addr->sa_data[5] << 8 |
1442 jwrite32(jme, JME_RXUMA_HI, val);
1443 spin_unlock(&jme->macaddr_lock);
1449 jme_set_multi(struct net_device *netdev)
1451 struct jme_adapter *jme = netdev_priv(netdev);
1452 u32 mc_hash[2] = {};
1454 unsigned long flags;
1456 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1458 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1460 if (netdev->flags & IFF_PROMISC) {
1461 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1463 else if (netdev->flags & IFF_ALLMULTI) {
1464 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1466 else if(netdev->flags & IFF_MULTICAST) {
1467 struct dev_mc_list *mclist;
1470 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1471 for (i = 0, mclist = netdev->mc_list;
1472 mclist && i < netdev->mc_count;
1473 ++i, mclist = mclist->next) {
1475 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
1476 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
1479 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
1480 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
1484 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1486 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1490 jme_change_mtu(struct net_device *netdev, int new_mtu)
1493 * Not supporting MTU change for now.
1499 jme_tx_timeout(struct net_device *netdev)
1501 struct jme_adapter *jme = netdev_priv(netdev);
1505 * And the link change will reinitiallize all RX/TX resources
1507 jme_restart_an(jme);
1511 jme_get_drvinfo(struct net_device *netdev,
1512 struct ethtool_drvinfo *info)
1514 struct jme_adapter *jme = netdev_priv(netdev);
1516 strcpy(info->driver, DRV_NAME);
1517 strcpy(info->version, DRV_VERSION);
1518 strcpy(info->bus_info, pci_name(jme->pdev));
1522 jme_get_regs_len(struct net_device *netdev)
1528 mmapio_memcpy(struct jme_adapter *jme, __u32 *p, __u32 reg, int len)
1532 for(i = 0 ; i < len ; i += 4)
1533 p[i>>2] = jread32(jme, reg + i);
1538 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
1540 struct jme_adapter *jme = netdev_priv(netdev);
1541 __u32 *p32 = (__u32*)p;
1543 memset(p, 0, 0x400);
1546 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
1549 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
1552 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
1555 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
1560 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
1562 struct jme_adapter *jme = netdev_priv(netdev);
1564 ecmd->use_adaptive_rx_coalesce = true;
1565 ecmd->tx_coalesce_usecs = PCC_TX_TO;
1566 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
1568 switch(jme->dpi.cur) {
1570 ecmd->rx_coalesce_usecs = PCC_P1_TO;
1571 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
1574 ecmd->rx_coalesce_usecs = PCC_P2_TO;
1575 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
1578 ecmd->rx_coalesce_usecs = PCC_P3_TO;
1579 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
1589 jme_get_pauseparam(struct net_device *netdev,
1590 struct ethtool_pauseparam *ecmd)
1592 struct jme_adapter *jme = netdev_priv(netdev);
1593 unsigned long flags;
1596 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
1597 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
1599 spin_lock_irqsave(&jme->phy_lock, flags);
1600 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1601 spin_unlock_irqrestore(&jme->phy_lock, flags);
1602 ecmd->autoneg = (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
1606 jme_set_pauseparam(struct net_device *netdev,
1607 struct ethtool_pauseparam *ecmd)
1609 struct jme_adapter *jme = netdev_priv(netdev);
1610 unsigned long flags;
1613 if( ((jme->reg_txpfc & TXPFC_PF_EN) != 0) !=
1614 (ecmd->tx_pause != 0)) {
1617 jme->reg_txpfc |= TXPFC_PF_EN;
1619 jme->reg_txpfc &= ~TXPFC_PF_EN;
1621 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
1624 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1625 if( ((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) !=
1626 (ecmd->rx_pause != 0)) {
1629 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
1631 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
1633 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1635 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1637 spin_lock_irqsave(&jme->phy_lock, flags);
1638 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
1639 if( ((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) !=
1640 (ecmd->autoneg != 0)) {
1643 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1645 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1647 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE, val);
1649 spin_unlock_irqrestore(&jme->phy_lock, flags);
1655 jme_get_settings(struct net_device *netdev,
1656 struct ethtool_cmd *ecmd)
1658 struct jme_adapter *jme = netdev_priv(netdev);
1661 spin_lock(&jme->phy_lock);
1662 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
1663 spin_unlock(&jme->phy_lock);
1668 jme_set_settings(struct net_device *netdev,
1669 struct ethtool_cmd *ecmd)
1671 struct jme_adapter *jme = netdev_priv(netdev);
1673 unsigned long flags;
1675 if(ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
1678 spin_lock_irqsave(&jme->phy_lock, flags);
1679 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
1680 spin_unlock_irqrestore(&jme->phy_lock, flags);
1686 jme_get_link(struct net_device *netdev)
1688 struct jme_adapter *jme = netdev_priv(netdev);
1689 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
1693 jme_get_rx_csum(struct net_device *netdev)
1695 struct jme_adapter *jme = netdev_priv(netdev);
1697 return jme->reg_rxmcs & RXMCS_CHECKSUM;
1701 jme_set_rx_csum(struct net_device *netdev, u32 on)
1703 struct jme_adapter *jme = netdev_priv(netdev);
1704 unsigned long flags;
1706 spin_lock_irqsave(&jme->rxmcs_lock, flags);
1708 jme->reg_rxmcs |= RXMCS_CHECKSUM;
1710 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
1711 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
1712 spin_unlock_irqrestore(&jme->rxmcs_lock, flags);
1718 jme_set_tx_csum(struct net_device *netdev, u32 on)
1721 netdev->features |= NETIF_F_HW_CSUM;
1723 netdev->features &= ~NETIF_F_HW_CSUM;
1729 jme_nway_reset(struct net_device *netdev)
1731 struct jme_adapter *jme = netdev_priv(netdev);
1732 jme_restart_an(jme);
1736 static const struct ethtool_ops jme_ethtool_ops = {
1737 .get_drvinfo = jme_get_drvinfo,
1738 .get_regs_len = jme_get_regs_len,
1739 .get_regs = jme_get_regs,
1740 .get_coalesce = jme_get_coalesce,
1741 .get_pauseparam = jme_get_pauseparam,
1742 .set_pauseparam = jme_set_pauseparam,
1743 .get_settings = jme_get_settings,
1744 .set_settings = jme_set_settings,
1745 .get_link = jme_get_link,
1746 .get_rx_csum = jme_get_rx_csum,
1747 .set_rx_csum = jme_set_rx_csum,
1748 .set_tx_csum = jme_set_tx_csum,
1749 .nway_reset = jme_nway_reset,
1753 jme_pci_dma64(struct pci_dev *pdev)
1755 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK))
1756 if(!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1759 if (!pci_set_dma_mask(pdev, DMA_40BIT_MASK))
1760 if(!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
1763 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
1764 if(!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
1770 static int __devinit
1771 jme_init_one(struct pci_dev *pdev,
1772 const struct pci_device_id *ent)
1774 int rc = 0, using_dac;
1775 struct net_device *netdev;
1776 struct jme_adapter *jme;
1779 * set up PCI device basics
1781 rc = pci_enable_device(pdev);
1783 printk(KERN_ERR PFX "Cannot enable PCI device.\n");
1787 using_dac = jme_pci_dma64(pdev);
1789 printk(KERN_ERR PFX "Cannot set PCI DMA Mask.\n");
1791 goto err_out_disable_pdev;
1794 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1795 printk(KERN_ERR PFX "No PCI resource region found.\n");
1797 goto err_out_disable_pdev;
1800 rc = pci_request_regions(pdev, DRV_NAME);
1802 printk(KERN_ERR PFX "Cannot obtain PCI resource region.\n");
1803 goto err_out_disable_pdev;
1806 pci_set_master(pdev);
1809 * alloc and init net device
1811 netdev = alloc_etherdev(sizeof(*jme));
1814 goto err_out_release_regions;
1816 netdev->open = jme_open;
1817 netdev->stop = jme_close;
1818 netdev->hard_start_xmit = jme_start_xmit;
1819 netdev->irq = pdev->irq;
1820 netdev->set_mac_address = jme_set_macaddr;
1821 netdev->set_multicast_list = jme_set_multi;
1822 netdev->change_mtu = jme_change_mtu;
1823 netdev->ethtool_ops = &jme_ethtool_ops;
1824 netdev->tx_timeout = jme_tx_timeout;
1825 netdev->watchdog_timeo = TX_TIMEOUT;
1826 NETDEV_GET_STATS(netdev, &jme_get_stats);
1827 netdev->features = NETIF_F_HW_CSUM;
1829 netdev->features |= NETIF_F_HIGHDMA;
1831 SET_NETDEV_DEV(netdev, &pdev->dev);
1832 pci_set_drvdata(pdev, netdev);
1837 jme = netdev_priv(netdev);
1841 jme->regs = ioremap(pci_resource_start(pdev, 0),
1842 pci_resource_len(pdev, 0));
1845 goto err_out_free_netdev;
1847 jme->shadow_regs = pci_alloc_consistent(pdev,
1848 sizeof(__u32) * SHADOW_REG_NR,
1849 &(jme->shadow_dma));
1850 if (!(jme->shadow_regs)) {
1855 spin_lock_init(&jme->tx_lock);
1856 spin_lock_init(&jme->phy_lock);
1857 spin_lock_init(&jme->macaddr_lock);
1858 spin_lock_init(&jme->rxmcs_lock);
1860 atomic_set(&jme->intr_sem, 1);
1861 atomic_set(&jme->link_changing, 1);
1862 atomic_set(&jme->rx_cleaning, 1);
1863 atomic_set(&jme->tx_cleaning, 1);
1865 tasklet_init(&jme->linkch_task,
1866 &jme_link_change_tasklet,
1867 (unsigned long) jme);
1868 tasklet_init(&jme->txclean_task,
1869 &jme_tx_clean_tasklet,
1870 (unsigned long) jme);
1871 tasklet_init(&jme->rxclean_task,
1872 &jme_rx_clean_tasklet,
1873 (unsigned long) jme);
1874 tasklet_init(&jme->rxempty_task,
1875 &jme_rx_empty_tasklet,
1876 (unsigned long) jme);
1877 jme->mii_if.dev = netdev;
1878 jme->mii_if.phy_id = 1;
1879 jme->mii_if.supports_gmii = 1;
1880 jme->mii_if.mdio_read = jme_mdio_read;
1881 jme->mii_if.mdio_write = jme_mdio_write;
1883 jme->dpi.cur = PCC_P1;
1885 jme->reg_ghc = GHC_DPX | GHC_SPEED_1000M;
1886 jme->reg_rxmcs = RXMCS_DEFAULT;
1889 * Get Max Read Req Size from PCI Config Space
1891 pci_read_config_byte(pdev, PCI_CONF_DCSR_MRRS, &jme->mrrs);
1894 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
1897 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
1900 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
1906 * Reset MAC processor and reload EEPROM for MAC Address
1909 jme_reset_phy_processor(jme);
1910 jme_reset_mac_processor(jme);
1911 rc = jme_reload_eeprom(jme);
1914 "Rload eeprom for reading MAC Address error.\n");
1915 goto err_out_free_shadow;
1917 jme_load_macaddr(netdev);
1921 * Tell stack that we are not ready to work until open()
1923 netif_carrier_off(netdev);
1924 netif_stop_queue(netdev);
1929 rc = register_netdev(netdev);
1931 printk(KERN_ERR PFX "Cannot register net device.\n");
1932 goto err_out_free_shadow;
1935 jprintk(netdev->name,
1936 "JMC250 gigabit eth %02x:%02x:%02x:%02x:%02x:%02x\n",
1937 netdev->dev_addr[0],
1938 netdev->dev_addr[1],
1939 netdev->dev_addr[2],
1940 netdev->dev_addr[3],
1941 netdev->dev_addr[4],
1942 netdev->dev_addr[5]);
1946 err_out_free_shadow:
1947 pci_free_consistent(pdev,
1948 sizeof(__u32) * SHADOW_REG_NR,
1953 err_out_free_netdev:
1954 pci_set_drvdata(pdev, NULL);
1955 free_netdev(netdev);
1956 err_out_release_regions:
1957 pci_release_regions(pdev);
1958 err_out_disable_pdev:
1959 pci_disable_device(pdev);
1964 static void __devexit
1965 jme_remove_one(struct pci_dev *pdev)
1967 struct net_device *netdev = pci_get_drvdata(pdev);
1968 struct jme_adapter *jme = netdev_priv(netdev);
1970 unregister_netdev(netdev);
1971 pci_free_consistent(pdev,
1972 sizeof(__u32) * SHADOW_REG_NR,
1976 pci_set_drvdata(pdev, NULL);
1977 free_netdev(netdev);
1978 pci_release_regions(pdev);
1979 pci_disable_device(pdev);
1983 static struct pci_device_id jme_pci_tbl[] = {
1984 { PCI_VDEVICE(JMICRON, 0x250) },
1988 static struct pci_driver jme_driver = {
1990 .id_table = jme_pci_tbl,
1991 .probe = jme_init_one,
1992 .remove = __devexit_p(jme_remove_one),
1995 .suspend = jme_suspend,
1996 .resume = jme_resume,
1997 #endif /* CONFIG_PM */
2002 jme_init_module(void)
2004 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
2005 "driver version %s\n", DRV_VERSION);
2006 return pci_register_driver(&jme_driver);
2010 jme_cleanup_module(void)
2012 pci_unregister_driver(&jme_driver);
2015 module_init(jme_init_module);
2016 module_exit(jme_cleanup_module);
2018 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
2019 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
2020 MODULE_LICENSE("GPL");
2021 MODULE_VERSION(DRV_VERSION);
2022 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);