jme.c

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  *
   7  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  */
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #include <linux/module.h>
  27 #include <linux/kernel.h>
  28 #include <linux/pci.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/etherdevice.h>
  31 #include <linux/ethtool.h>
  32 #include <linux/mii.h>
  33 #include <linux/crc32.h>
  34 #include <linux/delay.h>
  35 #include <linux/spinlock.h>
  36 #include <linux/in.h>
  37 #include <linux/ip.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/tcp.h>
  40 #include <linux/udp.h>
  41 #include <linux/if_vlan.h>
  42 #include <linux/slab.h>
  43 #include <net/ip6_checksum.h>
  44 #include "jme.h"
  45
  46 static int force_pseudohp = -1;
  47 static int no_pseudohp = -1;
  48 static int no_extplug = -1;
  49 module_param(force_pseudohp, int, 0);
  50 MODULE_PARM_DESC(force_pseudohp,
  51         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  52 module_param(no_pseudohp, int, 0);
  53 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  54 module_param(no_extplug, int, 0);
  55 MODULE_PARM_DESC(no_extplug,
  56         "Do not use external plug signal for pseudo hot-plug.");
  57
  58 static int
  59 jme_mdio_read(struct net_device *netdev, int phy, int reg)
  60 {
  61         struct jme_adapter *jme = netdev_priv(netdev);
  62         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  63
  64 read_again:
  65         jwrite32(jme, JME_SMI, SMI_OP_REQ |
  66                                 smi_phy_addr(phy) |
  67                                 smi_reg_addr(reg));
  68
  69         wmb();
  70         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  71                 udelay(20);
  72                 val = jread32(jme, JME_SMI);
  73                 if ((val & SMI_OP_REQ) == 0)
  74                         break;
  75         }
  76
  77         if (i == 0) {
  78                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
  79                 return 0;
  80         }
  81
  82         if (again--)
  83                 goto read_again;
  84
  85         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  86 }
  87
  88 static void
  89 jme_mdio_write(struct net_device *netdev,
  90                                 int phy, int reg, int val)
  91 {
  92         struct jme_adapter *jme = netdev_priv(netdev);
  93         int i;
  94
  95         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  96                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  97                 smi_phy_addr(phy) | smi_reg_addr(reg));
  98
  99         wmb();
 100         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
 101                 udelay(20);
 102                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
 103                         break;
 104         }
 105
 106         if (i == 0)
 107                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
 108 }
 109
 110 static inline void
 111 jme_reset_phy_processor(struct jme_adapter *jme)
 112 {
 113         u32 val;
 114
 115         jme_mdio_write(jme->dev,
 116                         jme->mii_if.phy_id,
 117                         MII_ADVERTISE, ADVERTISE_ALL |
 118                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 119
 120         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
 121                 jme_mdio_write(jme->dev,
 122                                 jme->mii_if.phy_id,
 123                                 MII_CTRL1000,
 124                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 125
 126         val = jme_mdio_read(jme->dev,
 127                                 jme->mii_if.phy_id,
 128                                 MII_BMCR);
 129
 130         jme_mdio_write(jme->dev,
 131                         jme->mii_if.phy_id,
 132                         MII_BMCR, val | BMCR_RESET);
 133 }
 134
 135 static void
 136 jme_setup_wakeup_frame(struct jme_adapter *jme,
 137                 u32 *mask, u32 crc, int fnr)
 138 {
 139         int i;
 140
 141         /*
 142          * Setup CRC pattern
 143          */
 144         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
 145         wmb();
 146         jwrite32(jme, JME_WFODP, crc);
 147         wmb();
 148
 149         /*
 150          * Setup Mask
 151          */
 152         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
 153                 jwrite32(jme, JME_WFOI,
 154                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
 155                                 (fnr & WFOI_FRAME_SEL));
 156                 wmb();
 157                 jwrite32(jme, JME_WFODP, mask[i]);
 158                 wmb();
 159         }
 160 }
 161
 162 static inline void
 163 jme_reset_mac_processor(struct jme_adapter *jme)
 164 {
 165         u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
 166         u32 crc = 0xCDCDCDCD;
 167         u32 gpreg0;
 168         int i;
 169
 170         jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
 171         udelay(2);
 172         jwrite32(jme, JME_GHC, jme->reg_ghc);
 173
 174         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
 175         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
 176         jwrite32(jme, JME_RXQDC, 0x00000000);
 177         jwrite32(jme, JME_RXNDA, 0x00000000);
 178         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
 179         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
 180         jwrite32(jme, JME_TXQDC, 0x00000000);
 181         jwrite32(jme, JME_TXNDA, 0x00000000);
 182
 183         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
 184         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
 185         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
 186                 jme_setup_wakeup_frame(jme, mask, crc, i);
 187         if (jme->fpgaver)
 188                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
 189         else
 190                 gpreg0 = GPREG0_DEFAULT;
 191         jwrite32(jme, JME_GPREG0, gpreg0);
 192         jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
 193 }
 194
 195 static inline void
 196 jme_reset_ghc_speed(struct jme_adapter *jme)
 197 {
 198         jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
 199         jwrite32(jme, JME_GHC, jme->reg_ghc);
 200 }
 201
 202 static inline void
 203 jme_clear_pm(struct jme_adapter *jme)
 204 {
 205         jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
 206         pci_set_power_state(jme->pdev, PCI_D0);
 207         pci_enable_wake(jme->pdev, PCI_D0, false);
 208 }
 209
 210 static int
 211 jme_reload_eeprom(struct jme_adapter *jme)
 212 {
 213         u32 val;
 214         int i;
 215
 216         val = jread32(jme, JME_SMBCSR);
 217
 218         if (val & SMBCSR_EEPROMD) {
 219                 val |= SMBCSR_CNACK;
 220                 jwrite32(jme, JME_SMBCSR, val);
 221                 val |= SMBCSR_RELOAD;
 222                 jwrite32(jme, JME_SMBCSR, val);
 223                 mdelay(12);
 224
 225                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
 226                         mdelay(1);
 227                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
 228                                 break;
 229                 }
 230
 231                 if (i == 0) {
 232                         pr_err("eeprom reload timeout\n");
 233                         return -EIO;
 234                 }
 235         }
 236
 237         return 0;
 238 }
 239
 240 static void
 241 jme_load_macaddr(struct net_device *netdev)
 242 {
 243         struct jme_adapter *jme = netdev_priv(netdev);
 244         unsigned char macaddr[6];
 245         u32 val;
 246
 247         spin_lock_bh(&jme->macaddr_lock);
 248         val = jread32(jme, JME_RXUMA_LO);
 249         macaddr[0] = (val >>  0) & 0xFF;
 250         macaddr[1] = (val >>  8) & 0xFF;
 251         macaddr[2] = (val >> 16) & 0xFF;
 252         macaddr[3] = (val >> 24) & 0xFF;
 253         val = jread32(jme, JME_RXUMA_HI);
 254         macaddr[4] = (val >>  0) & 0xFF;
 255         macaddr[5] = (val >>  8) & 0xFF;
 256         memcpy(netdev->dev_addr, macaddr, 6);
 257         spin_unlock_bh(&jme->macaddr_lock);
 258 }
 259
 260 static inline void
 261 jme_set_rx_pcc(struct jme_adapter *jme, int p)
 262 {
 263         switch (p) {
 264         case PCC_OFF:
 265                 jwrite32(jme, JME_PCCRX0,
 266                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 267                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 268                 break;
 269         case PCC_P1:
 270                 jwrite32(jme, JME_PCCRX0,
 271                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 272                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 273                 break;
 274         case PCC_P2:
 275                 jwrite32(jme, JME_PCCRX0,
 276                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 277                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 278                 break;
 279         case PCC_P3:
 280                 jwrite32(jme, JME_PCCRX0,
 281                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 282                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 283                 break;
 284         default:
 285                 break;
 286         }
 287         wmb();
 288
 289         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
 290                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
 291 }
 292
 293 static void
 294 jme_start_irq(struct jme_adapter *jme)
 295 {
 296         register struct dynpcc_info *dpi = &(jme->dpi);
 297
 298         jme_set_rx_pcc(jme, PCC_P1);
 299         dpi->cur                = PCC_P1;
 300         dpi->attempt            = PCC_P1;
 301         dpi->cnt                = 0;
 302
 303         jwrite32(jme, JME_PCCTX,
 304                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
 305                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
 306                         PCCTXQ0_EN
 307                 );
 308
 309         /*
 310          * Enable Interrupts
 311          */
 312         jwrite32(jme, JME_IENS, INTR_ENABLE);
 313 }
 314
 315 static inline void
 316 jme_stop_irq(struct jme_adapter *jme)
 317 {
 318         /*
 319          * Disable Interrupts
 320          */
 321         jwrite32f(jme, JME_IENC, INTR_ENABLE);
 322 }
 323
 324 static u32
 325 jme_linkstat_from_phy(struct jme_adapter *jme)
 326 {
 327         u32 phylink, bmsr;
 328
 329         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
 330         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
 331         if (bmsr & BMSR_ANCOMP)
 332                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
 333
 334         return phylink;
 335 }
 336
 337 static inline void
 338 jme_set_phyfifoa(struct jme_adapter *jme)
 339 {
 340         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 341 }
 342
 343 static inline void
 344 jme_set_phyfifob(struct jme_adapter *jme)
 345 {
 346         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 347 }
 348
 349 static int
 350 jme_check_link(struct net_device *netdev, int testonly)
 351 {
 352         struct jme_adapter *jme = netdev_priv(netdev);
 353         u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
 354         char linkmsg[64];
 355         int rc = 0;
 356
 357         linkmsg[0] = '\0';
 358
 359         if (jme->fpgaver)
 360                 phylink = jme_linkstat_from_phy(jme);
 361         else
 362                 phylink = jread32(jme, JME_PHY_LINK);
 363
 364         if (phylink & PHY_LINK_UP) {
 365                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
 366                         /*
 367                          * If we did not enable AN
 368                          * Speed/Duplex Info should be obtained from SMI
 369                          */
 370                         phylink = PHY_LINK_UP;
 371
 372                         bmcr = jme_mdio_read(jme->dev,
 373                                                 jme->mii_if.phy_id,
 374                                                 MII_BMCR);
 375
 376                         phylink |= ((bmcr & BMCR_SPEED1000) &&
 377                                         (bmcr & BMCR_SPEED100) == 0) ?
 378                                         PHY_LINK_SPEED_1000M :
 379                                         (bmcr & BMCR_SPEED100) ?
 380                                         PHY_LINK_SPEED_100M :
 381                                         PHY_LINK_SPEED_10M;
 382
 383                         phylink |= (bmcr & BMCR_FULLDPLX) ?
 384                                          PHY_LINK_DUPLEX : 0;
 385
 386                         strcat(linkmsg, "Forced: ");
 387                 } else {
 388                         /*
 389                          * Keep polling for speed/duplex resolve complete
 390                          */
 391                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
 392                                 --cnt) {
 393
 394                                 udelay(1);
 395
 396                                 if (jme->fpgaver)
 397                                         phylink = jme_linkstat_from_phy(jme);
 398                                 else
 399                                         phylink = jread32(jme, JME_PHY_LINK);
 400                         }
 401                         if (!cnt)
 402                                 pr_err("Waiting speed resolve timeout\n");
 403
 404                         strcat(linkmsg, "ANed: ");
 405                 }
 406
 407                 if (jme->phylink == phylink) {
 408                         rc = 1;
 409                         goto out;
 410                 }
 411                 if (testonly)
 412                         goto out;
 413
 414                 jme->phylink = phylink;
 415
 416                 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
 417                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
 418                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
 419                 switch (phylink & PHY_LINK_SPEED_MASK) {
 420                 case PHY_LINK_SPEED_10M:
 421                         ghc |= GHC_SPEED_10M |
 422                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 423                         strcat(linkmsg, "10 Mbps, ");
 424                         break;
 425                 case PHY_LINK_SPEED_100M:
 426                         ghc |= GHC_SPEED_100M |
 427                                 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 428                         strcat(linkmsg, "100 Mbps, ");
 429                         break;
 430                 case PHY_LINK_SPEED_1000M:
 431                         ghc |= GHC_SPEED_1000M |
 432                                 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 433                         strcat(linkmsg, "1000 Mbps, ");
 434                         break;
 435                 default:
 436                         break;
 437                 }
 438
 439                 if (phylink & PHY_LINK_DUPLEX) {
 440                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
 441                         ghc |= GHC_DPX;
 442                 } else {
 443                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
 444                                                 TXMCS_BACKOFF |
 445                                                 TXMCS_CARRIERSENSE |
 446                                                 TXMCS_COLLISION);
 447                         jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
 448                                 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
 449                                 TXTRHD_TXREN |
 450                                 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
 451                 }
 452
 453                 gpreg1 = GPREG1_DEFAULT;
 454                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 455                         if (!(phylink & PHY_LINK_DUPLEX))
 456                                 gpreg1 |= GPREG1_HALFMODEPATCH;
 457                         switch (phylink & PHY_LINK_SPEED_MASK) {
 458                         case PHY_LINK_SPEED_10M:
 459                                 jme_set_phyfifoa(jme);
 460                                 gpreg1 |= GPREG1_RSSPATCH;
 461                                 break;
 462                         case PHY_LINK_SPEED_100M:
 463                                 jme_set_phyfifob(jme);
 464                                 gpreg1 |= GPREG1_RSSPATCH;
 465                                 break;
 466                         case PHY_LINK_SPEED_1000M:
 467                                 jme_set_phyfifoa(jme);
 468                                 break;
 469                         default:
 470                                 break;
 471                         }
 472                 }
 473
 474                 jwrite32(jme, JME_GPREG1, gpreg1);
 475                 jwrite32(jme, JME_GHC, ghc);
 476                 jme->reg_ghc = ghc;
 477
 478                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
 479                                         "Full-Duplex, " :
 480                                         "Half-Duplex, ");
 481                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
 482                                         "MDI-X" :
 483                                         "MDI");
 484                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
 485                 netif_carrier_on(netdev);
 486         } else {
 487                 if (testonly)
 488                         goto out;
 489
 490                 netif_info(jme, link, jme->dev, "Link is down\n");
 491                 jme->phylink = 0;
 492                 netif_carrier_off(netdev);
 493         }
 494
 495 out:
 496         return rc;
 497 }
 498
 499 static int
 500 jme_setup_tx_resources(struct jme_adapter *jme)
 501 {
 502         struct jme_ring *txring = &(jme->txring[0]);
 503
 504         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 505                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 506                                    &(txring->dmaalloc),
 507                                    GFP_ATOMIC);
 508
 509         if (!txring->alloc)
 510                 goto err_set_null;
 511
 512         /*
 513          * 16 Bytes align
 514          */
 515         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
 516                                                 RING_DESC_ALIGN);
 517         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
 518         txring->next_to_use     = 0;
 519         atomic_set(&txring->next_to_clean, 0);
 520         atomic_set(&txring->nr_free, jme->tx_ring_size);
 521
 522         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 523                                         jme->tx_ring_size, GFP_ATOMIC);
 524         if (unlikely(!(txring->bufinf)))
 525                 goto err_free_txring;
 526
 527         /*
 528          * Initialize Transmit Descriptors
 529          */
 530         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
 531         memset(txring->bufinf, 0,
 532                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
 533
 534         return 0;
 535
 536 err_free_txring:
 537         dma_free_coherent(&(jme->pdev->dev),
 538                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 539                           txring->alloc,
 540                           txring->dmaalloc);
 541
 542 err_set_null:
 543         txring->desc = NULL;
 544         txring->dmaalloc = 0;
 545         txring->dma = 0;
 546         txring->bufinf = NULL;
 547
 548         return -ENOMEM;
 549 }
 550
 551 static void
 552 jme_free_tx_resources(struct jme_adapter *jme)
 553 {
 554         int i;
 555         struct jme_ring *txring = &(jme->txring[0]);
 556         struct jme_buffer_info *txbi;
 557
 558         if (txring->alloc) {
 559                 if (txring->bufinf) {
 560                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
 561                                 txbi = txring->bufinf + i;
 562                                 if (txbi->skb) {
 563                                         dev_kfree_skb(txbi->skb);
 564                                         txbi->skb = NULL;
 565                                 }
 566                                 txbi->mapping           = 0;
 567                                 txbi->len               = 0;
 568                                 txbi->nr_desc           = 0;
 569                                 txbi->start_xmit        = 0;
 570                         }
 571                         kfree(txring->bufinf);
 572                 }
 573
 574                 dma_free_coherent(&(jme->pdev->dev),
 575                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 576                                   txring->alloc,
 577                                   txring->dmaalloc);
 578
 579                 txring->alloc           = NULL;
 580                 txring->desc            = NULL;
 581                 txring->dmaalloc        = 0;
 582                 txring->dma             = 0;
 583                 txring->bufinf          = NULL;
 584         }
 585         txring->next_to_use     = 0;
 586         atomic_set(&txring->next_to_clean, 0);
 587         atomic_set(&txring->nr_free, 0);
 588 }
 589
 590 static inline void
 591 jme_enable_tx_engine(struct jme_adapter *jme)
 592 {
 593         /*
 594          * Select Queue 0
 595          */
 596         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
 597         wmb();
 598
 599         /*
 600          * Setup TX Queue 0 DMA Bass Address
 601          */
 602         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 603         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
 604         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 605
 606         /*
 607          * Setup TX Descptor Count
 608          */
 609         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
 610
 611         /*
 612          * Enable TX Engine
 613          */
 614         wmb();
 615         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 616                                 TXCS_SELECT_QUEUE0 |
 617                                 TXCS_ENABLE);
 618
 619 }
 620
 621 static inline void
 622 jme_restart_tx_engine(struct jme_adapter *jme)
 623 {
 624         /*
 625          * Restart TX Engine
 626          */
 627         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 628                                 TXCS_SELECT_QUEUE0 |
 629                                 TXCS_ENABLE);
 630 }
 631
 632 static inline void
 633 jme_disable_tx_engine(struct jme_adapter *jme)
 634 {
 635         int i;
 636         u32 val;
 637
 638         /*
 639          * Disable TX Engine
 640          */
 641         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
 642         wmb();
 643
 644         val = jread32(jme, JME_TXCS);
 645         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
 646                 mdelay(1);
 647                 val = jread32(jme, JME_TXCS);
 648                 rmb();
 649         }
 650
 651         if (!i)
 652                 pr_err("Disable TX engine timeout\n");
 653 }
 654
 655 static void
 656 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
 657 {
 658         struct jme_ring *rxring = &(jme->rxring[0]);
 659         register struct rxdesc *rxdesc = rxring->desc;
 660         struct jme_buffer_info *rxbi = rxring->bufinf;
 661         rxdesc += i;
 662         rxbi += i;
 663
 664         rxdesc->dw[0] = 0;
 665         rxdesc->dw[1] = 0;
 666         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
 667         rxdesc->desc1.bufaddrl  = cpu_to_le32(
 668                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
 669         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
 670         if (jme->dev->features & NETIF_F_HIGHDMA)
 671                 rxdesc->desc1.flags = RXFLAG_64BIT;
 672         wmb();
 673         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
 674 }
 675
 676 static int
 677 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
 678 {
 679         struct jme_ring *rxring = &(jme->rxring[0]);
 680         struct jme_buffer_info *rxbi = rxring->bufinf + i;
 681         struct sk_buff *skb;
 682
 683         skb = netdev_alloc_skb(jme->dev,
 684                 jme->dev->mtu + RX_EXTRA_LEN);
 685         if (unlikely(!skb))
 686                 return -ENOMEM;
 687
 688         rxbi->skb = skb;
 689         rxbi->len = skb_tailroom(skb);
 690         rxbi->mapping = pci_map_page(jme->pdev,
 691                                         virt_to_page(skb->data),
 692                                         offset_in_page(skb->data),
 693                                         rxbi->len,
 694                                         PCI_DMA_FROMDEVICE);
 695
 696         return 0;
 697 }
 698
 699 static void
 700 jme_free_rx_buf(struct jme_adapter *jme, int i)
 701 {
 702         struct jme_ring *rxring = &(jme->rxring[0]);
 703         struct jme_buffer_info *rxbi = rxring->bufinf;
 704         rxbi += i;
 705
 706         if (rxbi->skb) {
 707                 pci_unmap_page(jme->pdev,
 708                                  rxbi->mapping,
 709                                  rxbi->len,
 710                                  PCI_DMA_FROMDEVICE);
 711                 dev_kfree_skb(rxbi->skb);
 712                 rxbi->skb = NULL;
 713                 rxbi->mapping = 0;
 714                 rxbi->len = 0;
 715         }
 716 }
 717
 718 static void
 719 jme_free_rx_resources(struct jme_adapter *jme)
 720 {
 721         int i;
 722         struct jme_ring *rxring = &(jme->rxring[0]);
 723
 724         if (rxring->alloc) {
 725                 if (rxring->bufinf) {
 726                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
 727                                 jme_free_rx_buf(jme, i);
 728                         kfree(rxring->bufinf);
 729                 }
 730
 731                 dma_free_coherent(&(jme->pdev->dev),
 732                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 733                                   rxring->alloc,
 734                                   rxring->dmaalloc);
 735                 rxring->alloc    = NULL;
 736                 rxring->desc     = NULL;
 737                 rxring->dmaalloc = 0;
 738                 rxring->dma      = 0;
 739                 rxring->bufinf   = NULL;
 740         }
 741         rxring->next_to_use   = 0;
 742         atomic_set(&rxring->next_to_clean, 0);
 743 }
 744
 745 static int
 746 jme_setup_rx_resources(struct jme_adapter *jme)
 747 {
 748         int i;
 749         struct jme_ring *rxring = &(jme->rxring[0]);
 750
 751         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 752                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 753                                    &(rxring->dmaalloc),
 754                                    GFP_ATOMIC);
 755         if (!rxring->alloc)
 756                 goto err_set_null;
 757
 758         /*
 759          * 16 Bytes align
 760          */
 761         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
 762                                                 RING_DESC_ALIGN);
 763         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
 764         rxring->next_to_use     = 0;
 765         atomic_set(&rxring->next_to_clean, 0);
 766
 767         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 768                                         jme->rx_ring_size, GFP_ATOMIC);
 769         if (unlikely(!(rxring->bufinf)))
 770                 goto err_free_rxring;
 771
 772         /*
 773          * Initiallize Receive Descriptors
 774          */
 775         memset(rxring->bufinf, 0,
 776                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
 777         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
 778                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
 779                         jme_free_rx_resources(jme);
 780                         return -ENOMEM;
 781                 }
 782
 783                 jme_set_clean_rxdesc(jme, i);
 784         }
 785
 786         return 0;
 787
 788 err_free_rxring:
 789         dma_free_coherent(&(jme->pdev->dev),
 790                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 791                           rxring->alloc,
 792                           rxring->dmaalloc);
 793 err_set_null:
 794         rxring->desc = NULL;
 795         rxring->dmaalloc = 0;
 796         rxring->dma = 0;
 797         rxring->bufinf = NULL;
 798
 799         return -ENOMEM;
 800 }
 801
 802 static inline void
 803 jme_enable_rx_engine(struct jme_adapter *jme)
 804 {
 805         /*
 806          * Select Queue 0
 807          */
 808         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 809                                 RXCS_QUEUESEL_Q0);
 810         wmb();
 811
 812         /*
 813          * Setup RX DMA Bass Address
 814          */
 815         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 816         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
 817         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 818
 819         /*
 820          * Setup RX Descriptor Count
 821          */
 822         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
 823
 824         /*
 825          * Setup Unicast Filter
 826          */
 827         jme_set_multi(jme->dev);
 828
 829         /*
 830          * Enable RX Engine
 831          */
 832         wmb();
 833         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 834                                 RXCS_QUEUESEL_Q0 |
 835                                 RXCS_ENABLE |
 836                                 RXCS_QST);
 837 }
 838
 839 static inline void
 840 jme_restart_rx_engine(struct jme_adapter *jme)
 841 {
 842         /*
 843          * Start RX Engine
 844          */
 845         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 846                                 RXCS_QUEUESEL_Q0 |
 847                                 RXCS_ENABLE |
 848                                 RXCS_QST);
 849 }
 850
 851 static inline void
 852 jme_disable_rx_engine(struct jme_adapter *jme)
 853 {
 854         int i;
 855         u32 val;
 856
 857         /*
 858          * Disable RX Engine
 859          */
 860         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
 861         wmb();
 862
 863         val = jread32(jme, JME_RXCS);
 864         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
 865                 mdelay(1);
 866                 val = jread32(jme, JME_RXCS);
 867                 rmb();
 868         }
 869
 870         if (!i)
 871                 pr_err("Disable RX engine timeout\n");
 872
 873 }
 874
 875 static int
 876 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
 877 {
 878         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
 879                 return false;
 880
 881         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
 882                         == RXWBFLAG_TCPON)) {
 883                 if (flags & RXWBFLAG_IPV4)
 884                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
 885                 return false;
 886         }
 887
 888         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
 889                         == RXWBFLAG_UDPON)) {
 890                 if (flags & RXWBFLAG_IPV4)
 891                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
 892                 return false;
 893         }
 894
 895         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
 896                         == RXWBFLAG_IPV4)) {
 897                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
 898                 return false;
 899         }
 900
 901         return true;
 902 }
 903
 904 static void
 905 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
 906 {
 907         struct jme_ring *rxring = &(jme->rxring[0]);
 908         struct rxdesc *rxdesc = rxring->desc;
 909         struct jme_buffer_info *rxbi = rxring->bufinf;
 910         struct sk_buff *skb;
 911         int framesize;
 912
 913         rxdesc += idx;
 914         rxbi += idx;
 915
 916         skb = rxbi->skb;
 917         pci_dma_sync_single_for_cpu(jme->pdev,
 918                                         rxbi->mapping,
 919                                         rxbi->len,
 920                                         PCI_DMA_FROMDEVICE);
 921
 922         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
 923                 pci_dma_sync_single_for_device(jme->pdev,
 924                                                 rxbi->mapping,
 925                                                 rxbi->len,
 926                                                 PCI_DMA_FROMDEVICE);
 927
 928                 ++(NET_STAT(jme).rx_dropped);
 929         } else {
 930                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
 931                                 - RX_PREPAD_SIZE;
 932
 933                 skb_reserve(skb, RX_PREPAD_SIZE);
 934                 skb_put(skb, framesize);
 935                 skb->protocol = eth_type_trans(skb, jme->dev);
 936
 937                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
 938                         skb->ip_summed = CHECKSUM_UNNECESSARY;
 939                 else
 940                         skb_checksum_none_assert(skb);
 941
 942                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
 943                         if (jme->vlgrp) {
 944                                 jme->jme_vlan_rx(skb, jme->vlgrp,
 945                                         le16_to_cpu(rxdesc->descwb.vlan));
 946                                 NET_STAT(jme).rx_bytes += 4;
 947                         } else {
 948                                 dev_kfree_skb(skb);
 949                         }
 950                 } else {
 951                         jme->jme_rx(skb);
 952                 }
 953
 954                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
 955                     cpu_to_le16(RXWBFLAG_DEST_MUL))
 956                         ++(NET_STAT(jme).multicast);
 957
 958                 NET_STAT(jme).rx_bytes += framesize;
 959                 ++(NET_STAT(jme).rx_packets);
 960         }
 961
 962         jme_set_clean_rxdesc(jme, idx);
 963
 964 }
 965
 966 static int
 967 jme_process_receive(struct jme_adapter *jme, int limit)
 968 {
 969         struct jme_ring *rxring = &(jme->rxring[0]);
 970         struct rxdesc *rxdesc = rxring->desc;
 971         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
 972
 973         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
 974                 goto out_inc;
 975
 976         if (unlikely(atomic_read(&jme->link_changing) != 1))
 977                 goto out_inc;
 978
 979         if (unlikely(!netif_carrier_ok(jme->dev)))
 980                 goto out_inc;
 981
 982         i = atomic_read(&rxring->next_to_clean);
 983         while (limit > 0) {
 984                 rxdesc = rxring->desc;
 985                 rxdesc += i;
 986
 987                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
 988                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
 989                         goto out;
 990                 --limit;
 991
 992                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
 993
 994                 if (unlikely(desccnt > 1 ||
 995                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
 996
 997                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
 998                                 ++(NET_STAT(jme).rx_crc_errors);
 999                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1000                                 ++(NET_STAT(jme).rx_fifo_errors);
1001                         else
1002                                 ++(NET_STAT(jme).rx_errors);
1003
1004                         if (desccnt > 1)
1005                                 limit -= desccnt - 1;
1006
1007                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1008                                 jme_set_clean_rxdesc(jme, j);
1009                                 j = (j + 1) & (mask);
1010                         }
1011
1012                 } else {
1013                         jme_alloc_and_feed_skb(jme, i);
1014                 }
1015
1016                 i = (i + desccnt) & (mask);
1017         }
1018
1019 out:
1020         atomic_set(&rxring->next_to_clean, i);
1021
1022 out_inc:
1023         atomic_inc(&jme->rx_cleaning);
1024
1025         return limit > 0 ? limit : 0;
1026
1027 }
1028
1029 static void
1030 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1031 {
1032         if (likely(atmp == dpi->cur)) {
1033                 dpi->cnt = 0;
1034                 return;
1035         }
1036
1037         if (dpi->attempt == atmp) {
1038                 ++(dpi->cnt);
1039         } else {
1040                 dpi->attempt = atmp;
1041                 dpi->cnt = 0;
1042         }
1043
1044 }
1045
1046 static void
1047 jme_dynamic_pcc(struct jme_adapter *jme)
1048 {
1049         register struct dynpcc_info *dpi = &(jme->dpi);
1050
1051         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1052                 jme_attempt_pcc(dpi, PCC_P3);
1053         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1054                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1055                 jme_attempt_pcc(dpi, PCC_P2);
1056         else
1057                 jme_attempt_pcc(dpi, PCC_P1);
1058
1059         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1060                 if (dpi->attempt < dpi->cur)
1061                         tasklet_schedule(&jme->rxclean_task);
1062                 jme_set_rx_pcc(jme, dpi->attempt);
1063                 dpi->cur = dpi->attempt;
1064                 dpi->cnt = 0;
1065         }
1066 }
1067
1068 static void
1069 jme_start_pcc_timer(struct jme_adapter *jme)
1070 {
1071         struct dynpcc_info *dpi = &(jme->dpi);
1072         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1073         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1074         dpi->intr_cnt           = 0;
1075         jwrite32(jme, JME_TMCSR,
1076                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1077 }
1078
1079 static inline void
1080 jme_stop_pcc_timer(struct jme_adapter *jme)
1081 {
1082         jwrite32(jme, JME_TMCSR, 0);
1083 }
1084
1085 static void
1086 jme_shutdown_nic(struct jme_adapter *jme)
1087 {
1088         u32 phylink;
1089
1090         phylink = jme_linkstat_from_phy(jme);
1091
1092         if (!(phylink & PHY_LINK_UP)) {
1093                 /*
1094                  * Disable all interrupt before issue timer
1095                  */
1096                 jme_stop_irq(jme);
1097                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1098         }
1099 }
1100
1101 static void
1102 jme_pcc_tasklet(unsigned long arg)
1103 {
1104         struct jme_adapter *jme = (struct jme_adapter *)arg;
1105         struct net_device *netdev = jme->dev;
1106
1107         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1108                 jme_shutdown_nic(jme);
1109                 return;
1110         }
1111
1112         if (unlikely(!netif_carrier_ok(netdev) ||
1113                 (atomic_read(&jme->link_changing) != 1)
1114         )) {
1115                 jme_stop_pcc_timer(jme);
1116                 return;
1117         }
1118
1119         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1120                 jme_dynamic_pcc(jme);
1121
1122         jme_start_pcc_timer(jme);
1123 }
1124
1125 static inline void
1126 jme_polling_mode(struct jme_adapter *jme)
1127 {
1128         jme_set_rx_pcc(jme, PCC_OFF);
1129 }
1130
1131 static inline void
1132 jme_interrupt_mode(struct jme_adapter *jme)
1133 {
1134         jme_set_rx_pcc(jme, PCC_P1);
1135 }
1136
1137 static inline int
1138 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1139 {
1140         u32 apmc;
1141         apmc = jread32(jme, JME_APMC);
1142         return apmc & JME_APMC_PSEUDO_HP_EN;
1143 }
1144
1145 static void
1146 jme_start_shutdown_timer(struct jme_adapter *jme)
1147 {
1148         u32 apmc;
1149
1150         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1151         apmc &= ~JME_APMC_EPIEN_CTRL;
1152         if (!no_extplug) {
1153                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1154                 wmb();
1155         }
1156         jwrite32f(jme, JME_APMC, apmc);
1157
1158         jwrite32f(jme, JME_TIMER2, 0);
1159         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1160         jwrite32(jme, JME_TMCSR,
1161                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1162 }
1163
1164 static void
1165 jme_stop_shutdown_timer(struct jme_adapter *jme)
1166 {
1167         u32 apmc;
1168
1169         jwrite32f(jme, JME_TMCSR, 0);
1170         jwrite32f(jme, JME_TIMER2, 0);
1171         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1172
1173         apmc = jread32(jme, JME_APMC);
1174         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1175         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1176         wmb();
1177         jwrite32f(jme, JME_APMC, apmc);
1178 }
1179
1180 static void
1181 jme_link_change_tasklet(unsigned long arg)
1182 {
1183         struct jme_adapter *jme = (struct jme_adapter *)arg;
1184         struct net_device *netdev = jme->dev;
1185         int rc;
1186
1187         while (!atomic_dec_and_test(&jme->link_changing)) {
1188                 atomic_inc(&jme->link_changing);
1189                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1190                 while (atomic_read(&jme->link_changing) != 1)
1191                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1192         }
1193
1194         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1195                 goto out;
1196
1197         jme->old_mtu = netdev->mtu;
1198         netif_stop_queue(netdev);
1199         if (jme_pseudo_hotplug_enabled(jme))
1200                 jme_stop_shutdown_timer(jme);
1201
1202         jme_stop_pcc_timer(jme);
1203         tasklet_disable(&jme->txclean_task);
1204         tasklet_disable(&jme->rxclean_task);
1205         tasklet_disable(&jme->rxempty_task);
1206
1207         if (netif_carrier_ok(netdev)) {
1208                 jme_reset_ghc_speed(jme);
1209                 jme_disable_rx_engine(jme);
1210                 jme_disable_tx_engine(jme);
1211                 jme_reset_mac_processor(jme);
1212                 jme_free_rx_resources(jme);
1213                 jme_free_tx_resources(jme);
1214
1215                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1216                         jme_polling_mode(jme);
1217
1218                 netif_carrier_off(netdev);
1219         }
1220
1221         jme_check_link(netdev, 0);
1222         if (netif_carrier_ok(netdev)) {
1223                 rc = jme_setup_rx_resources(jme);
1224                 if (rc) {
1225                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1226                         goto out_enable_tasklet;
1227                 }
1228
1229                 rc = jme_setup_tx_resources(jme);
1230                 if (rc) {
1231                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1232                         goto err_out_free_rx_resources;
1233                 }
1234
1235                 jme_enable_rx_engine(jme);
1236                 jme_enable_tx_engine(jme);
1237
1238                 netif_start_queue(netdev);
1239
1240                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1241                         jme_interrupt_mode(jme);
1242
1243                 jme_start_pcc_timer(jme);
1244         } else if (jme_pseudo_hotplug_enabled(jme)) {
1245                 jme_start_shutdown_timer(jme);
1246         }
1247
1248         goto out_enable_tasklet;
1249
1250 err_out_free_rx_resources:
1251         jme_free_rx_resources(jme);
1252 out_enable_tasklet:
1253         tasklet_enable(&jme->txclean_task);
1254         tasklet_hi_enable(&jme->rxclean_task);
1255         tasklet_hi_enable(&jme->rxempty_task);
1256 out:
1257         atomic_inc(&jme->link_changing);
1258 }
1259
1260 static void
1261 jme_rx_clean_tasklet(unsigned long arg)
1262 {
1263         struct jme_adapter *jme = (struct jme_adapter *)arg;
1264         struct dynpcc_info *dpi = &(jme->dpi);
1265
1266         jme_process_receive(jme, jme->rx_ring_size);
1267         ++(dpi->intr_cnt);
1268
1269 }
1270
1271 static int
1272 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1273 {
1274         struct jme_adapter *jme = jme_napi_priv(holder);
1275         int rest;
1276
1277         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1278
1279         while (atomic_read(&jme->rx_empty) > 0) {
1280                 atomic_dec(&jme->rx_empty);
1281                 ++(NET_STAT(jme).rx_dropped);
1282                 jme_restart_rx_engine(jme);
1283         }
1284         atomic_inc(&jme->rx_empty);
1285
1286         if (rest) {
1287                 JME_RX_COMPLETE(netdev, holder);
1288                 jme_interrupt_mode(jme);
1289         }
1290
1291         JME_NAPI_WEIGHT_SET(budget, rest);
1292         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1293 }
1294
1295 static void
1296 jme_rx_empty_tasklet(unsigned long arg)
1297 {
1298         struct jme_adapter *jme = (struct jme_adapter *)arg;
1299
1300         if (unlikely(atomic_read(&jme->link_changing) != 1))
1301                 return;
1302
1303         if (unlikely(!netif_carrier_ok(jme->dev)))
1304                 return;
1305
1306         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1307
1308         jme_rx_clean_tasklet(arg);
1309
1310         while (atomic_read(&jme->rx_empty) > 0) {
1311                 atomic_dec(&jme->rx_empty);
1312                 ++(NET_STAT(jme).rx_dropped);
1313                 jme_restart_rx_engine(jme);
1314         }
1315         atomic_inc(&jme->rx_empty);
1316 }
1317
1318 static void
1319 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1320 {
1321         struct jme_ring *txring = &(jme->txring[0]);
1322
1323         smp_wmb();
1324         if (unlikely(netif_queue_stopped(jme->dev) &&
1325         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1326                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1327                 netif_wake_queue(jme->dev);
1328         }
1329
1330 }
1331
1332 static void
1333 jme_tx_clean_tasklet(unsigned long arg)
1334 {
1335         struct jme_adapter *jme = (struct jme_adapter *)arg;
1336         struct jme_ring *txring = &(jme->txring[0]);
1337         struct txdesc *txdesc = txring->desc;
1338         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1339         int i, j, cnt = 0, max, err, mask;
1340
1341         tx_dbg(jme, "Into txclean\n");
1342
1343         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1344                 goto out;
1345
1346         if (unlikely(atomic_read(&jme->link_changing) != 1))
1347                 goto out;
1348
1349         if (unlikely(!netif_carrier_ok(jme->dev)))
1350                 goto out;
1351
1352         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1353         mask = jme->tx_ring_mask;
1354
1355         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1356
1357                 ctxbi = txbi + i;
1358
1359                 if (likely(ctxbi->skb &&
1360                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1361
1362                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1363                                i, ctxbi->nr_desc, jiffies);
1364
1365                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1366
1367                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1368                                 ttxbi = txbi + ((i + j) & (mask));
1369                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1370
1371                                 pci_unmap_page(jme->pdev,
1372                                                  ttxbi->mapping,
1373                                                  ttxbi->len,
1374                                                  PCI_DMA_TODEVICE);
1375
1376                                 ttxbi->mapping = 0;
1377                                 ttxbi->len = 0;
1378                         }
1379
1380                         dev_kfree_skb(ctxbi->skb);
1381
1382                         cnt += ctxbi->nr_desc;
1383
1384                         if (unlikely(err)) {
1385                                 ++(NET_STAT(jme).tx_carrier_errors);
1386                         } else {
1387                                 ++(NET_STAT(jme).tx_packets);
1388                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1389                         }
1390
1391                         ctxbi->skb = NULL;
1392                         ctxbi->len = 0;
1393                         ctxbi->start_xmit = 0;
1394
1395                 } else {
1396                         break;
1397                 }
1398
1399                 i = (i + ctxbi->nr_desc) & mask;
1400
1401                 ctxbi->nr_desc = 0;
1402         }
1403
1404         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1405         atomic_set(&txring->next_to_clean, i);
1406         atomic_add(cnt, &txring->nr_free);
1407
1408         jme_wake_queue_if_stopped(jme);
1409
1410 out:
1411         atomic_inc(&jme->tx_cleaning);
1412 }
1413
1414 static void
1415 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1416 {
1417         /*
1418          * Disable interrupt
1419          */
1420         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1421
1422         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1423                 /*
1424                  * Link change event is critical
1425                  * all other events are ignored
1426                  */
1427                 jwrite32(jme, JME_IEVE, intrstat);
1428                 tasklet_schedule(&jme->linkch_task);
1429                 goto out_reenable;
1430         }
1431
1432         if (intrstat & INTR_TMINTR) {
1433                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1434                 tasklet_schedule(&jme->pcc_task);
1435         }
1436
1437         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1438                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1439                 tasklet_schedule(&jme->txclean_task);
1440         }
1441
1442         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1443                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1444                                                      INTR_PCCRX0 |
1445                                                      INTR_RX0EMP)) |
1446                                         INTR_RX0);
1447         }
1448
1449         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1450                 if (intrstat & INTR_RX0EMP)
1451                         atomic_inc(&jme->rx_empty);
1452
1453                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1455                                 jme_polling_mode(jme);
1456                                 JME_RX_SCHEDULE(jme);
1457                         }
1458                 }
1459         } else {
1460                 if (intrstat & INTR_RX0EMP) {
1461                         atomic_inc(&jme->rx_empty);
1462                         tasklet_hi_schedule(&jme->rxempty_task);
1463                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1464                         tasklet_hi_schedule(&jme->rxclean_task);
1465                 }
1466         }
1467
1468 out_reenable:
1469         /*
1470          * Re-enable interrupt
1471          */
1472         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1473 }
1474
1475 static irqreturn_t
1476 jme_intr(int irq, void *dev_id)
1477 {
1478         struct net_device *netdev = dev_id;
1479         struct jme_adapter *jme = netdev_priv(netdev);
1480         u32 intrstat;
1481
1482         intrstat = jread32(jme, JME_IEVE);
1483
1484         /*
1485          * Check if it's really an interrupt for us
1486          */
1487         if (unlikely((intrstat & INTR_ENABLE) == 0))
1488                 return IRQ_NONE;
1489
1490         /*
1491          * Check if the device still exist
1492          */
1493         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1494                 return IRQ_NONE;
1495
1496         jme_intr_msi(jme, intrstat);
1497
1498         return IRQ_HANDLED;
1499 }
1500
1501 static irqreturn_t
1502 jme_msi(int irq, void *dev_id)
1503 {
1504         struct net_device *netdev = dev_id;
1505         struct jme_adapter *jme = netdev_priv(netdev);
1506         u32 intrstat;
1507
1508         intrstat = jread32(jme, JME_IEVE);
1509
1510         jme_intr_msi(jme, intrstat);
1511
1512         return IRQ_HANDLED;
1513 }
1514
1515 static void
1516 jme_reset_link(struct jme_adapter *jme)
1517 {
1518         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1519 }
1520
1521 static void
1522 jme_restart_an(struct jme_adapter *jme)
1523 {
1524         u32 bmcr;
1525
1526         spin_lock_bh(&jme->phy_lock);
1527         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1528         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1529         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1530         spin_unlock_bh(&jme->phy_lock);
1531 }
1532
1533 static int
1534 jme_request_irq(struct jme_adapter *jme)
1535 {
1536         int rc;
1537         struct net_device *netdev = jme->dev;
1538         irq_handler_t handler = jme_intr;
1539         int irq_flags = IRQF_SHARED;
1540
1541         if (!pci_enable_msi(jme->pdev)) {
1542                 set_bit(JME_FLAG_MSI, &jme->flags);
1543                 handler = jme_msi;
1544                 irq_flags = 0;
1545         }
1546
1547         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1548                           netdev);
1549         if (rc) {
1550                 netdev_err(netdev,
1551                            "Unable to request %s interrupt (return: %d)\n",
1552                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1553                            rc);
1554
1555                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1556                         pci_disable_msi(jme->pdev);
1557                         clear_bit(JME_FLAG_MSI, &jme->flags);
1558                 }
1559         } else {
1560                 netdev->irq = jme->pdev->irq;
1561         }
1562
1563         return rc;
1564 }
1565
1566 static void
1567 jme_free_irq(struct jme_adapter *jme)
1568 {
1569         free_irq(jme->pdev->irq, jme->dev);
1570         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1571                 pci_disable_msi(jme->pdev);
1572                 clear_bit(JME_FLAG_MSI, &jme->flags);
1573                 jme->dev->irq = jme->pdev->irq;
1574         }
1575 }
1576
1577 static inline void
1578 jme_phy_on(struct jme_adapter *jme)
1579 {
1580         u32 bmcr;
1581
1582         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1583         bmcr &= ~BMCR_PDOWN;
1584         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1585 }
1586
1587 static int
1588 jme_open(struct net_device *netdev)
1589 {
1590         struct jme_adapter *jme = netdev_priv(netdev);
1591         int rc;
1592
1593         jme_clear_pm(jme);
1594         JME_NAPI_ENABLE(jme);
1595
1596         tasklet_enable(&jme->linkch_task);
1597         tasklet_enable(&jme->txclean_task);
1598         tasklet_hi_enable(&jme->rxclean_task);
1599         tasklet_hi_enable(&jme->rxempty_task);
1600
1601         rc = jme_request_irq(jme);
1602         if (rc)
1603                 goto err_out;
1604
1605         jme_start_irq(jme);
1606
1607         if (test_bit(JME_FLAG_SSET, &jme->flags)) {
1608                 jme_phy_on(jme);
1609                 jme_set_settings(netdev, &jme->old_ecmd);
1610         } else {
1611                 jme_reset_phy_processor(jme);
1612         }
1613
1614         jme_reset_link(jme);
1615
1616         return 0;
1617
1618 err_out:
1619         netif_stop_queue(netdev);
1620         netif_carrier_off(netdev);
1621         return rc;
1622 }
1623
1624 #ifdef CONFIG_PM
1625 static void
1626 jme_set_100m_half(struct jme_adapter *jme)
1627 {
1628         u32 bmcr, tmp;
1629
1630         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1631         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1632                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1633         tmp |= BMCR_SPEED100;
1634
1635         if (bmcr != tmp)
1636                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1637
1638         if (jme->fpgaver)
1639                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1640         else
1641                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1642 }
1643
1644 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1645 static void
1646 jme_wait_link(struct jme_adapter *jme)
1647 {
1648         u32 phylink, to = JME_WAIT_LINK_TIME;
1649
1650         mdelay(1000);
1651         phylink = jme_linkstat_from_phy(jme);
1652         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1653                 mdelay(10);
1654                 phylink = jme_linkstat_from_phy(jme);
1655         }
1656 }
1657 #endif
1658
1659 static inline void
1660 jme_phy_off(struct jme_adapter *jme)
1661 {
1662         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1663 }
1664
1665 static int
1666 jme_close(struct net_device *netdev)
1667 {
1668         struct jme_adapter *jme = netdev_priv(netdev);
1669
1670         netif_stop_queue(netdev);
1671         netif_carrier_off(netdev);
1672
1673         jme_stop_irq(jme);
1674         jme_free_irq(jme);
1675
1676         JME_NAPI_DISABLE(jme);
1677
1678         tasklet_disable(&jme->linkch_task);
1679         tasklet_disable(&jme->txclean_task);
1680         tasklet_disable(&jme->rxclean_task);
1681         tasklet_disable(&jme->rxempty_task);
1682
1683         jme_reset_ghc_speed(jme);
1684         jme_disable_rx_engine(jme);
1685         jme_disable_tx_engine(jme);
1686         jme_reset_mac_processor(jme);
1687         jme_free_rx_resources(jme);
1688         jme_free_tx_resources(jme);
1689         jme->phylink = 0;
1690         jme_phy_off(jme);
1691
1692         return 0;
1693 }
1694
1695 static int
1696 jme_alloc_txdesc(struct jme_adapter *jme,
1697                         struct sk_buff *skb)
1698 {
1699         struct jme_ring *txring = &(jme->txring[0]);
1700         int idx, nr_alloc, mask = jme->tx_ring_mask;
1701
1702         idx = txring->next_to_use;
1703         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1704
1705         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1706                 return -1;
1707
1708         atomic_sub(nr_alloc, &txring->nr_free);
1709
1710         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1711
1712         return idx;
1713 }
1714
1715 static void
1716 jme_fill_tx_map(struct pci_dev *pdev,
1717                 struct txdesc *txdesc,
1718                 struct jme_buffer_info *txbi,
1719                 struct page *page,
1720                 u32 page_offset,
1721                 u32 len,
1722                 u8 hidma)
1723 {
1724         dma_addr_t dmaaddr;
1725
1726         dmaaddr = pci_map_page(pdev,
1727                                 page,
1728                                 page_offset,
1729                                 len,
1730                                 PCI_DMA_TODEVICE);
1731
1732         pci_dma_sync_single_for_device(pdev,
1733                                        dmaaddr,
1734                                        len,
1735                                        PCI_DMA_TODEVICE);
1736
1737         txdesc->dw[0] = 0;
1738         txdesc->dw[1] = 0;
1739         txdesc->desc2.flags     = TXFLAG_OWN;
1740         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1741         txdesc->desc2.datalen   = cpu_to_le16(len);
1742         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1743         txdesc->desc2.bufaddrl  = cpu_to_le32(
1744                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1745
1746         txbi->mapping = dmaaddr;
1747         txbi->len = len;
1748 }
1749
1750 static void
1751 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1752 {
1753         struct jme_ring *txring = &(jme->txring[0]);
1754         struct txdesc *txdesc = txring->desc, *ctxdesc;
1755         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1756         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1757         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1758         int mask = jme->tx_ring_mask;
1759         struct skb_frag_struct *frag;
1760         u32 len;
1761
1762         for (i = 0 ; i < nr_frags ; ++i) {
1763                 frag = &skb_shinfo(skb)->frags[i];
1764                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1765                 ctxbi = txbi + ((idx + i + 2) & (mask));
1766
1767                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1768                                  frag->page_offset, frag->size, hidma);
1769         }
1770
1771         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1772         ctxdesc = txdesc + ((idx + 1) & (mask));
1773         ctxbi = txbi + ((idx + 1) & (mask));
1774         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1775                         offset_in_page(skb->data), len, hidma);
1776
1777 }
1778
1779 static int
1780 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1781 {
1782         if (unlikely(skb_shinfo(skb)->gso_size &&
1783                         skb_header_cloned(skb) &&
1784                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1785                 dev_kfree_skb(skb);
1786                 return -1;
1787         }
1788
1789         return 0;
1790 }
1791
1792 static int
1793 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1794 {
1795         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1796         if (*mss) {
1797                 *flags |= TXFLAG_LSEN;
1798
1799                 if (skb->protocol == htons(ETH_P_IP)) {
1800                         struct iphdr *iph = ip_hdr(skb);
1801
1802                         iph->check = 0;
1803                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1804                                                                 iph->daddr, 0,
1805                                                                 IPPROTO_TCP,
1806                                                                 0);
1807                 } else {
1808                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1809
1810                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1811                                                                 &ip6h->daddr, 0,
1812                                                                 IPPROTO_TCP,
1813                                                                 0);
1814                 }
1815
1816                 return 0;
1817         }
1818
1819         return 1;
1820 }
1821
1822 static void
1823 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1824 {
1825         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1826                 u8 ip_proto;
1827
1828                 switch (skb->protocol) {
1829                 case htons(ETH_P_IP):
1830                         ip_proto = ip_hdr(skb)->protocol;
1831                         break;
1832                 case htons(ETH_P_IPV6):
1833                         ip_proto = ipv6_hdr(skb)->nexthdr;
1834                         break;
1835                 default:
1836                         ip_proto = 0;
1837                         break;
1838                 }
1839
1840                 switch (ip_proto) {
1841                 case IPPROTO_TCP:
1842                         *flags |= TXFLAG_TCPCS;
1843                         break;
1844                 case IPPROTO_UDP:
1845                         *flags |= TXFLAG_UDPCS;
1846                         break;
1847                 default:
1848                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1849                         break;
1850                 }
1851         }
1852 }
1853
1854 static inline void
1855 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1856 {
1857         if (vlan_tx_tag_present(skb)) {
1858                 *flags |= TXFLAG_TAGON;
1859                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1860         }
1861 }
1862
1863 static int
1864 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1865 {
1866         struct jme_ring *txring = &(jme->txring[0]);
1867         struct txdesc *txdesc;
1868         struct jme_buffer_info *txbi;
1869         u8 flags;
1870
1871         txdesc = (struct txdesc *)txring->desc + idx;
1872         txbi = txring->bufinf + idx;
1873
1874         txdesc->dw[0] = 0;
1875         txdesc->dw[1] = 0;
1876         txdesc->dw[2] = 0;
1877         txdesc->dw[3] = 0;
1878         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1879         /*
1880          * Set OWN bit at final.
1881          * When kernel transmit faster than NIC.
1882          * And NIC trying to send this descriptor before we tell
1883          * it to start sending this TX queue.
1884          * Other fields are already filled correctly.
1885          */
1886         wmb();
1887         flags = TXFLAG_OWN | TXFLAG_INT;
1888         /*
1889          * Set checksum flags while not tso
1890          */
1891         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1892                 jme_tx_csum(jme, skb, &flags);
1893         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1894         jme_map_tx_skb(jme, skb, idx);
1895         txdesc->desc1.flags = flags;
1896         /*
1897          * Set tx buffer info after telling NIC to send
1898          * For better tx_clean timing
1899          */
1900         wmb();
1901         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1902         txbi->skb = skb;
1903         txbi->len = skb->len;
1904         txbi->start_xmit = jiffies;
1905         if (!txbi->start_xmit)
1906                 txbi->start_xmit = (0UL-1);
1907
1908         return 0;
1909 }
1910
1911 static void
1912 jme_stop_queue_if_full(struct jme_adapter *jme)
1913 {
1914         struct jme_ring *txring = &(jme->txring[0]);
1915         struct jme_buffer_info *txbi = txring->bufinf;
1916         int idx = atomic_read(&txring->next_to_clean);
1917
1918         txbi += idx;
1919
1920         smp_wmb();
1921         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1922                 netif_stop_queue(jme->dev);
1923                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
1924                 smp_wmb();
1925                 if (atomic_read(&txring->nr_free)
1926                         >= (jme->tx_wake_threshold)) {
1927                         netif_wake_queue(jme->dev);
1928                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
1929                 }
1930         }
1931
1932         if (unlikely(txbi->start_xmit &&
1933                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1934                         txbi->skb)) {
1935                 netif_stop_queue(jme->dev);
1936                 netif_info(jme, tx_queued, jme->dev,
1937                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
1938         }
1939 }
1940
1941 /*
1942  * This function is already protected by netif_tx_lock()
1943  */
1944
1945 static netdev_tx_t
1946 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1947 {
1948         struct jme_adapter *jme = netdev_priv(netdev);
1949         int idx;
1950
1951         if (unlikely(jme_expand_header(jme, skb))) {
1952                 ++(NET_STAT(jme).tx_dropped);
1953                 return NETDEV_TX_OK;
1954         }
1955
1956         idx = jme_alloc_txdesc(jme, skb);
1957
1958         if (unlikely(idx < 0)) {
1959                 netif_stop_queue(netdev);
1960                 netif_err(jme, tx_err, jme->dev,
1961                           "BUG! Tx ring full when queue awake!\n");
1962
1963                 return NETDEV_TX_BUSY;
1964         }
1965
1966         jme_fill_tx_desc(jme, skb, idx);
1967
1968         jwrite32(jme, JME_TXCS, jme->reg_txcs |
1969                                 TXCS_SELECT_QUEUE0 |
1970                                 TXCS_QUEUE0S |
1971                                 TXCS_ENABLE);
1972
1973         tx_dbg(jme, "xmit: %d+%d@%lu\n",
1974                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
1975         jme_stop_queue_if_full(jme);
1976
1977         return NETDEV_TX_OK;
1978 }
1979
1980 static int
1981 jme_set_macaddr(struct net_device *netdev, void *p)
1982 {
1983         struct jme_adapter *jme = netdev_priv(netdev);
1984         struct sockaddr *addr = p;
1985         u32 val;
1986
1987         if (netif_running(netdev))
1988                 return -EBUSY;
1989
1990         spin_lock_bh(&jme->macaddr_lock);
1991         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1992
1993         val = (addr->sa_data[3] & 0xff) << 24 |
1994               (addr->sa_data[2] & 0xff) << 16 |
1995               (addr->sa_data[1] & 0xff) <<  8 |
1996               (addr->sa_data[0] & 0xff);
1997         jwrite32(jme, JME_RXUMA_LO, val);
1998         val = (addr->sa_data[5] & 0xff) << 8 |
1999               (addr->sa_data[4] & 0xff);
2000         jwrite32(jme, JME_RXUMA_HI, val);
2001         spin_unlock_bh(&jme->macaddr_lock);
2002
2003         return 0;
2004 }
2005
2006 static void
2007 jme_set_multi(struct net_device *netdev)
2008 {
2009         struct jme_adapter *jme = netdev_priv(netdev);
2010         u32 mc_hash[2] = {};
2011
2012         spin_lock_bh(&jme->rxmcs_lock);
2013
2014         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2015
2016         if (netdev->flags & IFF_PROMISC) {
2017                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2018         } else if (netdev->flags & IFF_ALLMULTI) {
2019                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2020         } else if (netdev->flags & IFF_MULTICAST) {
2021                 struct netdev_hw_addr *ha;
2022                 int bit_nr;
2023
2024                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2025                 netdev_for_each_mc_addr(ha, netdev) {
2026                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2027                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2028                 }
2029
2030                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2031                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2032         }
2033
2034         wmb();
2035         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2036
2037         spin_unlock_bh(&jme->rxmcs_lock);
2038 }
2039
2040 static int
2041 jme_change_mtu(struct net_device *netdev, int new_mtu)
2042 {
2043         struct jme_adapter *jme = netdev_priv(netdev);
2044
2045         if (new_mtu == jme->old_mtu)
2046                 return 0;
2047
2048         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2049                 ((new_mtu) < IPV6_MIN_MTU))
2050                 return -EINVAL;
2051
2052         if (new_mtu > 4000) {
2053                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2054                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2055                 jme_restart_rx_engine(jme);
2056         } else {
2057                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2058                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2059                 jme_restart_rx_engine(jme);
2060         }
2061
2062         if (new_mtu > 1900) {
2063                 netdev->features &= ~(NETIF_F_HW_CSUM |
2064                                 NETIF_F_TSO |
2065                                 NETIF_F_TSO6);
2066         } else {
2067                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2068                         netdev->features |= NETIF_F_HW_CSUM;
2069                 if (test_bit(JME_FLAG_TSO, &jme->flags))
2070                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2071         }
2072
2073         netdev->mtu = new_mtu;
2074         jme_reset_link(jme);
2075
2076         return 0;
2077 }
2078
2079 static void
2080 jme_tx_timeout(struct net_device *netdev)
2081 {
2082         struct jme_adapter *jme = netdev_priv(netdev);
2083
2084         jme->phylink = 0;
2085         jme_reset_phy_processor(jme);
2086         if (test_bit(JME_FLAG_SSET, &jme->flags))
2087                 jme_set_settings(netdev, &jme->old_ecmd);
2088
2089         /*
2090          * Force to Reset the link again
2091          */
2092         jme_reset_link(jme);
2093 }
2094
2095 static inline void jme_pause_rx(struct jme_adapter *jme)
2096 {
2097         atomic_dec(&jme->link_changing);
2098
2099         jme_set_rx_pcc(jme, PCC_OFF);
2100         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2101                 JME_NAPI_DISABLE(jme);
2102         } else {
2103                 tasklet_disable(&jme->rxclean_task);
2104                 tasklet_disable(&jme->rxempty_task);
2105         }
2106 }
2107
2108 static inline void jme_resume_rx(struct jme_adapter *jme)
2109 {
2110         struct dynpcc_info *dpi = &(jme->dpi);
2111
2112         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2113                 JME_NAPI_ENABLE(jme);
2114         } else {
2115                 tasklet_hi_enable(&jme->rxclean_task);
2116                 tasklet_hi_enable(&jme->rxempty_task);
2117         }
2118         dpi->cur                = PCC_P1;
2119         dpi->attempt            = PCC_P1;
2120         dpi->cnt                = 0;
2121         jme_set_rx_pcc(jme, PCC_P1);
2122
2123         atomic_inc(&jme->link_changing);
2124 }
2125
2126 static void
2127 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2128 {
2129         struct jme_adapter *jme = netdev_priv(netdev);
2130
2131         jme_pause_rx(jme);
2132         jme->vlgrp = grp;
2133         jme_resume_rx(jme);
2134 }
2135
2136 static void
2137 jme_get_drvinfo(struct net_device *netdev,
2138                      struct ethtool_drvinfo *info)
2139 {
2140         struct jme_adapter *jme = netdev_priv(netdev);
2141
2142         strcpy(info->driver, DRV_NAME);
2143         strcpy(info->version, DRV_VERSION);
2144         strcpy(info->bus_info, pci_name(jme->pdev));
2145 }
2146
2147 static int
2148 jme_get_regs_len(struct net_device *netdev)
2149 {
2150         return JME_REG_LEN;
2151 }
2152
2153 static void
2154 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2155 {
2156         int i;
2157
2158         for (i = 0 ; i < len ; i += 4)
2159                 p[i >> 2] = jread32(jme, reg + i);
2160 }
2161
2162 static void
2163 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2164 {
2165         int i;
2166         u16 *p16 = (u16 *)p;
2167
2168         for (i = 0 ; i < reg_nr ; ++i)
2169                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2170 }
2171
2172 static void
2173 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2174 {
2175         struct jme_adapter *jme = netdev_priv(netdev);
2176         u32 *p32 = (u32 *)p;
2177
2178         memset(p, 0xFF, JME_REG_LEN);
2179
2180         regs->version = 1;
2181         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2182
2183         p32 += 0x100 >> 2;
2184         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2185
2186         p32 += 0x100 >> 2;
2187         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2188
2189         p32 += 0x100 >> 2;
2190         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2191
2192         p32 += 0x100 >> 2;
2193         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2194 }
2195
2196 static int
2197 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2198 {
2199         struct jme_adapter *jme = netdev_priv(netdev);
2200
2201         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2202         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2203
2204         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2205                 ecmd->use_adaptive_rx_coalesce = false;
2206                 ecmd->rx_coalesce_usecs = 0;
2207                 ecmd->rx_max_coalesced_frames = 0;
2208                 return 0;
2209         }
2210
2211         ecmd->use_adaptive_rx_coalesce = true;
2212
2213         switch (jme->dpi.cur) {
2214         case PCC_P1:
2215                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2216                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2217                 break;
2218         case PCC_P2:
2219                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2220                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2221                 break;
2222         case PCC_P3:
2223                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2224                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2225                 break;
2226         default:
2227                 break;
2228         }
2229
2230         return 0;
2231 }
2232
2233 static int
2234 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2235 {
2236         struct jme_adapter *jme = netdev_priv(netdev);
2237         struct dynpcc_info *dpi = &(jme->dpi);
2238
2239         if (netif_running(netdev))
2240                 return -EBUSY;
2241
2242         if (ecmd->use_adaptive_rx_coalesce &&
2243             test_bit(JME_FLAG_POLL, &jme->flags)) {
2244                 clear_bit(JME_FLAG_POLL, &jme->flags);
2245                 jme->jme_rx = netif_rx;
2246                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2247                 dpi->cur                = PCC_P1;
2248                 dpi->attempt            = PCC_P1;
2249                 dpi->cnt                = 0;
2250                 jme_set_rx_pcc(jme, PCC_P1);
2251                 jme_interrupt_mode(jme);
2252         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2253                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2254                 set_bit(JME_FLAG_POLL, &jme->flags);
2255                 jme->jme_rx = netif_receive_skb;
2256                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2257                 jme_interrupt_mode(jme);
2258         }
2259
2260         return 0;
2261 }
2262
2263 static void
2264 jme_get_pauseparam(struct net_device *netdev,
2265                         struct ethtool_pauseparam *ecmd)
2266 {
2267         struct jme_adapter *jme = netdev_priv(netdev);
2268         u32 val;
2269
2270         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2271         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2272
2273         spin_lock_bh(&jme->phy_lock);
2274         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2275         spin_unlock_bh(&jme->phy_lock);
2276
2277         ecmd->autoneg =
2278                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2279 }
2280
2281 static int
2282 jme_set_pauseparam(struct net_device *netdev,
2283                         struct ethtool_pauseparam *ecmd)
2284 {
2285         struct jme_adapter *jme = netdev_priv(netdev);
2286         u32 val;
2287
2288         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2289                 (ecmd->tx_pause != 0)) {
2290
2291                 if (ecmd->tx_pause)
2292                         jme->reg_txpfc |= TXPFC_PF_EN;
2293                 else
2294                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2295
2296                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2297         }
2298
2299         spin_lock_bh(&jme->rxmcs_lock);
2300         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2301                 (ecmd->rx_pause != 0)) {
2302
2303                 if (ecmd->rx_pause)
2304                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2305                 else
2306                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2307
2308                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2309         }
2310         spin_unlock_bh(&jme->rxmcs_lock);
2311
2312         spin_lock_bh(&jme->phy_lock);
2313         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2314         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2315                 (ecmd->autoneg != 0)) {
2316
2317                 if (ecmd->autoneg)
2318                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2319                 else
2320                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2321
2322                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2323                                 MII_ADVERTISE, val);
2324         }
2325         spin_unlock_bh(&jme->phy_lock);
2326
2327         return 0;
2328 }
2329
2330 static void
2331 jme_get_wol(struct net_device *netdev,
2332                 struct ethtool_wolinfo *wol)
2333 {
2334         struct jme_adapter *jme = netdev_priv(netdev);
2335
2336         wol->supported = WAKE_MAGIC | WAKE_PHY;
2337
2338         wol->wolopts = 0;
2339
2340         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2341                 wol->wolopts |= WAKE_PHY;
2342
2343         if (jme->reg_pmcs & PMCS_MFEN)
2344                 wol->wolopts |= WAKE_MAGIC;
2345
2346 }
2347
2348 static int
2349 jme_set_wol(struct net_device *netdev,
2350                 struct ethtool_wolinfo *wol)
2351 {
2352         struct jme_adapter *jme = netdev_priv(netdev);
2353
2354         if (wol->wolopts & (WAKE_MAGICSECURE |
2355                                 WAKE_UCAST |
2356                                 WAKE_MCAST |
2357                                 WAKE_BCAST |
2358                                 WAKE_ARP))
2359                 return -EOPNOTSUPP;
2360
2361         jme->reg_pmcs = 0;
2362
2363         if (wol->wolopts & WAKE_PHY)
2364                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2365
2366         if (wol->wolopts & WAKE_MAGIC)
2367                 jme->reg_pmcs |= PMCS_MFEN;
2368
2369         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2370
2371         return 0;
2372 }
2373
2374 static int
2375 jme_get_settings(struct net_device *netdev,
2376                      struct ethtool_cmd *ecmd)
2377 {
2378         struct jme_adapter *jme = netdev_priv(netdev);
2379         int rc;
2380
2381         spin_lock_bh(&jme->phy_lock);
2382         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2383         spin_unlock_bh(&jme->phy_lock);
2384         return rc;
2385 }
2386
2387 static int
2388 jme_set_settings(struct net_device *netdev,
2389                      struct ethtool_cmd *ecmd)
2390 {
2391         struct jme_adapter *jme = netdev_priv(netdev);
2392         int rc, fdc = 0;
2393
2394         if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2395                 return -EINVAL;
2396
2397         /*
2398          * Check If user changed duplex only while force_media.
2399          * Hardware would not generate link change interrupt.
2400          */
2401         if (jme->mii_if.force_media &&
2402         ecmd->autoneg != AUTONEG_ENABLE &&
2403         (jme->mii_if.full_duplex != ecmd->duplex))
2404                 fdc = 1;
2405
2406         spin_lock_bh(&jme->phy_lock);
2407         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2408         spin_unlock_bh(&jme->phy_lock);
2409
2410         if (!rc) {
2411                 if (fdc)
2412                         jme_reset_link(jme);
2413                 set_bit(JME_FLAG_SSET, &jme->flags);
2414                 jme->old_ecmd = *ecmd;
2415         }
2416
2417         return rc;
2418 }
2419
2420 static u32
2421 jme_get_link(struct net_device *netdev)
2422 {
2423         struct jme_adapter *jme = netdev_priv(netdev);
2424         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2425 }
2426
2427 static u32
2428 jme_get_msglevel(struct net_device *netdev)
2429 {
2430         struct jme_adapter *jme = netdev_priv(netdev);
2431         return jme->msg_enable;
2432 }
2433
2434 static void
2435 jme_set_msglevel(struct net_device *netdev, u32 value)
2436 {
2437         struct jme_adapter *jme = netdev_priv(netdev);
2438         jme->msg_enable = value;
2439 }
2440
2441 static u32
2442 jme_get_rx_csum(struct net_device *netdev)
2443 {
2444         struct jme_adapter *jme = netdev_priv(netdev);
2445         return jme->reg_rxmcs & RXMCS_CHECKSUM;
2446 }
2447
2448 static int
2449 jme_set_rx_csum(struct net_device *netdev, u32 on)
2450 {
2451         struct jme_adapter *jme = netdev_priv(netdev);
2452
2453         spin_lock_bh(&jme->rxmcs_lock);
2454         if (on)
2455                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2456         else
2457                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2458         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2459         spin_unlock_bh(&jme->rxmcs_lock);
2460
2461         return 0;
2462 }
2463
2464 static int
2465 jme_set_tx_csum(struct net_device *netdev, u32 on)
2466 {
2467         struct jme_adapter *jme = netdev_priv(netdev);
2468
2469         if (on) {
2470                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2471                 if (netdev->mtu <= 1900)
2472                         netdev->features |= NETIF_F_HW_CSUM;
2473         } else {
2474                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2475                 netdev->features &= ~NETIF_F_HW_CSUM;
2476         }
2477
2478         return 0;
2479 }
2480
2481 static int
2482 jme_set_tso(struct net_device *netdev, u32 on)
2483 {
2484         struct jme_adapter *jme = netdev_priv(netdev);
2485
2486         if (on) {
2487                 set_bit(JME_FLAG_TSO, &jme->flags);
2488                 if (netdev->mtu <= 1900)
2489                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2490         } else {
2491                 clear_bit(JME_FLAG_TSO, &jme->flags);
2492                 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2493         }
2494
2495         return 0;
2496 }
2497
2498 static int
2499 jme_nway_reset(struct net_device *netdev)
2500 {
2501         struct jme_adapter *jme = netdev_priv(netdev);
2502         jme_restart_an(jme);
2503         return 0;
2504 }
2505
2506 static u8
2507 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2508 {
2509         u32 val;
2510         int to;
2511
2512         val = jread32(jme, JME_SMBCSR);
2513         to = JME_SMB_BUSY_TIMEOUT;
2514         while ((val & SMBCSR_BUSY) && --to) {
2515                 msleep(1);
2516                 val = jread32(jme, JME_SMBCSR);
2517         }
2518         if (!to) {
2519                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2520                 return 0xFF;
2521         }
2522
2523         jwrite32(jme, JME_SMBINTF,
2524                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2525                 SMBINTF_HWRWN_READ |
2526                 SMBINTF_HWCMD);
2527
2528         val = jread32(jme, JME_SMBINTF);
2529         to = JME_SMB_BUSY_TIMEOUT;
2530         while ((val & SMBINTF_HWCMD) && --to) {
2531                 msleep(1);
2532                 val = jread32(jme, JME_SMBINTF);
2533         }
2534         if (!to) {
2535                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2536                 return 0xFF;
2537         }
2538
2539         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2540 }
2541
2542 static void
2543 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2544 {
2545         u32 val;
2546         int to;
2547
2548         val = jread32(jme, JME_SMBCSR);
2549         to = JME_SMB_BUSY_TIMEOUT;
2550         while ((val & SMBCSR_BUSY) && --to) {
2551                 msleep(1);
2552                 val = jread32(jme, JME_SMBCSR);
2553         }
2554         if (!to) {
2555                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2556                 return;
2557         }
2558
2559         jwrite32(jme, JME_SMBINTF,
2560                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2561                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2562                 SMBINTF_HWRWN_WRITE |
2563                 SMBINTF_HWCMD);
2564
2565         val = jread32(jme, JME_SMBINTF);
2566         to = JME_SMB_BUSY_TIMEOUT;
2567         while ((val & SMBINTF_HWCMD) && --to) {
2568                 msleep(1);
2569                 val = jread32(jme, JME_SMBINTF);
2570         }
2571         if (!to) {
2572                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2573                 return;
2574         }
2575
2576         mdelay(2);
2577 }
2578
2579 static int
2580 jme_get_eeprom_len(struct net_device *netdev)
2581 {
2582         struct jme_adapter *jme = netdev_priv(netdev);
2583         u32 val;
2584         val = jread32(jme, JME_SMBCSR);
2585         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2586 }
2587
2588 static int
2589 jme_get_eeprom(struct net_device *netdev,
2590                 struct ethtool_eeprom *eeprom, u8 *data)
2591 {
2592         struct jme_adapter *jme = netdev_priv(netdev);
2593         int i, offset = eeprom->offset, len = eeprom->len;
2594
2595         /*
2596          * ethtool will check the boundary for us
2597          */
2598         eeprom->magic = JME_EEPROM_MAGIC;
2599         for (i = 0 ; i < len ; ++i)
2600                 data[i] = jme_smb_read(jme, i + offset);
2601
2602         return 0;
2603 }
2604
2605 static int
2606 jme_set_eeprom(struct net_device *netdev,
2607                 struct ethtool_eeprom *eeprom, u8 *data)
2608 {
2609         struct jme_adapter *jme = netdev_priv(netdev);
2610         int i, offset = eeprom->offset, len = eeprom->len;
2611
2612         if (eeprom->magic != JME_EEPROM_MAGIC)
2613                 return -EINVAL;
2614
2615         /*
2616          * ethtool will check the boundary for us
2617          */
2618         for (i = 0 ; i < len ; ++i)
2619                 jme_smb_write(jme, i + offset, data[i]);
2620
2621         return 0;
2622 }
2623
2624 static const struct ethtool_ops jme_ethtool_ops = {
2625         .get_drvinfo            = jme_get_drvinfo,
2626         .get_regs_len           = jme_get_regs_len,
2627         .get_regs               = jme_get_regs,
2628         .get_coalesce           = jme_get_coalesce,
2629         .set_coalesce           = jme_set_coalesce,
2630         .get_pauseparam         = jme_get_pauseparam,
2631         .set_pauseparam         = jme_set_pauseparam,
2632         .get_wol                = jme_get_wol,
2633         .set_wol                = jme_set_wol,
2634         .get_settings           = jme_get_settings,
2635         .set_settings           = jme_set_settings,
2636         .get_link               = jme_get_link,
2637         .get_msglevel           = jme_get_msglevel,
2638         .set_msglevel           = jme_set_msglevel,
2639         .get_rx_csum            = jme_get_rx_csum,
2640         .set_rx_csum            = jme_set_rx_csum,
2641         .set_tx_csum            = jme_set_tx_csum,
2642         .set_tso                = jme_set_tso,
2643         .set_sg                 = ethtool_op_set_sg,
2644         .nway_reset             = jme_nway_reset,
2645         .get_eeprom_len         = jme_get_eeprom_len,
2646         .get_eeprom             = jme_get_eeprom,
2647         .set_eeprom             = jme_set_eeprom,
2648 };
2649
2650 static int
2651 jme_pci_dma64(struct pci_dev *pdev)
2652 {
2653         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2654             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2655                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2656                         return 1;
2657
2658         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2659             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2660                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2661                         return 1;
2662
2663         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2664                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2665                         return 0;
2666
2667         return -1;
2668 }
2669
2670 static inline void
2671 jme_phy_init(struct jme_adapter *jme)
2672 {
2673         u16 reg26;
2674
2675         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2676         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2677 }
2678
2679 static inline void
2680 jme_check_hw_ver(struct jme_adapter *jme)
2681 {
2682         u32 chipmode;
2683
2684         chipmode = jread32(jme, JME_CHIPMODE);
2685
2686         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2687         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2688 }
2689
2690 static const struct net_device_ops jme_netdev_ops = {
2691         .ndo_open               = jme_open,
2692         .ndo_stop               = jme_close,
2693         .ndo_validate_addr      = eth_validate_addr,
2694         .ndo_start_xmit         = jme_start_xmit,
2695         .ndo_set_mac_address    = jme_set_macaddr,
2696         .ndo_set_multicast_list = jme_set_multi,
2697         .ndo_change_mtu         = jme_change_mtu,
2698         .ndo_tx_timeout         = jme_tx_timeout,
2699         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2700 };
2701
2702 static int __devinit
2703 jme_init_one(struct pci_dev *pdev,
2704              const struct pci_device_id *ent)
2705 {
2706         int rc = 0, using_dac, i;
2707         struct net_device *netdev;
2708         struct jme_adapter *jme;
2709         u16 bmcr, bmsr;
2710         u32 apmc;
2711
2712         /*
2713          * set up PCI device basics
2714          */
2715         rc = pci_enable_device(pdev);
2716         if (rc) {
2717                 pr_err("Cannot enable PCI device\n");
2718                 goto err_out;
2719         }
2720
2721         using_dac = jme_pci_dma64(pdev);
2722         if (using_dac < 0) {
2723                 pr_err("Cannot set PCI DMA Mask\n");
2724                 rc = -EIO;
2725                 goto err_out_disable_pdev;
2726         }
2727
2728         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2729                 pr_err("No PCI resource region found\n");
2730                 rc = -ENOMEM;
2731                 goto err_out_disable_pdev;
2732         }
2733
2734         rc = pci_request_regions(pdev, DRV_NAME);
2735         if (rc) {
2736                 pr_err("Cannot obtain PCI resource region\n");
2737                 goto err_out_disable_pdev;
2738         }
2739
2740         pci_set_master(pdev);
2741
2742         /*
2743          * alloc and init net device
2744          */
2745         netdev = alloc_etherdev(sizeof(*jme));
2746         if (!netdev) {
2747                 pr_err("Cannot allocate netdev structure\n");
2748                 rc = -ENOMEM;
2749                 goto err_out_release_regions;
2750         }
2751         netdev->netdev_ops = &jme_netdev_ops;
2752         netdev->ethtool_ops             = &jme_ethtool_ops;
2753         netdev->watchdog_timeo          = TX_TIMEOUT;
2754         netdev->features                =       NETIF_F_HW_CSUM |
2755                                                 NETIF_F_SG |
2756                                                 NETIF_F_TSO |
2757                                                 NETIF_F_TSO6 |
2758                                                 NETIF_F_HW_VLAN_TX |
2759                                                 NETIF_F_HW_VLAN_RX;
2760         if (using_dac)
2761                 netdev->features        |=      NETIF_F_HIGHDMA;
2762
2763         SET_NETDEV_DEV(netdev, &pdev->dev);
2764         pci_set_drvdata(pdev, netdev);
2765
2766         /*
2767          * init adapter info
2768          */
2769         jme = netdev_priv(netdev);
2770         jme->pdev = pdev;
2771         jme->dev = netdev;
2772         jme->jme_rx = netif_rx;
2773         jme->jme_vlan_rx = vlan_hwaccel_rx;
2774         jme->old_mtu = netdev->mtu = 1500;
2775         jme->phylink = 0;
2776         jme->tx_ring_size = 1 << 10;
2777         jme->tx_ring_mask = jme->tx_ring_size - 1;
2778         jme->tx_wake_threshold = 1 << 9;
2779         jme->rx_ring_size = 1 << 9;
2780         jme->rx_ring_mask = jme->rx_ring_size - 1;
2781         jme->msg_enable = JME_DEF_MSG_ENABLE;
2782         jme->regs = ioremap(pci_resource_start(pdev, 0),
2783                              pci_resource_len(pdev, 0));
2784         if (!(jme->regs)) {
2785                 pr_err("Mapping PCI resource region error\n");
2786                 rc = -ENOMEM;
2787                 goto err_out_free_netdev;
2788         }
2789
2790         if (no_pseudohp) {
2791                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2792                 jwrite32(jme, JME_APMC, apmc);
2793         } else if (force_pseudohp) {
2794                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2795                 jwrite32(jme, JME_APMC, apmc);
2796         }
2797
2798         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2799
2800         spin_lock_init(&jme->phy_lock);
2801         spin_lock_init(&jme->macaddr_lock);
2802         spin_lock_init(&jme->rxmcs_lock);
2803
2804         atomic_set(&jme->link_changing, 1);
2805         atomic_set(&jme->rx_cleaning, 1);
2806         atomic_set(&jme->tx_cleaning, 1);
2807         atomic_set(&jme->rx_empty, 1);
2808
2809         tasklet_init(&jme->pcc_task,
2810                      jme_pcc_tasklet,
2811                      (unsigned long) jme);
2812         tasklet_init(&jme->linkch_task,
2813                      jme_link_change_tasklet,
2814                      (unsigned long) jme);
2815         tasklet_init(&jme->txclean_task,
2816                      jme_tx_clean_tasklet,
2817                      (unsigned long) jme);
2818         tasklet_init(&jme->rxclean_task,
2819                      jme_rx_clean_tasklet,
2820                      (unsigned long) jme);
2821         tasklet_init(&jme->rxempty_task,
2822                      jme_rx_empty_tasklet,
2823                      (unsigned long) jme);
2824         tasklet_disable_nosync(&jme->linkch_task);
2825         tasklet_disable_nosync(&jme->txclean_task);
2826         tasklet_disable_nosync(&jme->rxclean_task);
2827         tasklet_disable_nosync(&jme->rxempty_task);
2828         jme->dpi.cur = PCC_P1;
2829
2830         jme->reg_ghc = 0;
2831         jme->reg_rxcs = RXCS_DEFAULT;
2832         jme->reg_rxmcs = RXMCS_DEFAULT;
2833         jme->reg_txpfc = 0;
2834         jme->reg_pmcs = PMCS_MFEN;
2835         set_bit(JME_FLAG_TXCSUM, &jme->flags);
2836         set_bit(JME_FLAG_TSO, &jme->flags);
2837
2838         /*
2839          * Get Max Read Req Size from PCI Config Space
2840          */
2841         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2842         jme->mrrs &= PCI_DCSR_MRRS_MASK;
2843         switch (jme->mrrs) {
2844         case MRRS_128B:
2845                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2846                 break;
2847         case MRRS_256B:
2848                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2849                 break;
2850         default:
2851                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2852                 break;
2853         }
2854
2855         /*
2856          * Must check before reset_mac_processor
2857          */
2858         jme_check_hw_ver(jme);
2859         jme->mii_if.dev = netdev;
2860         if (jme->fpgaver) {
2861                 jme->mii_if.phy_id = 0;
2862                 for (i = 1 ; i < 32 ; ++i) {
2863                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2864                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2865                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2866                                 jme->mii_if.phy_id = i;
2867                                 break;
2868                         }
2869                 }
2870
2871                 if (!jme->mii_if.phy_id) {
2872                         rc = -EIO;
2873                         pr_err("Can not find phy_id\n");
2874                         goto err_out_unmap;
2875                 }
2876
2877                 jme->reg_ghc |= GHC_LINK_POLL;
2878         } else {
2879                 jme->mii_if.phy_id = 1;
2880         }
2881         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2882                 jme->mii_if.supports_gmii = true;
2883         else
2884                 jme->mii_if.supports_gmii = false;
2885         jme->mii_if.mdio_read = jme_mdio_read;
2886         jme->mii_if.mdio_write = jme_mdio_write;
2887
2888         jme_clear_pm(jme);
2889         jme_set_phyfifoa(jme);
2890         pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2891         if (!jme->fpgaver)
2892                 jme_phy_init(jme);
2893         jme_phy_off(jme);
2894
2895         /*
2896          * Reset MAC processor and reload EEPROM for MAC Address
2897          */
2898         jme_reset_mac_processor(jme);
2899         rc = jme_reload_eeprom(jme);
2900         if (rc) {
2901                 pr_err("Reload eeprom for reading MAC Address error\n");
2902                 goto err_out_unmap;
2903         }
2904         jme_load_macaddr(netdev);
2905
2906         /*
2907          * Tell stack that we are not ready to work until open()
2908          */
2909         netif_carrier_off(netdev);
2910         netif_stop_queue(netdev);
2911
2912         /*
2913          * Register netdev
2914          */
2915         rc = register_netdev(netdev);
2916         if (rc) {
2917                 pr_err("Cannot register net device\n");
2918                 goto err_out_unmap;
2919         }
2920
2921         netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2922                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2923                    "JMC250 Gigabit Ethernet" :
2924                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2925                    "JMC260 Fast Ethernet" : "Unknown",
2926                    (jme->fpgaver != 0) ? " (FPGA)" : "",
2927                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2928                    jme->rev, netdev->dev_addr);
2929
2930         return 0;
2931
2932 err_out_unmap:
2933         iounmap(jme->regs);
2934 err_out_free_netdev:
2935         pci_set_drvdata(pdev, NULL);
2936         free_netdev(netdev);
2937 err_out_release_regions:
2938         pci_release_regions(pdev);
2939 err_out_disable_pdev:
2940         pci_disable_device(pdev);
2941 err_out:
2942         return rc;
2943 }
2944
2945 static void __devexit
2946 jme_remove_one(struct pci_dev *pdev)
2947 {
2948         struct net_device *netdev = pci_get_drvdata(pdev);
2949         struct jme_adapter *jme = netdev_priv(netdev);
2950
2951         unregister_netdev(netdev);
2952         iounmap(jme->regs);
2953         pci_set_drvdata(pdev, NULL);
2954         free_netdev(netdev);
2955         pci_release_regions(pdev);
2956         pci_disable_device(pdev);
2957
2958 }
2959
2960 #ifdef CONFIG_PM
2961 static int
2962 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2963 {
2964         struct net_device *netdev = pci_get_drvdata(pdev);
2965         struct jme_adapter *jme = netdev_priv(netdev);
2966
2967         atomic_dec(&jme->link_changing);
2968
2969         netif_device_detach(netdev);
2970         netif_stop_queue(netdev);
2971         jme_stop_irq(jme);
2972
2973         tasklet_disable(&jme->txclean_task);
2974         tasklet_disable(&jme->rxclean_task);
2975         tasklet_disable(&jme->rxempty_task);
2976
2977         if (netif_carrier_ok(netdev)) {
2978                 if (test_bit(JME_FLAG_POLL, &jme->flags))
2979                         jme_polling_mode(jme);
2980
2981                 jme_stop_pcc_timer(jme);
2982                 jme_reset_ghc_speed(jme);
2983                 jme_disable_rx_engine(jme);
2984                 jme_disable_tx_engine(jme);
2985                 jme_reset_mac_processor(jme);
2986                 jme_free_rx_resources(jme);
2987                 jme_free_tx_resources(jme);
2988                 netif_carrier_off(netdev);
2989                 jme->phylink = 0;
2990         }
2991
2992         tasklet_enable(&jme->txclean_task);
2993         tasklet_hi_enable(&jme->rxclean_task);
2994         tasklet_hi_enable(&jme->rxempty_task);
2995
2996         pci_save_state(pdev);
2997         if (jme->reg_pmcs) {
2998                 jme_set_100m_half(jme);
2999
3000                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
3001                         jme_wait_link(jme);
3002
3003                 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
3004
3005                 pci_enable_wake(pdev, PCI_D3cold, true);
3006         } else {
3007                 jme_phy_off(jme);
3008         }
3009         pci_set_power_state(pdev, PCI_D3cold);
3010
3011         return 0;
3012 }
3013
3014 static int
3015 jme_resume(struct pci_dev *pdev)
3016 {
3017         struct net_device *netdev = pci_get_drvdata(pdev);
3018         struct jme_adapter *jme = netdev_priv(netdev);
3019
3020         jme_clear_pm(jme);
3021         pci_restore_state(pdev);
3022
3023         if (test_bit(JME_FLAG_SSET, &jme->flags)) {
3024                 jme_phy_on(jme);
3025                 jme_set_settings(netdev, &jme->old_ecmd);
3026         } else {
3027                 jme_reset_phy_processor(jme);
3028         }
3029
3030         jme_start_irq(jme);
3031         netif_device_attach(netdev);
3032
3033         atomic_inc(&jme->link_changing);
3034
3035         jme_reset_link(jme);
3036
3037         return 0;
3038 }
3039 #endif
3040
3041 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3042         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3043         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3044         { }
3045 };
3046
3047 static struct pci_driver jme_driver = {
3048         .name           = DRV_NAME,
3049         .id_table       = jme_pci_tbl,
3050         .probe          = jme_init_one,
3051         .remove         = __devexit_p(jme_remove_one),
3052 #ifdef CONFIG_PM
3053         .suspend        = jme_suspend,
3054         .resume         = jme_resume,
3055 #endif /* CONFIG_PM */
3056 };
3057
3058 static int __init
3059 jme_init_module(void)
3060 {
3061         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3062         return pci_register_driver(&jme_driver);
3063 }
3064
3065 static void __exit
3066 jme_cleanup_module(void)
3067 {
3068         pci_unregister_driver(&jme_driver);
3069 }
3070
3071 module_init(jme_init_module);
3072 module_exit(jme_cleanup_module);
3073
3074 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3075 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3076 MODULE_LICENSE("GPL");
3077 MODULE_VERSION(DRV_VERSION);
3078 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3079