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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#include <linux/version.h>
25
26#define DRV_NAME "jme"
27#define DRV_VERSION "0.9a"
28#define PFX DRV_NAME ": "
29
30#ifdef DEBUG
31#define dprintk(devname, fmt, args...) \
32 printk(KERN_DEBUG "%s: " fmt, devname, ## args)
33#else
34#define dprintk(devname, fmt, args...)
35#endif
36
37#ifdef TX_DEBUG
38#define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
39#else
40#define tx_dbg(args...)
41#endif
42
43#ifdef RX_DEBUG
44#define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
45#else
46#define rx_dbg(args...)
47#endif
48
49#ifdef QUEUE_DEBUG
50#define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
51#else
52#define queue_dbg(args...)
53#endif
54
55#ifdef CSUM_DEBUG
56#define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
57#else
58#define csum_dbg(args...)
59#endif
60
61#ifdef VLAN_DEBUG
62#define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
63#else
64#define vlan_dbg(args...)
65#endif
66
67#define jprintk(devname, fmt, args...) \
68 printk(KERN_INFO "%s: " fmt, devname, ## args)
69
70#define jeprintk(devname, fmt, args...) \
71 printk(KERN_ERR "%s: " fmt, devname, ## args)
72
73#define DEFAULT_MSG_ENABLE \
74 (NETIF_MSG_DRV | \
75 NETIF_MSG_PROBE | \
76 NETIF_MSG_LINK | \
77 NETIF_MSG_TIMER | \
78 NETIF_MSG_RX_ERR | \
79 NETIF_MSG_TX_ERR)
80
81#define PCI_CONF_DCSR_MRRS 0x59
82#define PCI_CONF_DCSR_MRRS_MASK 0x70
83enum pci_conf_dcsr_mrrs_vals {
84 MRRS_128B = 0x00,
85 MRRS_256B = 0x10,
86 MRRS_512B = 0x20,
87 MRRS_1024B = 0x30,
88 MRRS_2048B = 0x40,
89 MRRS_4096B = 0x50,
90};
91
92#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
93#define MIN_ETHERNET_PACKET_SIZE 60
94
95enum dynamic_pcc_values {
96 PCC_OFF = 0,
97 PCC_P1 = 1,
98 PCC_P2 = 2,
99 PCC_P3 = 3,
100
101 PCC_OFF_TO = 0,
102 PCC_P1_TO = 1,
103 PCC_P2_TO = 64,
104 PCC_P3_TO = 128,
105
106 PCC_OFF_CNT = 0,
107 PCC_P1_CNT = 1,
108 PCC_P2_CNT = 16,
109 PCC_P3_CNT = 32,
110};
111struct dynpcc_info {
112 unsigned long last_bytes;
113 unsigned long last_pkts;
114 unsigned long intr_cnt;
115 unsigned char cur;
116 unsigned char attempt;
117 unsigned char cnt;
118};
119#define PCC_INTERVAL_US 100000
120#define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
121#define PCC_P3_THRESHOLD 3*1024*1024
122#define PCC_P2_THRESHOLD 800
123#define PCC_INTR_THRESHOLD 800
124#define PCC_TX_TO 333
125#define PCC_TX_CNT 8
126
127/*
128 * TX/RX Descriptors
129 *
130 * TX/RX Ring DESC Count Must be multiple of 16
131 * RX Ring DESC Count Must be <= 1024
132 */
133#define RING_DESC_ALIGN 16 /* Descriptor alignment */
134
135#define TX_DESC_SIZE 16
136#define TX_RING_NR 8
137#define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
138
139struct txdesc {
140 union {
141 __u8 all[16];
142 __u32 dw[4];
143 struct {
144 /* DW0 */
145 __u16 vlan;
146 __u8 rsv1;
147 __u8 flags;
148
149 /* DW1 */
150 __u16 datalen;
151 __u16 mss;
152
153 /* DW2 */
154 __u16 pktsize;
155 __u16 rsv2;
156
157 /* DW3 */
158 __u32 bufaddr;
159 } desc1;
160 struct {
161 /* DW0 */
162 __u16 rsv1;
163 __u8 rsv2;
164 __u8 flags;
165
166 /* DW1 */
167 __u16 datalen;
168 __u16 rsv3;
169
170 /* DW2 */
171 __u32 bufaddrh;
172
173 /* DW3 */
174 __u32 bufaddrl;
175 } desc2;
176 struct {
177 /* DW0 */
178 __u8 ehdrsz;
179 __u8 rsv1;
180 __u8 rsv2;
181 __u8 flags;
182
183 /* DW1 */
184 __u16 trycnt;
185 __u16 segcnt;
186
187 /* DW2 */
188 __u16 pktsz;
189 __u16 rsv3;
190
191 /* DW3 */
192 __u32 bufaddrl;
193 } descwb;
194 };
195};
196enum jme_txdesc_flags_bits {
197 TXFLAG_OWN = 0x80,
198 TXFLAG_INT = 0x40,
199 TXFLAG_64BIT = 0x20,
200 TXFLAG_TCPCS = 0x10,
201 TXFLAG_UDPCS = 0x08,
202 TXFLAG_IPCS = 0x04,
203 TXFLAG_LSEN = 0x02,
204 TXFLAG_TAGON = 0x01,
205};
206#define TXDESC_MSS_SHIFT 2
207enum jme_rxdescwb_flags_bits {
208 TXWBFLAG_OWN = 0x80,
209 TXWBFLAG_INT = 0x40,
210 TXWBFLAG_TMOUT = 0x20,
211 TXWBFLAG_TRYOUT = 0x10,
212 TXWBFLAG_COL = 0x08,
213
214 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
215 TXWBFLAG_TRYOUT |
216 TXWBFLAG_COL,
217};
218
219
220#define RX_DESC_SIZE 16
221#define RX_RING_NR 4
222#define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
223
224#define RX_BUF_DMA_ALIGN 8
225#define RX_PREPAD_SIZE 10
226#define ETH_CRC_LEN 2
227#define RX_VLANHDR_LEN 2
228#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
229 ETH_HLEN + \
230 ETH_CRC_LEN + \
231 RX_VLANHDR_LEN + \
232 RX_BUF_DMA_ALIGN)
233
234struct rxdesc {
235 union {
236 __u8 all[16];
237 __le32 dw[4];
238 struct {
239 /* DW0 */
240 __le16 rsv2;
241 __u8 rsv1;
242 __u8 flags;
243
244 /* DW1 */
245 __le16 datalen;
246 __le16 wbcpl;
247
248 /* DW2 */
249 __le32 bufaddrh;
250
251 /* DW3 */
252 __le32 bufaddrl;
253 } desc1;
254 struct {
255 /* DW0 */
256 __le16 vlan;
257 __le16 flags;
258
259 /* DW1 */
260 __le16 framesize;
261 __u8 errstat;
262 __u8 desccnt;
263
264 /* DW2 */
265 __le32 rsshash;
266
267 /* DW3 */
268 __u8 hashfun;
269 __u8 hashtype;
270 __le16 resrv;
271 } descwb;
272 };
273};
274enum jme_rxdesc_flags_bits {
275 RXFLAG_OWN = 0x80,
276 RXFLAG_INT = 0x40,
277 RXFLAG_64BIT = 0x20,
278};
279enum jme_rxwbdesc_flags_bits {
280 RXWBFLAG_OWN = 0x8000,
281 RXWBFLAG_INT = 0x4000,
282 RXWBFLAG_MF = 0x2000,
283 RXWBFLAG_64BIT = 0x2000,
284 RXWBFLAG_TCPON = 0x1000,
285 RXWBFLAG_UDPON = 0x0800,
286 RXWBFLAG_IPCS = 0x0400,
287 RXWBFLAG_TCPCS = 0x0200,
288 RXWBFLAG_UDPCS = 0x0100,
289 RXWBFLAG_TAGON = 0x0080,
290 RXWBFLAG_IPV4 = 0x0040,
291 RXWBFLAG_IPV6 = 0x0020,
292 RXWBFLAG_PAUSE = 0x0010,
293 RXWBFLAG_MAGIC = 0x0008,
294 RXWBFLAG_WAKEUP = 0x0004,
295 RXWBFLAG_DEST = 0x0003,
296 RXWBFLAG_DEST_UNI = 0x0001,
297 RXWBFLAG_DEST_MUL = 0x0002,
298 RXWBFLAG_DEST_BRO = 0x0003,
299};
300enum jme_rxwbdesc_desccnt_mask {
301 RXWBDCNT_WBCPL = 0x80,
302 RXWBDCNT_DCNT = 0x7F,
303};
304enum jme_rxwbdesc_errstat_bits {
305 RXWBERR_LIMIT = 0x80,
306 RXWBERR_MIIER = 0x40,
307 RXWBERR_NIBON = 0x20,
308 RXWBERR_COLON = 0x10,
309 RXWBERR_ABORT = 0x08,
310 RXWBERR_SHORT = 0x04,
311 RXWBERR_OVERUN = 0x02,
312 RXWBERR_CRCERR = 0x01,
313 RXWBERR_ALLERR = 0xFF,
314};
315
316struct jme_buffer_info {
317 struct sk_buff *skb;
318 dma_addr_t mapping;
319 int len;
320 int nr_desc;
321};
322
323#define MAX_RING_DESC_NR 1024
324struct jme_ring {
325 void* alloc; /* pointer to allocated memory */
326 volatile void* desc; /* pointer to ring memory */
327 dma_addr_t dmaalloc; /* phys address of ring alloc */
328 dma_addr_t dma; /* phys address for ring dma */
329
330 /* Buffer information corresponding to each descriptor */
331 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
332
333 int next_to_use;
334 int next_to_clean;
335
336 atomic_t nr_free;
337};
338
339#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
340#define NET_STAT(priv) priv->stats
341#define NETDEV_GET_STATS(netdev, fun_ptr) \
342 netdev->get_stats = fun_ptr
343#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
344#else
345#define NET_STAT(priv) priv->dev->stats
346#define NETDEV_GET_STATS(netdev, fun_ptr)
347#define DECLARE_NET_DEVICE_STATS
348#endif
349
350/*
351 * Jmac Adapter Private data
352 */
353#define SHADOW_REG_NR 8
354struct jme_adapter {
355 struct pci_dev *pdev;
356 struct net_device *dev;
357 void __iomem *regs;
358 dma_addr_t shadow_dma;
359 __u32 *shadow_regs;
360 struct mii_if_info mii_if;
361 struct jme_ring rxring[RX_RING_NR];
362 struct jme_ring txring[TX_RING_NR];
363 spinlock_t phy_lock;
364 spinlock_t macaddr_lock;
365 spinlock_t rxmcs_lock;
366 struct tasklet_struct rxempty_task;
367 struct tasklet_struct rxclean_task;
368 struct tasklet_struct txclean_task;
369 struct tasklet_struct linkch_task;
370 struct tasklet_struct pcc_task;
371 __u32 flags;
372 __u32 reg_txcs;
373 __u32 reg_txpfc;
374 __u32 reg_rxcs;
375 __u32 reg_rxmcs;
376 __u32 reg_ghc;
377 __u32 reg_pmcs;
378 __u32 phylink;
379 __u32 tx_ring_size;
380 __u32 tx_ring_mask;
381 __u32 tx_wake_threshold;
382 __u32 rx_ring_size;
383 __u32 rx_ring_mask;
384 __u8 mrrs;
385 struct ethtool_cmd old_ecmd;
386 unsigned int old_mtu;
387 struct vlan_group* vlgrp;
388 struct dynpcc_info dpi;
389 atomic_t intr_sem;
390 atomic_t link_changing;
391 atomic_t tx_cleaning;
392 atomic_t rx_cleaning;
393 atomic_t rx_empty;
394 struct napi_struct napi;
395 DECLARE_NET_DEVICE_STATS
396};
397enum shadow_reg_val {
398 SHADOW_IEVE = 0,
399};
400enum jme_flags_bits {
401 JME_FLAG_MSI = 0x00000001,
402 JME_FLAG_SSET = 0x00000002,
403 JME_FLAG_TXCSUM = 0x00000004,
404 JME_FLAG_TSO = 0x00000008,
405 JME_FLAG_POLL = 0x00000010,
406};
407#define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
408#define TX_TIMEOUT (5*HZ)
409
410
411/*
412 * MMaped I/O Resters
413 */
414enum jme_iomap_offsets {
415 JME_MAC = 0x0000,
416 JME_PHY = 0x0400,
417 JME_MISC = 0x0800,
418 JME_RSS = 0x0C00,
419};
420
421enum jme_iomap_lens {
422 JME_MAC_LEN = 0x80,
423 JME_PHY_LEN = 0x58,
424 JME_MISC_LEN = 0x98,
425 JME_RSS_LEN = 0xFF,
426};
427
428enum jme_iomap_regs {
429 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
430 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
431 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
432 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
433 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
434 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
435 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
436 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
437
438 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
439 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
440 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
441 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
442 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
443 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
444 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
445 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
446 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
447 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
448 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
449 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
450
451 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
452 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
453 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
454
455
456 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
457 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
458 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
459
460
461 JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */
462 JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */
463 JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */
464 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
465 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
466 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
467 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
468 JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
469 JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */
470 JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */
471 JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */
472 JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */
473};
474
475/*
476 * TX Control/Status Bits
477 */
478enum jme_txcs_bits {
479 TXCS_QUEUE7S = 0x00008000,
480 TXCS_QUEUE6S = 0x00004000,
481 TXCS_QUEUE5S = 0x00002000,
482 TXCS_QUEUE4S = 0x00001000,
483 TXCS_QUEUE3S = 0x00000800,
484 TXCS_QUEUE2S = 0x00000400,
485 TXCS_QUEUE1S = 0x00000200,
486 TXCS_QUEUE0S = 0x00000100,
487 TXCS_FIFOTH = 0x000000C0,
488 TXCS_DMASIZE = 0x00000030,
489 TXCS_BURST = 0x00000004,
490 TXCS_ENABLE = 0x00000001,
491};
492enum jme_txcs_value {
493 TXCS_FIFOTH_16QW = 0x000000C0,
494 TXCS_FIFOTH_12QW = 0x00000080,
495 TXCS_FIFOTH_8QW = 0x00000040,
496 TXCS_FIFOTH_4QW = 0x00000000,
497
498 TXCS_DMASIZE_64B = 0x00000000,
499 TXCS_DMASIZE_128B = 0x00000010,
500 TXCS_DMASIZE_256B = 0x00000020,
501 TXCS_DMASIZE_512B = 0x00000030,
502
503 TXCS_SELECT_QUEUE0 = 0x00000000,
504 TXCS_SELECT_QUEUE1 = 0x00010000,
505 TXCS_SELECT_QUEUE2 = 0x00020000,
506 TXCS_SELECT_QUEUE3 = 0x00030000,
507 TXCS_SELECT_QUEUE4 = 0x00040000,
508 TXCS_SELECT_QUEUE5 = 0x00050000,
509 TXCS_SELECT_QUEUE6 = 0x00060000,
510 TXCS_SELECT_QUEUE7 = 0x00070000,
511
512 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
513 TXCS_BURST,
514};
515#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
516
517/*
518 * TX MAC Control/Status Bits
519 */
520enum jme_txmcs_bit_masks {
521 TXMCS_IFG2 = 0xC0000000,
522 TXMCS_IFG1 = 0x30000000,
523 TXMCS_TTHOLD = 0x00000300,
524 TXMCS_FBURST = 0x00000080,
525 TXMCS_CARRIEREXT = 0x00000040,
526 TXMCS_DEFER = 0x00000020,
527 TXMCS_BACKOFF = 0x00000010,
528 TXMCS_CARRIERSENSE = 0x00000008,
529 TXMCS_COLLISION = 0x00000004,
530 TXMCS_CRC = 0x00000002,
531 TXMCS_PADDING = 0x00000001,
532};
533enum jme_txmcs_values {
534 TXMCS_IFG2_6_4 = 0x00000000,
535 TXMCS_IFG2_8_5 = 0x40000000,
536 TXMCS_IFG2_10_6 = 0x80000000,
537 TXMCS_IFG2_12_7 = 0xC0000000,
538
539 TXMCS_IFG1_8_4 = 0x00000000,
540 TXMCS_IFG1_12_6 = 0x10000000,
541 TXMCS_IFG1_16_8 = 0x20000000,
542 TXMCS_IFG1_20_10 = 0x30000000,
543
544 TXMCS_TTHOLD_1_8 = 0x00000000,
545 TXMCS_TTHOLD_1_4 = 0x00000100,
546 TXMCS_TTHOLD_1_2 = 0x00000200,
547 TXMCS_TTHOLD_FULL = 0x00000300,
548
549 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
550 TXMCS_IFG1_16_8 |
551 TXMCS_TTHOLD_FULL |
552 TXMCS_DEFER |
553 TXMCS_CRC |
554 TXMCS_PADDING,
555};
556
557enum jme_txpfc_bits_masks {
558 TXPFC_VLAN_TAG = 0xFFFF0000,
559 TXPFC_VLAN_EN = 0x00008000,
560 TXPFC_PF_EN = 0x00000001,
561};
562
563enum jme_txtrhd_bits_masks {
564 TXTRHD_TXPEN = 0x80000000,
565 TXTRHD_TXP = 0x7FFFFF00,
566 TXTRHD_TXREN = 0x00000080,
567 TXTRHD_TXRL = 0x0000007F,
568};
569enum jme_txtrhd_shifts {
570 TXTRHD_TXP_SHIFT = 8,
571 TXTRHD_TXRL_SHIFT = 0,
572};
573
574
575/*
576 * RX Control/Status Bits
577 */
578enum jme_rxcs_bit_masks {
579 /* FIFO full threshold for transmitting Tx Pause Packet */
580 RXCS_FIFOTHTP = 0x30000000,
581 /* FIFO threshold for processing next packet */
582 RXCS_FIFOTHNP = 0x0C000000,
583 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
584 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
585 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
586 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
587 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
588 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
589 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
590 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
591 RXCS_QST = 0x00000004, /* Receive queue start */
592 RXCS_SUSPEND = 0x00000002,
593 RXCS_ENABLE = 0x00000001,
594};
595enum jme_rxcs_values {
596 RXCS_FIFOTHTP_16T = 0x00000000,
597 RXCS_FIFOTHTP_32T = 0x10000000,
598 RXCS_FIFOTHTP_64T = 0x20000000,
599 RXCS_FIFOTHTP_128T = 0x30000000,
600
601 RXCS_FIFOTHNP_16QW = 0x00000000,
602 RXCS_FIFOTHNP_32QW = 0x04000000,
603 RXCS_FIFOTHNP_64QW = 0x08000000,
604 RXCS_FIFOTHNP_128QW = 0x0C000000,
605
606 RXCS_DMAREQSZ_16B = 0x00000000,
607 RXCS_DMAREQSZ_32B = 0x01000000,
608 RXCS_DMAREQSZ_64B = 0x02000000,
609 RXCS_DMAREQSZ_128B = 0x03000000,
610
611 RXCS_QUEUESEL_Q0 = 0x00000000,
612 RXCS_QUEUESEL_Q1 = 0x00010000,
613 RXCS_QUEUESEL_Q2 = 0x00020000,
614 RXCS_QUEUESEL_Q3 = 0x00030000,
615
616 RXCS_RETRYGAP_256ns = 0x00000000,
617 RXCS_RETRYGAP_512ns = 0x00001000,
618 RXCS_RETRYGAP_1024ns = 0x00002000,
619 RXCS_RETRYGAP_2048ns = 0x00003000,
620 RXCS_RETRYGAP_4096ns = 0x00004000,
621 RXCS_RETRYGAP_8192ns = 0x00005000,
622 RXCS_RETRYGAP_16384ns = 0x00006000,
623 RXCS_RETRYGAP_32768ns = 0x00007000,
624
625 RXCS_RETRYCNT_0 = 0x00000000,
626 RXCS_RETRYCNT_4 = 0x00000100,
627 RXCS_RETRYCNT_8 = 0x00000200,
628 RXCS_RETRYCNT_12 = 0x00000300,
629 RXCS_RETRYCNT_16 = 0x00000400,
630 RXCS_RETRYCNT_20 = 0x00000500,
631 RXCS_RETRYCNT_24 = 0x00000600,
632 RXCS_RETRYCNT_28 = 0x00000700,
633 RXCS_RETRYCNT_32 = 0x00000800,
634 RXCS_RETRYCNT_36 = 0x00000900,
635 RXCS_RETRYCNT_40 = 0x00000A00,
636 RXCS_RETRYCNT_44 = 0x00000B00,
637 RXCS_RETRYCNT_48 = 0x00000C00,
638 RXCS_RETRYCNT_52 = 0x00000D00,
639 RXCS_RETRYCNT_56 = 0x00000E00,
640 RXCS_RETRYCNT_60 = 0x00000F00,
641
642 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
643 RXCS_FIFOTHNP_128QW |
644 RXCS_DMAREQSZ_128B |
645 RXCS_RETRYGAP_256ns |
646 RXCS_RETRYCNT_32,
647};
648#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
649
650/*
651 * RX MAC Control/Status Bits
652 */
653enum jme_rxmcs_bits {
654 RXMCS_ALLFRAME = 0x00000800,
655 RXMCS_BRDFRAME = 0x00000400,
656 RXMCS_MULFRAME = 0x00000200,
657 RXMCS_UNIFRAME = 0x00000100,
658 RXMCS_ALLMULFRAME = 0x00000080,
659 RXMCS_MULFILTERED = 0x00000040,
660 RXMCS_RXCOLLDEC = 0x00000020,
661 RXMCS_FLOWCTRL = 0x00000008,
662 RXMCS_VTAGRM = 0x00000004,
663 RXMCS_PREPAD = 0x00000002,
664 RXMCS_CHECKSUM = 0x00000001,
665
666 RXMCS_DEFAULT = RXMCS_VTAGRM |
667 RXMCS_PREPAD |
668 RXMCS_FLOWCTRL |
669 RXMCS_CHECKSUM,
670};
671
672/*
673 * Wakeup Frame setup interface registers
674 */
675#define WAKEUP_FRAME_NR 8
676#define WAKEUP_FRAME_MASK_DWNR 4
677enum jme_wfoi_bit_masks {
678 WFOI_MASK_SEL = 0x00000070,
679 WFOI_CRC_SEL = 0x00000008,
680 WFOI_FRAME_SEL = 0x00000007,
681};
682enum jme_wfoi_shifts {
683 WFOI_MASK_SHIFT = 4,
684};
685
686/*
687 * SMI Related definitions
688 */
689enum jme_smi_bit_mask
690{
691 SMI_DATA_MASK = 0xFFFF0000,
692 SMI_REG_ADDR_MASK = 0x0000F800,
693 SMI_PHY_ADDR_MASK = 0x000007C0,
694 SMI_OP_WRITE = 0x00000020,
695 /* Set to 1, after req done it'll be cleared to 0 */
696 SMI_OP_REQ = 0x00000010,
697 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
698 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
699 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
700 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
701};
702enum jme_smi_bit_shift
703{
704 SMI_DATA_SHIFT = 16,
705 SMI_REG_ADDR_SHIFT = 11,
706 SMI_PHY_ADDR_SHIFT = 6,
707};
708__always_inline __u32 smi_reg_addr(int x)
709{
710 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
711}
712__always_inline __u32 smi_phy_addr(int x)
713{
714 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
715}
716#define JME_PHY_TIMEOUT 1000 /* 1000 usec */
717
718/*
719 * Global Host Control
720 */
721enum jme_ghc_bit_mask {
722 GHC_SWRST = 0x40000000,
723 GHC_DPX = 0x00000040,
724 GHC_SPEED = 0x00000030,
725 GHC_LINK_POLL = 0x00000001,
726};
727enum jme_ghc_speed_val {
728 GHC_SPEED_10M = 0x00000010,
729 GHC_SPEED_100M = 0x00000020,
730 GHC_SPEED_1000M = 0x00000030,
731};
732
733/*
734 * Power management control and status register
735 */
736enum jme_pmcs_bit_masks {
737 PMCS_WF7DET = 0x80000000,
738 PMCS_WF6DET = 0x40000000,
739 PMCS_WF5DET = 0x20000000,
740 PMCS_WF4DET = 0x10000000,
741 PMCS_WF3DET = 0x08000000,
742 PMCS_WF2DET = 0x04000000,
743 PMCS_WF1DET = 0x02000000,
744 PMCS_WF0DET = 0x01000000,
745 PMCS_LFDET = 0x00040000,
746 PMCS_LRDET = 0x00020000,
747 PMCS_MFDET = 0x00010000,
748 PMCS_WF7EN = 0x00008000,
749 PMCS_WF6EN = 0x00004000,
750 PMCS_WF5EN = 0x00002000,
751 PMCS_WF4EN = 0x00001000,
752 PMCS_WF3EN = 0x00000800,
753 PMCS_WF2EN = 0x00000400,
754 PMCS_WF1EN = 0x00000200,
755 PMCS_WF0EN = 0x00000100,
756 PMCS_LFEN = 0x00000004,
757 PMCS_LREN = 0x00000002,
758 PMCS_MFEN = 0x00000001,
759};
760
761/*
762 * Giga PHY Status Registers
763 */
764enum jme_phy_link_bit_mask {
765 PHY_LINK_SPEED_MASK = 0x0000C000,
766 PHY_LINK_DUPLEX = 0x00002000,
767 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
768 PHY_LINK_UP = 0x00000400,
769 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
770 PHY_LINK_MDI_STAT = 0x00000040,
771};
772enum jme_phy_link_speed_val {
773 PHY_LINK_SPEED_10M = 0x00000000,
774 PHY_LINK_SPEED_100M = 0x00004000,
775 PHY_LINK_SPEED_1000M = 0x00008000,
776};
777#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
778
779/*
780 * SMB Control and Status
781 */
782enum jme_smbcsr_bit_mask {
783 SMBCSR_CNACK = 0x00020000,
784 SMBCSR_RELOAD = 0x00010000,
785 SMBCSR_EEPROMD = 0x00000020,
786};
787#define JME_SMB_TIMEOUT 10 /* 10 msec */
788
789/*
790 * Timer Control/Status Register
791 */
792enum jme_tmcsr_bit_masks {
793 TMCSR_SWIT = 0x80000000,
794 TMCSR_EN = 0x01000000,
795 TMCSR_CNT = 0x00FFFFFF,
796};
797
798
799/*
800 * General Purpost REG-0
801 */
802enum jme_gpreg0_masks {
803 GPREG0_DISSH = 0xFF000000,
804 GPREG0_PCIRLMT = 0x00300000,
805 GPREG0_PCCNOMUTCLR = 0x00040000,
806 GPREG0_PCCTMR = 0x00000300,
807 GPREG0_PHYADDR = 0x0000001F,
808};
809enum jme_gpreg0_vals {
810 GPREG0_DISSH_DW7 = 0x80000000,
811 GPREG0_DISSH_DW6 = 0x40000000,
812 GPREG0_DISSH_DW5 = 0x20000000,
813 GPREG0_DISSH_DW4 = 0x10000000,
814 GPREG0_DISSH_DW3 = 0x08000000,
815 GPREG0_DISSH_DW2 = 0x04000000,
816 GPREG0_DISSH_DW1 = 0x02000000,
817 GPREG0_DISSH_DW0 = 0x01000000,
818 GPREG0_DISSH_ALL = 0xFF000000,
819
820 GPREG0_PCIRLMT_8 = 0x00000000,
821 GPREG0_PCIRLMT_6 = 0x00100000,
822 GPREG0_PCIRLMT_5 = 0x00200000,
823 GPREG0_PCIRLMT_4 = 0x00300000,
824
825 GPREG0_PCCTMR_16ns = 0x00000000,
826 GPREG0_PCCTMR_256ns = 0x00000100,
827 GPREG0_PCCTMR_1us = 0x00000200,
828 GPREG0_PCCTMR_1ms = 0x00000300,
829
830 GPREG0_PHYADDR_1 = 0x00000001,
831
832 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
833 GPREG0_PCCNOMUTCLR |
834 GPREG0_PCCTMR_1us |
835 GPREG0_PHYADDR_1,
836};
837
838/*
839 * Interrupt Status Bits
840 */
841enum jme_interrupt_bits
842{
843 INTR_SWINTR = 0x80000000,
844 INTR_TMINTR = 0x40000000,
845 INTR_LINKCH = 0x20000000,
846 INTR_PAUSERCV = 0x10000000,
847 INTR_MAGICRCV = 0x08000000,
848 INTR_WAKERCV = 0x04000000,
849 INTR_PCCRX0TO = 0x02000000,
850 INTR_PCCRX1TO = 0x01000000,
851 INTR_PCCRX2TO = 0x00800000,
852 INTR_PCCRX3TO = 0x00400000,
853 INTR_PCCTXTO = 0x00200000,
854 INTR_PCCRX0 = 0x00100000,
855 INTR_PCCRX1 = 0x00080000,
856 INTR_PCCRX2 = 0x00040000,
857 INTR_PCCRX3 = 0x00020000,
858 INTR_PCCTX = 0x00010000,
859 INTR_RX3EMP = 0x00008000,
860 INTR_RX2EMP = 0x00004000,
861 INTR_RX1EMP = 0x00002000,
862 INTR_RX0EMP = 0x00001000,
863 INTR_RX3 = 0x00000800,
864 INTR_RX2 = 0x00000400,
865 INTR_RX1 = 0x00000200,
866 INTR_RX0 = 0x00000100,
867 INTR_TX7 = 0x00000080,
868 INTR_TX6 = 0x00000040,
869 INTR_TX5 = 0x00000020,
870 INTR_TX4 = 0x00000010,
871 INTR_TX3 = 0x00000008,
872 INTR_TX2 = 0x00000004,
873 INTR_TX1 = 0x00000002,
874 INTR_TX0 = 0x00000001,
875};
876static const __u32 INTR_ENABLE = INTR_SWINTR |
877 INTR_TMINTR |
878 INTR_LINKCH |
879 INTR_RX0EMP |
880 INTR_PCCRX0TO |
881 INTR_PCCRX0 |
882 INTR_PCCTXTO |
883 INTR_PCCTX;
884
885/*
886 * PCC Control Registers
887 */
888enum jme_pccrx_masks {
889 PCCRXTO_MASK = 0xFFFF0000,
890 PCCRX_MASK = 0x0000FF00,
891};
892enum jme_pcctx_masks {
893 PCCTXTO_MASK = 0xFFFF0000,
894 PCCTX_MASK = 0x0000FF00,
895 PCCTX_QS_MASK = 0x000000FF,
896};
897enum jme_pccrx_shifts {
898 PCCRXTO_SHIFT = 16,
899 PCCRX_SHIFT = 8,
900};
901enum jme_pcctx_shifts {
902 PCCTXTO_SHIFT = 16,
903 PCCTX_SHIFT = 8,
904};
905enum jme_pcctx_bits {
906 PCCTXQ0_EN = 0x00000001,
907 PCCTXQ1_EN = 0x00000002,
908 PCCTXQ2_EN = 0x00000004,
909 PCCTXQ3_EN = 0x00000008,
910 PCCTXQ4_EN = 0x00000010,
911 PCCTXQ5_EN = 0x00000020,
912 PCCTXQ6_EN = 0x00000040,
913 PCCTXQ7_EN = 0x00000080,
914};
915
916
917/*
918 * Shadow base address register bits
919 */
920enum jme_shadow_base_address_bits {
921 SHBA_POSTEN = 0x1,
922};
923
924/*
925 * Read/Write MMaped I/O Registers
926 */
927__always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
928{
929 return le32_to_cpu(readl((__u8*)jme->regs + reg));
930}
931__always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
932{
933 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
934}
935__always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
936{
937 /*
938 * Read after write should cause flush
939 */
940 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
941 readl((__u8*)jme->regs + reg);
942}
943
944/*
945 * Function prototypes for ethtool
946 */
947static void jme_get_drvinfo(struct net_device *netdev,
948 struct ethtool_drvinfo *info);
949static int jme_get_settings(struct net_device *netdev,
950 struct ethtool_cmd *ecmd);
951static int jme_set_settings(struct net_device *netdev,
952 struct ethtool_cmd *ecmd);
953static u32 jme_get_link(struct net_device *netdev);
954
955
956/*
957 * Function prototypes for netdev
958 */
959static int jme_open(struct net_device *netdev);
960static int jme_close(struct net_device *netdev);
961static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
962static int jme_set_macaddr(struct net_device *netdev, void *p);
963static void jme_set_multi(struct net_device *netdev);
964
965
JMicron Ethernet Linux driver