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drivers/net: Remove alloc_etherdev error messages
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#ifndef __JME_H_INCLUDED__
26#define __JME_H_INCLUDED__
27#include <linux/interrupt.h>
28
29#define DRV_NAME "jme"
30#define DRV_VERSION "1.0.8.2-jmmod"
31#define PFX DRV_NAME ": "
32
33#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34#define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35
36/*
37 * Message related definitions
38 */
39#define JME_DEF_MSG_ENABLE \
40 (NETIF_MSG_PROBE | \
41 NETIF_MSG_LINK | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR | \
44 NETIF_MSG_HW)
45
46#ifndef pr_err
47#define pr_err(fmt, arg...) \
48 printk(KERN_ERR fmt, ##arg)
49#endif
50#ifndef netdev_err
51#define netdev_err(netdev, fmt, arg...) \
52 pr_err(fmt, ##arg)
53#endif
54
55#ifdef TX_DEBUG
56#define tx_dbg(priv, fmt, args...) \
57 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
58#else
59#define tx_dbg(priv, fmt, args...) \
60do { \
61 if (0) \
62 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
63} while (0)
64#endif
65
66#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
67#define jme_msg(msglvl, type, priv, fmt, args...) \
68 if (netif_msg_##type(priv)) \
69 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
70
71#define msg_probe(priv, fmt, args...) \
72 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
73
74#define msg_link(priv, fmt, args...) \
75 jme_msg(KERN_INFO, link, priv, fmt, ## args)
76
77#define msg_intr(priv, fmt, args...) \
78 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
79
80#define msg_rx_err(priv, fmt, args...) \
81 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
82
83#define msg_rx_status(priv, fmt, args...) \
84 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
85
86#define msg_tx_err(priv, fmt, args...) \
87 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
88
89#define msg_tx_done(priv, fmt, args...) \
90 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
91
92#define msg_tx_queued(priv, fmt, args...) \
93 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
94
95#define msg_hw(priv, fmt, args...) \
96 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
97
98#ifndef netif_info
99#define netif_info(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
101#endif
102#ifndef netif_err
103#define netif_err(priv, type, dev, fmt, args...) \
104 msg_ ## type(priv, fmt, ## args)
105#endif
106#endif
107
108#ifndef NETIF_F_TSO6
109#define NETIF_F_TSO6 0
110#endif
111#ifndef NETIF_F_IPV6_CSUM
112#define NETIF_F_IPV6_CSUM 0
113#endif
114
115#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
116#define __USE_NDO_FIX_FEATURES__
117#endif
118
119#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,1,0)
120#define __UNIFY_VLAN_RX_PATH__
121#define __USE_NDO_SET_RX_MODE__
122#endif
123
124#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
125#define __USE_SKB_FRAG_API__
126#endif
127
128#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)
129#define __NEW_FIX_FEATURES_TYPE__
130#endif
131
132/*
133 * Extra PCI Configuration space interface
134 */
135#define PCI_DCSR_MRRS 0x59
136#define PCI_DCSR_MRRS_MASK 0x70
137
138enum pci_dcsr_mrrs_vals {
139 MRRS_128B = 0x00,
140 MRRS_256B = 0x10,
141 MRRS_512B = 0x20,
142 MRRS_1024B = 0x30,
143 MRRS_2048B = 0x40,
144 MRRS_4096B = 0x50,
145};
146
147#define PCI_SPI 0xB0
148
149enum pci_spi_bits {
150 SPI_EN = 0x10,
151 SPI_MISO = 0x08,
152 SPI_MOSI = 0x04,
153 SPI_SCLK = 0x02,
154 SPI_CS = 0x01,
155};
156
157struct jme_spi_op {
158 void __user *uwbuf;
159 void __user *urbuf;
160 __u8 wn; /* Number of write actions */
161 __u8 rn; /* Number of read actions */
162 __u8 bitn; /* Number of bits per action */
163 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
164 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
165
166 /* Internal use only */
167 u8 *kwbuf;
168 u8 *krbuf;
169 u8 sr;
170 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
171};
172
173enum jme_spi_op_bits {
174 SPI_MODE_CPHA = 0x01,
175 SPI_MODE_CPOL = 0x02,
176 SPI_MODE_DUP = 0x80,
177};
178
179#define HALF_US 500 /* 500 ns */
180
181#define PCI_PRIV_PE1 0xE4
182
183enum pci_priv_pe1_bit_masks {
184 PE1_ASPMSUPRT = 0x00000003, /*
185 * RW:
186 * Aspm_support[1:0]
187 * (R/W Port of 5C[11:10])
188 */
189 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
190 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
191 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
192 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
193 PE1_GPREG0 = 0x0000FF00, /*
194 * SRW:
195 * Cfg_gp_reg0
196 * [7:6] phy_giga BG control
197 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
198 * [4:0] Reserved
199 */
200 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
201 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
202 PE1_REVID = 0xFF000000, /* RO: Rev ID */
203};
204
205enum pci_priv_pe1_values {
206 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
207 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
208 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
209 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
210};
211
212/*
213 * Dynamic(adaptive)/Static PCC values
214 */
215enum dynamic_pcc_values {
216 PCC_OFF = 0,
217 PCC_P1 = 1,
218 PCC_P2 = 2,
219 PCC_P3 = 3,
220
221 PCC_OFF_TO = 0,
222 PCC_P1_TO = 1,
223 PCC_P2_TO = 64,
224 PCC_P3_TO = 128,
225
226 PCC_OFF_CNT = 0,
227 PCC_P1_CNT = 1,
228 PCC_P2_CNT = 16,
229 PCC_P3_CNT = 32,
230};
231struct dynpcc_info {
232 unsigned long last_bytes;
233 unsigned long last_pkts;
234 unsigned long intr_cnt;
235 unsigned char cur;
236 unsigned char attempt;
237 unsigned char cnt;
238};
239#define PCC_INTERVAL_US 100000
240#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
241#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
242#define PCC_P2_THRESHOLD 800
243#define PCC_INTR_THRESHOLD 800
244#define PCC_TX_TO 1000
245#define PCC_TX_CNT 8
246
247/*
248 * TX/RX Descriptors
249 *
250 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
251 */
252#define RING_DESC_ALIGN 16 /* Descriptor alignment */
253#define TX_DESC_SIZE 16
254#define TX_RING_NR 8
255#define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
256
257struct txdesc {
258 union {
259 __u8 all[16];
260 __le32 dw[4];
261 struct {
262 /* DW0 */
263 __le16 vlan;
264 __u8 rsv1;
265 __u8 flags;
266
267 /* DW1 */
268 __le16 datalen;
269 __le16 mss;
270
271 /* DW2 */
272 __le16 pktsize;
273 __le16 rsv2;
274
275 /* DW3 */
276 __le32 bufaddr;
277 } desc1;
278 struct {
279 /* DW0 */
280 __le16 rsv1;
281 __u8 rsv2;
282 __u8 flags;
283
284 /* DW1 */
285 __le16 datalen;
286 __le16 rsv3;
287
288 /* DW2 */
289 __le32 bufaddrh;
290
291 /* DW3 */
292 __le32 bufaddrl;
293 } desc2;
294 struct {
295 /* DW0 */
296 __u8 ehdrsz;
297 __u8 rsv1;
298 __u8 rsv2;
299 __u8 flags;
300
301 /* DW1 */
302 __le16 trycnt;
303 __le16 segcnt;
304
305 /* DW2 */
306 __le16 pktsz;
307 __le16 rsv3;
308
309 /* DW3 */
310 __le32 bufaddrl;
311 } descwb;
312 };
313};
314
315enum jme_txdesc_flags_bits {
316 TXFLAG_OWN = 0x80,
317 TXFLAG_INT = 0x40,
318 TXFLAG_64BIT = 0x20,
319 TXFLAG_TCPCS = 0x10,
320 TXFLAG_UDPCS = 0x08,
321 TXFLAG_IPCS = 0x04,
322 TXFLAG_LSEN = 0x02,
323 TXFLAG_TAGON = 0x01,
324};
325
326#define TXDESC_MSS_SHIFT 2
327enum jme_txwbdesc_flags_bits {
328 TXWBFLAG_OWN = 0x80,
329 TXWBFLAG_INT = 0x40,
330 TXWBFLAG_TMOUT = 0x20,
331 TXWBFLAG_TRYOUT = 0x10,
332 TXWBFLAG_COL = 0x08,
333
334 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
335 TXWBFLAG_TRYOUT |
336 TXWBFLAG_COL,
337};
338
339#define RX_DESC_SIZE 16
340#define RX_RING_NR 4
341#define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
342#define RX_BUF_DMA_ALIGN 8
343#define RX_PREPAD_SIZE 10
344#define ETH_CRC_LEN 2
345#define RX_VLANHDR_LEN 2
346#define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
347 ETH_HLEN + \
348 ETH_CRC_LEN + \
349 RX_VLANHDR_LEN + \
350 RX_BUF_DMA_ALIGN)
351
352struct rxdesc {
353 union {
354 __u8 all[16];
355 __le32 dw[4];
356 struct {
357 /* DW0 */
358 __le16 rsv2;
359 __u8 rsv1;
360 __u8 flags;
361
362 /* DW1 */
363 __le16 datalen;
364 __le16 wbcpl;
365
366 /* DW2 */
367 __le32 bufaddrh;
368
369 /* DW3 */
370 __le32 bufaddrl;
371 } desc1;
372 struct {
373 /* DW0 */
374 __le16 vlan;
375 __le16 flags;
376
377 /* DW1 */
378 __le16 framesize;
379 __u8 errstat;
380 __u8 desccnt;
381
382 /* DW2 */
383 __le32 rsshash;
384
385 /* DW3 */
386 __u8 hashfun;
387 __u8 hashtype;
388 __le16 resrv;
389 } descwb;
390 };
391};
392
393enum jme_rxdesc_flags_bits {
394 RXFLAG_OWN = 0x80,
395 RXFLAG_INT = 0x40,
396 RXFLAG_64BIT = 0x20,
397};
398
399enum jme_rxwbdesc_flags_bits {
400 RXWBFLAG_OWN = 0x8000,
401 RXWBFLAG_INT = 0x4000,
402 RXWBFLAG_MF = 0x2000,
403 RXWBFLAG_64BIT = 0x2000,
404 RXWBFLAG_TCPON = 0x1000,
405 RXWBFLAG_UDPON = 0x0800,
406 RXWBFLAG_IPCS = 0x0400,
407 RXWBFLAG_TCPCS = 0x0200,
408 RXWBFLAG_UDPCS = 0x0100,
409 RXWBFLAG_TAGON = 0x0080,
410 RXWBFLAG_IPV4 = 0x0040,
411 RXWBFLAG_IPV6 = 0x0020,
412 RXWBFLAG_PAUSE = 0x0010,
413 RXWBFLAG_MAGIC = 0x0008,
414 RXWBFLAG_WAKEUP = 0x0004,
415 RXWBFLAG_DEST = 0x0003,
416 RXWBFLAG_DEST_UNI = 0x0001,
417 RXWBFLAG_DEST_MUL = 0x0002,
418 RXWBFLAG_DEST_BRO = 0x0003,
419};
420
421enum jme_rxwbdesc_desccnt_mask {
422 RXWBDCNT_WBCPL = 0x80,
423 RXWBDCNT_DCNT = 0x7F,
424};
425
426enum jme_rxwbdesc_errstat_bits {
427 RXWBERR_LIMIT = 0x80,
428 RXWBERR_MIIER = 0x40,
429 RXWBERR_NIBON = 0x20,
430 RXWBERR_COLON = 0x10,
431 RXWBERR_ABORT = 0x08,
432 RXWBERR_SHORT = 0x04,
433 RXWBERR_OVERUN = 0x02,
434 RXWBERR_CRCERR = 0x01,
435 RXWBERR_ALLERR = 0xFF,
436};
437
438/*
439 * Buffer information corresponding to ring descriptors.
440 */
441struct jme_buffer_info {
442 struct sk_buff *skb;
443 dma_addr_t mapping;
444 int len;
445 int nr_desc;
446 unsigned long start_xmit;
447};
448
449/*
450 * The structure holding buffer information and ring descriptors all together.
451 */
452struct jme_ring {
453 void *alloc; /* pointer to allocated memory */
454 void *desc; /* pointer to ring memory */
455 dma_addr_t dmaalloc; /* phys address of ring alloc */
456 dma_addr_t dma; /* phys address for ring dma */
457
458 /* Buffer information corresponding to each descriptor */
459 struct jme_buffer_info *bufinf;
460
461 int next_to_use;
462 atomic_t next_to_clean;
463 atomic_t nr_free;
464};
465
466#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
467#define false 0
468#define true 0
469#define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
470#define PCI_VENDOR_ID_JMICRON 0x197B
471#endif
472
473#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
474#define PCI_VDEVICE(vendor, device) \
475 PCI_VENDOR_ID_##vendor, (device), \
476 PCI_ANY_ID, PCI_ANY_ID, 0, 0
477#endif
478
479#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
480#define NET_STAT(priv) priv->stats
481#define NETDEV_GET_STATS(netdev, fun_ptr) \
482 netdev->get_stats = fun_ptr
483#define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
484/*
485 * CentOS 5.2 have *_hdr helpers back-ported
486 */
487#ifdef RHEL_RELEASE_CODE
488#if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
489#define __DEFINE_IPHDR_HELPERS__
490#endif
491#else
492#define __DEFINE_IPHDR_HELPERS__
493#endif
494#else
495#define NET_STAT(priv) (priv->dev->stats)
496#define NETDEV_GET_STATS(netdev, fun_ptr)
497#define DECLARE_NET_DEVICE_STATS
498#endif
499
500#ifdef __DEFINE_IPHDR_HELPERS__
501static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
502{
503 return skb->nh.iph;
504}
505
506static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
507{
508 return skb->nh.ipv6h;
509}
510
511static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
512{
513 return skb->h.th;
514}
515#endif
516
517#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
518#define DECLARE_NAPI_STRUCT
519#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
520 dev->poll = pollfn; \
521 dev->weight = q;
522#define JME_NAPI_HOLDER(holder) struct net_device *holder
523#define JME_NAPI_WEIGHT(w) int *w
524#define JME_NAPI_WEIGHT_VAL(w) *w
525#define JME_NAPI_WEIGHT_SET(w, r) *w = r
526#define DECLARE_NETDEV struct net_device *netdev = jme->dev;
527#define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
528#define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
529#define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
530#define JME_RX_SCHEDULE_PREP(priv) \
531 netif_rx_schedule_prep(priv->dev)
532#define JME_RX_SCHEDULE(priv) \
533 __netif_rx_schedule(priv->dev);
534#else
535#define DECLARE_NAPI_STRUCT struct napi_struct napi;
536#define NETIF_NAPI_SET(dev, napis, pollfn, q) \
537 netif_napi_add(dev, napis, pollfn, q);
538#define JME_NAPI_HOLDER(holder) struct napi_struct *holder
539#define JME_NAPI_WEIGHT(w) int w
540#define JME_NAPI_WEIGHT_VAL(w) w
541#define JME_NAPI_WEIGHT_SET(w, r)
542#define DECLARE_NETDEV
543#define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
544#define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
545#define JME_NAPI_DISABLE(priv) \
546 if (!napi_disable_pending(&priv->napi)) \
547 napi_disable(&priv->napi);
548#define JME_RX_SCHEDULE_PREP(priv) \
549 napi_schedule_prep(&priv->napi)
550#define JME_RX_SCHEDULE(priv) \
551 __napi_schedule(&priv->napi);
552#endif
553
554#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
555#define JME_NEW_PM_API
556#endif
557
558#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26)
559static inline __u32 ethtool_cmd_speed(struct ethtool_cmd *ep)
560{
561 return ep->speed;
562}
563#endif
564
565/*
566 * Jmac Adapter Private data
567 */
568struct jme_adapter {
569 struct pci_dev *pdev;
570 struct net_device *dev;
571 void __iomem *regs;
572 struct mii_if_info mii_if;
573 struct jme_ring rxring[RX_RING_NR];
574 struct jme_ring txring[TX_RING_NR];
575 spinlock_t phy_lock;
576 spinlock_t macaddr_lock;
577 spinlock_t rxmcs_lock;
578 struct tasklet_struct rxempty_task;
579 struct tasklet_struct rxclean_task;
580 struct tasklet_struct txclean_task;
581 struct tasklet_struct linkch_task;
582 struct tasklet_struct pcc_task;
583 unsigned long flags;
584 u32 reg_txcs;
585 u32 reg_txpfc;
586 u32 reg_rxcs;
587 u32 reg_rxmcs;
588 u32 reg_ghc;
589 u32 reg_pmcs;
590 u32 reg_gpreg1;
591 u32 phylink;
592 u32 tx_ring_size;
593 u32 tx_ring_mask;
594 u32 tx_wake_threshold;
595 u32 rx_ring_size;
596 u32 rx_ring_mask;
597 u8 mrrs;
598 unsigned int fpgaver;
599 u8 chiprev;
600 u8 chip_main_rev;
601 u8 chip_sub_rev;
602 u8 pcirev;
603 u32 msg_enable;
604 struct ethtool_cmd old_ecmd;
605 unsigned int old_mtu;
606#ifndef __UNIFY_VLAN_RX_PATH__
607 struct vlan_group *vlgrp;
608#endif
609 struct dynpcc_info dpi;
610 atomic_t intr_sem;
611 atomic_t link_changing;
612 atomic_t tx_cleaning;
613 atomic_t rx_cleaning;
614 atomic_t rx_empty;
615 int (*jme_rx)(struct sk_buff *skb);
616#ifndef __UNIFY_VLAN_RX_PATH__
617 int (*jme_vlan_rx)(struct sk_buff *skb,
618 struct vlan_group *grp,
619 unsigned short vlan_tag);
620#endif
621 DECLARE_NAPI_STRUCT
622 DECLARE_NET_DEVICE_STATS
623};
624
625#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
626static struct net_device_stats *
627jme_get_stats(struct net_device *netdev)
628{
629 struct jme_adapter *jme = netdev_priv(netdev);
630 return &jme->stats;
631}
632#endif
633
634enum jme_flags_bits {
635 JME_FLAG_MSI = 1,
636 JME_FLAG_SSET = 2,
637#ifndef __USE_NDO_FIX_FEATURES__
638 JME_FLAG_TXCSUM = 3,
639 JME_FLAG_TSO = 4,
640#endif
641 JME_FLAG_POLL = 5,
642 JME_FLAG_SHUTDOWN = 6,
643};
644
645#define TX_TIMEOUT (5 * HZ)
646#define JME_REG_LEN 0x500
647#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
648
649#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
650static inline struct jme_adapter*
651jme_napi_priv(struct net_device *holder)
652{
653 struct jme_adapter *jme;
654 jme = netdev_priv(holder);
655 return jme;
656}
657#else
658static inline struct jme_adapter*
659jme_napi_priv(struct napi_struct *napi)
660{
661 struct jme_adapter *jme;
662 jme = container_of(napi, struct jme_adapter, napi);
663 return jme;
664}
665#endif
666
667/*
668 * MMaped I/O Resters
669 */
670enum jme_iomap_offsets {
671 JME_MAC = 0x0000,
672 JME_PHY = 0x0400,
673 JME_MISC = 0x0800,
674 JME_RSS = 0x0C00,
675};
676
677enum jme_iomap_lens {
678 JME_MAC_LEN = 0x80,
679 JME_PHY_LEN = 0x58,
680 JME_MISC_LEN = 0x98,
681 JME_RSS_LEN = 0xFF,
682};
683
684enum jme_iomap_regs {
685 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
686 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
687 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
688 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
689 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
690 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
691 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
692 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
693
694 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
695 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
696 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
697 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
698 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
699 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
700 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
701 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
702 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
703 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
704 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
705 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
706
707 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
708 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
709 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
710
711
712 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
713 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
714 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
715 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
716 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
717
718
719 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
720 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
721 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
722 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
723 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
724 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
725 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
726 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
727 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
728 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
729 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
730 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
731 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
732 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
733 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
734 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
735};
736
737/*
738 * TX Control/Status Bits
739 */
740enum jme_txcs_bits {
741 TXCS_QUEUE7S = 0x00008000,
742 TXCS_QUEUE6S = 0x00004000,
743 TXCS_QUEUE5S = 0x00002000,
744 TXCS_QUEUE4S = 0x00001000,
745 TXCS_QUEUE3S = 0x00000800,
746 TXCS_QUEUE2S = 0x00000400,
747 TXCS_QUEUE1S = 0x00000200,
748 TXCS_QUEUE0S = 0x00000100,
749 TXCS_FIFOTH = 0x000000C0,
750 TXCS_DMASIZE = 0x00000030,
751 TXCS_BURST = 0x00000004,
752 TXCS_ENABLE = 0x00000001,
753};
754
755enum jme_txcs_value {
756 TXCS_FIFOTH_16QW = 0x000000C0,
757 TXCS_FIFOTH_12QW = 0x00000080,
758 TXCS_FIFOTH_8QW = 0x00000040,
759 TXCS_FIFOTH_4QW = 0x00000000,
760
761 TXCS_DMASIZE_64B = 0x00000000,
762 TXCS_DMASIZE_128B = 0x00000010,
763 TXCS_DMASIZE_256B = 0x00000020,
764 TXCS_DMASIZE_512B = 0x00000030,
765
766 TXCS_SELECT_QUEUE0 = 0x00000000,
767 TXCS_SELECT_QUEUE1 = 0x00010000,
768 TXCS_SELECT_QUEUE2 = 0x00020000,
769 TXCS_SELECT_QUEUE3 = 0x00030000,
770 TXCS_SELECT_QUEUE4 = 0x00040000,
771 TXCS_SELECT_QUEUE5 = 0x00050000,
772 TXCS_SELECT_QUEUE6 = 0x00060000,
773 TXCS_SELECT_QUEUE7 = 0x00070000,
774
775 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
776 TXCS_BURST,
777};
778
779#define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
780
781/*
782 * TX MAC Control/Status Bits
783 */
784enum jme_txmcs_bit_masks {
785 TXMCS_IFG2 = 0xC0000000,
786 TXMCS_IFG1 = 0x30000000,
787 TXMCS_TTHOLD = 0x00000300,
788 TXMCS_FBURST = 0x00000080,
789 TXMCS_CARRIEREXT = 0x00000040,
790 TXMCS_DEFER = 0x00000020,
791 TXMCS_BACKOFF = 0x00000010,
792 TXMCS_CARRIERSENSE = 0x00000008,
793 TXMCS_COLLISION = 0x00000004,
794 TXMCS_CRC = 0x00000002,
795 TXMCS_PADDING = 0x00000001,
796};
797
798enum jme_txmcs_values {
799 TXMCS_IFG2_6_4 = 0x00000000,
800 TXMCS_IFG2_8_5 = 0x40000000,
801 TXMCS_IFG2_10_6 = 0x80000000,
802 TXMCS_IFG2_12_7 = 0xC0000000,
803
804 TXMCS_IFG1_8_4 = 0x00000000,
805 TXMCS_IFG1_12_6 = 0x10000000,
806 TXMCS_IFG1_16_8 = 0x20000000,
807 TXMCS_IFG1_20_10 = 0x30000000,
808
809 TXMCS_TTHOLD_1_8 = 0x00000000,
810 TXMCS_TTHOLD_1_4 = 0x00000100,
811 TXMCS_TTHOLD_1_2 = 0x00000200,
812 TXMCS_TTHOLD_FULL = 0x00000300,
813
814 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
815 TXMCS_IFG1_16_8 |
816 TXMCS_TTHOLD_FULL |
817 TXMCS_DEFER |
818 TXMCS_CRC |
819 TXMCS_PADDING,
820};
821
822enum jme_txpfc_bits_masks {
823 TXPFC_VLAN_TAG = 0xFFFF0000,
824 TXPFC_VLAN_EN = 0x00008000,
825 TXPFC_PF_EN = 0x00000001,
826};
827
828enum jme_txtrhd_bits_masks {
829 TXTRHD_TXPEN = 0x80000000,
830 TXTRHD_TXP = 0x7FFFFF00,
831 TXTRHD_TXREN = 0x00000080,
832 TXTRHD_TXRL = 0x0000007F,
833};
834
835enum jme_txtrhd_shifts {
836 TXTRHD_TXP_SHIFT = 8,
837 TXTRHD_TXRL_SHIFT = 0,
838};
839
840enum jme_txtrhd_values {
841 TXTRHD_FULLDUPLEX = 0x00000000,
842 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
843 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
844 TXTRHD_TXREN |
845 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
846};
847
848/*
849 * RX Control/Status Bits
850 */
851enum jme_rxcs_bit_masks {
852 /* FIFO full threshold for transmitting Tx Pause Packet */
853 RXCS_FIFOTHTP = 0x30000000,
854 /* FIFO threshold for processing next packet */
855 RXCS_FIFOTHNP = 0x0C000000,
856 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
857 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
858 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
859 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
860 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
861 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
862 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
863 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
864 RXCS_QST = 0x00000004, /* Receive queue start */
865 RXCS_SUSPEND = 0x00000002,
866 RXCS_ENABLE = 0x00000001,
867};
868
869enum jme_rxcs_values {
870 RXCS_FIFOTHTP_16T = 0x00000000,
871 RXCS_FIFOTHTP_32T = 0x10000000,
872 RXCS_FIFOTHTP_64T = 0x20000000,
873 RXCS_FIFOTHTP_128T = 0x30000000,
874
875 RXCS_FIFOTHNP_16QW = 0x00000000,
876 RXCS_FIFOTHNP_32QW = 0x04000000,
877 RXCS_FIFOTHNP_64QW = 0x08000000,
878 RXCS_FIFOTHNP_128QW = 0x0C000000,
879
880 RXCS_DMAREQSZ_16B = 0x00000000,
881 RXCS_DMAREQSZ_32B = 0x01000000,
882 RXCS_DMAREQSZ_64B = 0x02000000,
883 RXCS_DMAREQSZ_128B = 0x03000000,
884
885 RXCS_QUEUESEL_Q0 = 0x00000000,
886 RXCS_QUEUESEL_Q1 = 0x00010000,
887 RXCS_QUEUESEL_Q2 = 0x00020000,
888 RXCS_QUEUESEL_Q3 = 0x00030000,
889
890 RXCS_RETRYGAP_256ns = 0x00000000,
891 RXCS_RETRYGAP_512ns = 0x00001000,
892 RXCS_RETRYGAP_1024ns = 0x00002000,
893 RXCS_RETRYGAP_2048ns = 0x00003000,
894 RXCS_RETRYGAP_4096ns = 0x00004000,
895 RXCS_RETRYGAP_8192ns = 0x00005000,
896 RXCS_RETRYGAP_16384ns = 0x00006000,
897 RXCS_RETRYGAP_32768ns = 0x00007000,
898
899 RXCS_RETRYCNT_0 = 0x00000000,
900 RXCS_RETRYCNT_4 = 0x00000100,
901 RXCS_RETRYCNT_8 = 0x00000200,
902 RXCS_RETRYCNT_12 = 0x00000300,
903 RXCS_RETRYCNT_16 = 0x00000400,
904 RXCS_RETRYCNT_20 = 0x00000500,
905 RXCS_RETRYCNT_24 = 0x00000600,
906 RXCS_RETRYCNT_28 = 0x00000700,
907 RXCS_RETRYCNT_32 = 0x00000800,
908 RXCS_RETRYCNT_36 = 0x00000900,
909 RXCS_RETRYCNT_40 = 0x00000A00,
910 RXCS_RETRYCNT_44 = 0x00000B00,
911 RXCS_RETRYCNT_48 = 0x00000C00,
912 RXCS_RETRYCNT_52 = 0x00000D00,
913 RXCS_RETRYCNT_56 = 0x00000E00,
914 RXCS_RETRYCNT_60 = 0x00000F00,
915
916 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
917 RXCS_FIFOTHNP_128QW |
918 RXCS_DMAREQSZ_128B |
919 RXCS_RETRYGAP_256ns |
920 RXCS_RETRYCNT_32,
921};
922
923#define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
924
925/*
926 * RX MAC Control/Status Bits
927 */
928enum jme_rxmcs_bits {
929 RXMCS_ALLFRAME = 0x00000800,
930 RXMCS_BRDFRAME = 0x00000400,
931 RXMCS_MULFRAME = 0x00000200,
932 RXMCS_UNIFRAME = 0x00000100,
933 RXMCS_ALLMULFRAME = 0x00000080,
934 RXMCS_MULFILTERED = 0x00000040,
935 RXMCS_RXCOLLDEC = 0x00000020,
936 RXMCS_FLOWCTRL = 0x00000008,
937 RXMCS_VTAGRM = 0x00000004,
938 RXMCS_PREPAD = 0x00000002,
939 RXMCS_CHECKSUM = 0x00000001,
940
941 RXMCS_DEFAULT = RXMCS_VTAGRM |
942 RXMCS_PREPAD |
943 RXMCS_FLOWCTRL |
944 RXMCS_CHECKSUM,
945};
946
947/* Extern PHY common register 2 */
948
949#define PHY_GAD_TEST_MODE_1 0x00002000
950#define PHY_GAD_TEST_MODE_MSK 0x0000E000
951#define JM_PHY_SPEC_REG_READ 0x00004000
952#define JM_PHY_SPEC_REG_WRITE 0x00008000
953#define PHY_CALIBRATION_DELAY 20
954#define JM_PHY_SPEC_ADDR_REG 0x1E
955#define JM_PHY_SPEC_DATA_REG 0x1F
956
957#define JM_PHY_EXT_COMM_0_REG 0x30
958#define JM_PHY_EXT_COMM_1_REG 0x31
959#define JM_PHY_EXT_COMM_2_REG 0x32
960#define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01
961#define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02
962#define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10
963#define PCI_PRIV_SHARE_NICCTRL 0xF5
964#define JME_FLAG_PHYEA_ENABLE 0x2
965
966/*
967 * Wakeup Frame setup interface registers
968 */
969#define WAKEUP_FRAME_NR 8
970#define WAKEUP_FRAME_MASK_DWNR 4
971
972enum jme_wfoi_bit_masks {
973 WFOI_MASK_SEL = 0x00000070,
974 WFOI_CRC_SEL = 0x00000008,
975 WFOI_FRAME_SEL = 0x00000007,
976};
977
978enum jme_wfoi_shifts {
979 WFOI_MASK_SHIFT = 4,
980};
981
982/*
983 * SMI Related definitions
984 */
985enum jme_smi_bit_mask {
986 SMI_DATA_MASK = 0xFFFF0000,
987 SMI_REG_ADDR_MASK = 0x0000F800,
988 SMI_PHY_ADDR_MASK = 0x000007C0,
989 SMI_OP_WRITE = 0x00000020,
990 /* Set to 1, after req done it'll be cleared to 0 */
991 SMI_OP_REQ = 0x00000010,
992 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
993 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
994 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
995 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
996};
997
998enum jme_smi_bit_shift {
999 SMI_DATA_SHIFT = 16,
1000 SMI_REG_ADDR_SHIFT = 11,
1001 SMI_PHY_ADDR_SHIFT = 6,
1002};
1003
1004static inline u32 smi_reg_addr(int x)
1005{
1006 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
1007}
1008
1009static inline u32 smi_phy_addr(int x)
1010{
1011 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
1012}
1013
1014#define JME_PHY_TIMEOUT 100 /* 100 msec */
1015#define JME_PHY_REG_NR 32
1016
1017/*
1018 * Global Host Control
1019 */
1020enum jme_ghc_bit_mask {
1021 GHC_SWRST = 0x40000000,
1022 GHC_TO_CLK_SRC = 0x00C00000,
1023 GHC_TXMAC_CLK_SRC = 0x00300000,
1024 GHC_DPX = 0x00000040,
1025 GHC_SPEED = 0x00000030,
1026 GHC_LINK_POLL = 0x00000001,
1027};
1028
1029enum jme_ghc_speed_val {
1030 GHC_SPEED_10M = 0x00000010,
1031 GHC_SPEED_100M = 0x00000020,
1032 GHC_SPEED_1000M = 0x00000030,
1033};
1034
1035enum jme_ghc_to_clk {
1036 GHC_TO_CLK_OFF = 0x00000000,
1037 GHC_TO_CLK_GPHY = 0x00400000,
1038 GHC_TO_CLK_PCIE = 0x00800000,
1039 GHC_TO_CLK_INVALID = 0x00C00000,
1040};
1041
1042enum jme_ghc_txmac_clk {
1043 GHC_TXMAC_CLK_OFF = 0x00000000,
1044 GHC_TXMAC_CLK_GPHY = 0x00100000,
1045 GHC_TXMAC_CLK_PCIE = 0x00200000,
1046 GHC_TXMAC_CLK_INVALID = 0x00300000,
1047};
1048
1049/*
1050 * Power management control and status register
1051 */
1052enum jme_pmcs_bit_masks {
1053 PMCS_STMASK = 0xFFFF0000,
1054 PMCS_WF7DET = 0x80000000,
1055 PMCS_WF6DET = 0x40000000,
1056 PMCS_WF5DET = 0x20000000,
1057 PMCS_WF4DET = 0x10000000,
1058 PMCS_WF3DET = 0x08000000,
1059 PMCS_WF2DET = 0x04000000,
1060 PMCS_WF1DET = 0x02000000,
1061 PMCS_WF0DET = 0x01000000,
1062 PMCS_LFDET = 0x00040000,
1063 PMCS_LRDET = 0x00020000,
1064 PMCS_MFDET = 0x00010000,
1065 PMCS_ENMASK = 0x0000FFFF,
1066 PMCS_WF7EN = 0x00008000,
1067 PMCS_WF6EN = 0x00004000,
1068 PMCS_WF5EN = 0x00002000,
1069 PMCS_WF4EN = 0x00001000,
1070 PMCS_WF3EN = 0x00000800,
1071 PMCS_WF2EN = 0x00000400,
1072 PMCS_WF1EN = 0x00000200,
1073 PMCS_WF0EN = 0x00000100,
1074 PMCS_LFEN = 0x00000004,
1075 PMCS_LREN = 0x00000002,
1076 PMCS_MFEN = 0x00000001,
1077};
1078
1079/*
1080 * New PHY Power Control Register
1081 */
1082enum jme_phy_pwr_bit_masks {
1083 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1084 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1085 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1086 PHY_PWR_CLKSEL = 0x08000000, /*
1087 * XTL_OUT Clock select
1088 * (an internal free-running clock)
1089 * 0: xtl_out = phy_giga.A_XTL25_O
1090 * 1: xtl_out = phy_giga.PD_OSC
1091 */
1092};
1093
1094/*
1095 * Giga PHY Status Registers
1096 */
1097enum jme_phy_link_bit_mask {
1098 PHY_LINK_SPEED_MASK = 0x0000C000,
1099 PHY_LINK_DUPLEX = 0x00002000,
1100 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1101 PHY_LINK_UP = 0x00000400,
1102 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
1103 PHY_LINK_MDI_STAT = 0x00000040,
1104};
1105
1106enum jme_phy_link_speed_val {
1107 PHY_LINK_SPEED_10M = 0x00000000,
1108 PHY_LINK_SPEED_100M = 0x00004000,
1109 PHY_LINK_SPEED_1000M = 0x00008000,
1110};
1111
1112#define JME_SPDRSV_TIMEOUT 500 /* 500 us */
1113
1114/*
1115 * SMB Control and Status
1116 */
1117enum jme_smbcsr_bit_mask {
1118 SMBCSR_CNACK = 0x00020000,
1119 SMBCSR_RELOAD = 0x00010000,
1120 SMBCSR_EEPROMD = 0x00000020,
1121 SMBCSR_INITDONE = 0x00000010,
1122 SMBCSR_BUSY = 0x0000000F,
1123};
1124
1125enum jme_smbintf_bit_mask {
1126 SMBINTF_HWDATR = 0xFF000000,
1127 SMBINTF_HWDATW = 0x00FF0000,
1128 SMBINTF_HWADDR = 0x0000FF00,
1129 SMBINTF_HWRWN = 0x00000020,
1130 SMBINTF_HWCMD = 0x00000010,
1131 SMBINTF_FASTM = 0x00000008,
1132 SMBINTF_GPIOSCL = 0x00000004,
1133 SMBINTF_GPIOSDA = 0x00000002,
1134 SMBINTF_GPIOEN = 0x00000001,
1135};
1136
1137enum jme_smbintf_vals {
1138 SMBINTF_HWRWN_READ = 0x00000020,
1139 SMBINTF_HWRWN_WRITE = 0x00000000,
1140};
1141
1142enum jme_smbintf_shifts {
1143 SMBINTF_HWDATR_SHIFT = 24,
1144 SMBINTF_HWDATW_SHIFT = 16,
1145 SMBINTF_HWADDR_SHIFT = 8,
1146};
1147
1148#define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1149#define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1150#define JME_SMB_LEN 256
1151#define JME_EEPROM_MAGIC 0x250
1152
1153/*
1154 * Timer Control/Status Register
1155 */
1156enum jme_tmcsr_bit_masks {
1157 TMCSR_SWIT = 0x80000000,
1158 TMCSR_EN = 0x01000000,
1159 TMCSR_CNT = 0x00FFFFFF,
1160};
1161
1162/*
1163 * General Purpose REG-0
1164 */
1165enum jme_gpreg0_masks {
1166 GPREG0_DISSH = 0xFF000000,
1167 GPREG0_PCIRLMT = 0x00300000,
1168 GPREG0_PCCNOMUTCLR = 0x00040000,
1169 GPREG0_LNKINTPOLL = 0x00001000,
1170 GPREG0_PCCTMR = 0x00000300,
1171 GPREG0_PHYADDR = 0x0000001F,
1172};
1173
1174enum jme_gpreg0_vals {
1175 GPREG0_DISSH_DW7 = 0x80000000,
1176 GPREG0_DISSH_DW6 = 0x40000000,
1177 GPREG0_DISSH_DW5 = 0x20000000,
1178 GPREG0_DISSH_DW4 = 0x10000000,
1179 GPREG0_DISSH_DW3 = 0x08000000,
1180 GPREG0_DISSH_DW2 = 0x04000000,
1181 GPREG0_DISSH_DW1 = 0x02000000,
1182 GPREG0_DISSH_DW0 = 0x01000000,
1183 GPREG0_DISSH_ALL = 0xFF000000,
1184
1185 GPREG0_PCIRLMT_8 = 0x00000000,
1186 GPREG0_PCIRLMT_6 = 0x00100000,
1187 GPREG0_PCIRLMT_5 = 0x00200000,
1188 GPREG0_PCIRLMT_4 = 0x00300000,
1189
1190 GPREG0_PCCTMR_16ns = 0x00000000,
1191 GPREG0_PCCTMR_256ns = 0x00000100,
1192 GPREG0_PCCTMR_1us = 0x00000200,
1193 GPREG0_PCCTMR_1ms = 0x00000300,
1194
1195 GPREG0_PHYADDR_1 = 0x00000001,
1196
1197 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1198 GPREG0_PCCTMR_1us |
1199 GPREG0_PHYADDR_1,
1200};
1201
1202/*
1203 * General Purpose REG-1
1204 */
1205enum jme_gpreg1_bit_masks {
1206 GPREG1_RXCLKOFF = 0x04000000,
1207 GPREG1_PCREQN = 0x00020000,
1208 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1209 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1210 GPREG1_INTRDELAYUNIT = 0x00000018,
1211 GPREG1_INTRDELAYENABLE = 0x00000007,
1212};
1213
1214enum jme_gpreg1_vals {
1215 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1216 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1217 GPREG1_INTDLYUNIT_1US = 0x00000010,
1218 GPREG1_INTDLYUNIT_16US = 0x00000018,
1219
1220 GPREG1_INTDLYEN_1U = 0x00000001,
1221 GPREG1_INTDLYEN_2U = 0x00000002,
1222 GPREG1_INTDLYEN_3U = 0x00000003,
1223 GPREG1_INTDLYEN_4U = 0x00000004,
1224 GPREG1_INTDLYEN_5U = 0x00000005,
1225 GPREG1_INTDLYEN_6U = 0x00000006,
1226 GPREG1_INTDLYEN_7U = 0x00000007,
1227
1228 GPREG1_DEFAULT = GPREG1_PCREQN,
1229};
1230
1231/*
1232 * Interrupt Status Bits
1233 */
1234enum jme_interrupt_bits {
1235 INTR_SWINTR = 0x80000000,
1236 INTR_TMINTR = 0x40000000,
1237 INTR_LINKCH = 0x20000000,
1238 INTR_PAUSERCV = 0x10000000,
1239 INTR_MAGICRCV = 0x08000000,
1240 INTR_WAKERCV = 0x04000000,
1241 INTR_PCCRX0TO = 0x02000000,
1242 INTR_PCCRX1TO = 0x01000000,
1243 INTR_PCCRX2TO = 0x00800000,
1244 INTR_PCCRX3TO = 0x00400000,
1245 INTR_PCCTXTO = 0x00200000,
1246 INTR_PCCRX0 = 0x00100000,
1247 INTR_PCCRX1 = 0x00080000,
1248 INTR_PCCRX2 = 0x00040000,
1249 INTR_PCCRX3 = 0x00020000,
1250 INTR_PCCTX = 0x00010000,
1251 INTR_RX3EMP = 0x00008000,
1252 INTR_RX2EMP = 0x00004000,
1253 INTR_RX1EMP = 0x00002000,
1254 INTR_RX0EMP = 0x00001000,
1255 INTR_RX3 = 0x00000800,
1256 INTR_RX2 = 0x00000400,
1257 INTR_RX1 = 0x00000200,
1258 INTR_RX0 = 0x00000100,
1259 INTR_TX7 = 0x00000080,
1260 INTR_TX6 = 0x00000040,
1261 INTR_TX5 = 0x00000020,
1262 INTR_TX4 = 0x00000010,
1263 INTR_TX3 = 0x00000008,
1264 INTR_TX2 = 0x00000004,
1265 INTR_TX1 = 0x00000002,
1266 INTR_TX0 = 0x00000001,
1267};
1268
1269static const u32 INTR_ENABLE = INTR_SWINTR |
1270 INTR_TMINTR |
1271 INTR_LINKCH |
1272 INTR_PCCRX0TO |
1273 INTR_PCCRX0 |
1274 INTR_PCCTXTO |
1275 INTR_PCCTX |
1276 INTR_RX0EMP;
1277
1278/*
1279 * PCC Control Registers
1280 */
1281enum jme_pccrx_masks {
1282 PCCRXTO_MASK = 0xFFFF0000,
1283 PCCRX_MASK = 0x0000FF00,
1284};
1285
1286enum jme_pcctx_masks {
1287 PCCTXTO_MASK = 0xFFFF0000,
1288 PCCTX_MASK = 0x0000FF00,
1289 PCCTX_QS_MASK = 0x000000FF,
1290};
1291
1292enum jme_pccrx_shifts {
1293 PCCRXTO_SHIFT = 16,
1294 PCCRX_SHIFT = 8,
1295};
1296
1297enum jme_pcctx_shifts {
1298 PCCTXTO_SHIFT = 16,
1299 PCCTX_SHIFT = 8,
1300};
1301
1302enum jme_pcctx_bits {
1303 PCCTXQ0_EN = 0x00000001,
1304 PCCTXQ1_EN = 0x00000002,
1305 PCCTXQ2_EN = 0x00000004,
1306 PCCTXQ3_EN = 0x00000008,
1307 PCCTXQ4_EN = 0x00000010,
1308 PCCTXQ5_EN = 0x00000020,
1309 PCCTXQ6_EN = 0x00000040,
1310 PCCTXQ7_EN = 0x00000080,
1311};
1312
1313/*
1314 * Chip Mode Register
1315 */
1316enum jme_chipmode_bit_masks {
1317 CM_FPGAVER_MASK = 0xFFFF0000,
1318 CM_CHIPREV_MASK = 0x0000FF00,
1319 CM_CHIPMODE_MASK = 0x0000000F,
1320};
1321
1322enum jme_chipmode_shifts {
1323 CM_FPGAVER_SHIFT = 16,
1324 CM_CHIPREV_SHIFT = 8,
1325};
1326
1327/*
1328 * Aggressive Power Mode Control
1329 */
1330enum jme_apmc_bits {
1331 JME_APMC_PCIE_SD_EN = 0x40000000,
1332 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1333 JME_APMC_EPIEN = 0x04000000,
1334 JME_APMC_EPIEN_CTRL = 0x03000000,
1335};
1336
1337enum jme_apmc_values {
1338 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1339 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1340};
1341
1342#define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1343
1344#ifdef REG_DEBUG
1345static char *MAC_REG_NAME[] = {
1346 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1347 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1348 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1349 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1350 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1351 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1352 "JME_PMCS"};
1353
1354static char *PE_REG_NAME[] = {
1355 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1356 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1357 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1358 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1359 "JME_SMBCSR", "JME_SMBINTF"};
1360
1361static char *MISC_REG_NAME[] = {
1362 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1363 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1364 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1365 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1366 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1367 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1368 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1369 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1370 "JME_PCCSRX0"};
1371
1372static inline void reg_dbg(const struct jme_adapter *jme,
1373 const char *msg, u32 val, u32 reg)
1374{
1375 const char *regname;
1376 switch (reg & 0xF00) {
1377 case 0x000:
1378 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1379 break;
1380 case 0x400:
1381 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1382 break;
1383 case 0x800:
1384 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1385 break;
1386 default:
1387 regname = PE_REG_NAME[0];
1388 }
1389 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1390 msg, val, regname);
1391}
1392#else
1393static inline void reg_dbg(const struct jme_adapter *jme,
1394 const char *msg, u32 val, u32 reg) {}
1395#endif
1396
1397/*
1398 * Read/Write MMaped I/O Registers
1399 */
1400static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1401{
1402 return readl(jme->regs + reg);
1403}
1404
1405static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1406{
1407 reg_dbg(jme, "REG WRITE", val, reg);
1408 writel(val, jme->regs + reg);
1409 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1410}
1411
1412static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1413{
1414 /*
1415 * Read after write should cause flush
1416 */
1417 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1418 writel(val, jme->regs + reg);
1419 readl(jme->regs + reg);
1420 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1421}
1422
1423/*
1424 * PHY Regs
1425 */
1426enum jme_phy_reg17_bit_masks {
1427 PREG17_SPEED = 0xC000,
1428 PREG17_DUPLEX = 0x2000,
1429 PREG17_SPDRSV = 0x0800,
1430 PREG17_LNKUP = 0x0400,
1431 PREG17_MDI = 0x0040,
1432};
1433
1434enum jme_phy_reg17_vals {
1435 PREG17_SPEED_10M = 0x0000,
1436 PREG17_SPEED_100M = 0x4000,
1437 PREG17_SPEED_1000M = 0x8000,
1438};
1439
1440#define BMSR_ANCOMP 0x0020
1441
1442/*
1443 * Workaround
1444 */
1445static inline int is_buggy250(unsigned short device, u8 chiprev)
1446{
1447 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1448}
1449
1450static inline int new_phy_power_ctrl(u8 chip_main_rev)
1451{
1452 return chip_main_rev >= 5;
1453}
1454
1455/*
1456 * Function prototypes
1457 */
1458static int jme_set_settings(struct net_device *netdev,
1459 struct ethtool_cmd *ecmd);
1460static void jme_set_unicastaddr(struct net_device *netdev);
1461static void jme_set_multi(struct net_device *netdev);
1462
1463#endif
1464
JMicron Ethernet Linux driver