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jme: Reinit PHY processor after each PHY power on
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67
68read_again:
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
72
73 wmb();
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 udelay(20);
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
78 break;
79 }
80
81 if (i == 0) {
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
83 return 0;
84 }
85
86 if (again--)
87 goto read_again;
88
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90}
91
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
102
103 wmb();
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 break;
108 }
109
110 if (i == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112}
113
114static int
115jme_phyext_read(struct jme_adapter *jme, int reg)
116{
117 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
118 JME_PHY_SPEC_ADDR_REG,
119 JME_PHY_SPEC_REG_READ | (reg & 0x3FFF));
120 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
121 JME_PHY_SPEC_DATA_REG);
122}
123
124static void
125jme_phyext_write(struct jme_adapter *jme, int reg, int val)
126{
127 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
128 JME_PHY_SPEC_DATA_REG, val);
129 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
130 JME_PHY_SPEC_ADDR_REG,
131 JME_PHY_SPEC_REG_WRITE | (reg & 0x3FFF));
132}
133
134static void
135jme_phyext_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
136{
137 int i;
138 u16 *p16 = (u16 *)p;
139
140 for (i = 0 ; i < reg_nr ; ++i)
141 p16[i] = jme_phyext_read(jme, i);
142}
143
144static inline void
145jme_reset_phy_processor(struct jme_adapter *jme)
146{
147 u32 val;
148
149 jme_mdio_write(jme->dev,
150 jme->mii_if.phy_id,
151 MII_ADVERTISE, ADVERTISE_ALL |
152 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
153
154 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
155 jme_mdio_write(jme->dev,
156 jme->mii_if.phy_id,
157 MII_CTRL1000,
158 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
159
160 val = jme_mdio_read(jme->dev,
161 jme->mii_if.phy_id,
162 MII_BMCR);
163
164 jme_mdio_write(jme->dev,
165 jme->mii_if.phy_id,
166 MII_BMCR, val | BMCR_RESET);
167}
168
169static void
170jme_setup_wakeup_frame(struct jme_adapter *jme,
171 const u32 *mask, u32 crc, int fnr)
172{
173 int i;
174
175 /*
176 * Setup CRC pattern
177 */
178 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
179 wmb();
180 jwrite32(jme, JME_WFODP, crc);
181 wmb();
182
183 /*
184 * Setup Mask
185 */
186 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
187 jwrite32(jme, JME_WFOI,
188 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
189 (fnr & WFOI_FRAME_SEL));
190 wmb();
191 jwrite32(jme, JME_WFODP, mask[i]);
192 wmb();
193 }
194}
195
196static inline void
197jme_mac_rxclk_off(struct jme_adapter *jme)
198{
199 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
200 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
201}
202
203static inline void
204jme_mac_rxclk_on(struct jme_adapter *jme)
205{
206 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
207 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
208}
209
210static inline void
211jme_mac_txclk_off(struct jme_adapter *jme)
212{
213 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
215}
216
217static inline void
218jme_mac_txclk_on(struct jme_adapter *jme)
219{
220 u32 speed = jme->reg_ghc & GHC_SPEED;
221 if (speed == GHC_SPEED_1000M)
222 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
223 else
224 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
225 jwrite32f(jme, JME_GHC, jme->reg_ghc);
226}
227
228static inline void
229jme_reset_ghc_speed(struct jme_adapter *jme)
230{
231 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
233}
234
235static inline void
236jme_reset_250A2_workaround(struct jme_adapter *jme)
237{
238 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
239 GPREG1_RSSPATCH);
240 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
241}
242
243static inline void
244jme_assert_ghc_reset(struct jme_adapter *jme)
245{
246 jme->reg_ghc |= GHC_SWRST;
247 jwrite32f(jme, JME_GHC, jme->reg_ghc);
248}
249
250static inline void
251jme_clear_ghc_reset(struct jme_adapter *jme)
252{
253 jme->reg_ghc &= ~GHC_SWRST;
254 jwrite32f(jme, JME_GHC, jme->reg_ghc);
255}
256
257static inline void
258jme_reset_mac_processor(struct jme_adapter *jme)
259{
260 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
261 u32 crc = 0xCDCDCDCD;
262 u32 gpreg0;
263 int i;
264
265 jme_reset_ghc_speed(jme);
266 jme_reset_250A2_workaround(jme);
267
268 jme_mac_rxclk_on(jme);
269 jme_mac_txclk_on(jme);
270 udelay(1);
271 jme_assert_ghc_reset(jme);
272 udelay(1);
273 jme_mac_rxclk_off(jme);
274 jme_mac_txclk_off(jme);
275 udelay(1);
276 jme_clear_ghc_reset(jme);
277 udelay(1);
278 jme_mac_rxclk_on(jme);
279 jme_mac_txclk_on(jme);
280 udelay(1);
281 jme_mac_rxclk_off(jme);
282 jme_mac_txclk_off(jme);
283
284 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
285 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
286 jwrite32(jme, JME_RXQDC, 0x00000000);
287 jwrite32(jme, JME_RXNDA, 0x00000000);
288 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
289 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
290 jwrite32(jme, JME_TXQDC, 0x00000000);
291 jwrite32(jme, JME_TXNDA, 0x00000000);
292
293 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
294 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
295 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
296 jme_setup_wakeup_frame(jme, mask, crc, i);
297 if (jme->fpgaver)
298 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
299 else
300 gpreg0 = GPREG0_DEFAULT;
301 jwrite32(jme, JME_GPREG0, gpreg0);
302}
303
304static inline void
305jme_clear_pm(struct jme_adapter *jme)
306{
307 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
308 pci_set_power_state(jme->pdev, PCI_D0);
309 pci_enable_wake(jme->pdev, PCI_D0, false);
310}
311
312static int
313jme_reload_eeprom(struct jme_adapter *jme)
314{
315 u32 val;
316 int i;
317
318 val = jread32(jme, JME_SMBCSR);
319
320 if (val & SMBCSR_EEPROMD) {
321 val |= SMBCSR_CNACK;
322 jwrite32(jme, JME_SMBCSR, val);
323 val |= SMBCSR_RELOAD;
324 jwrite32(jme, JME_SMBCSR, val);
325 mdelay(12);
326
327 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
328 mdelay(1);
329 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
330 break;
331 }
332
333 if (i == 0) {
334 pr_err("eeprom reload timeout\n");
335 return -EIO;
336 }
337 }
338
339 return 0;
340}
341
342static void
343jme_load_macaddr(struct net_device *netdev)
344{
345 struct jme_adapter *jme = netdev_priv(netdev);
346 unsigned char macaddr[6];
347 u32 val;
348
349 spin_lock_bh(&jme->macaddr_lock);
350 val = jread32(jme, JME_RXUMA_LO);
351 macaddr[0] = (val >> 0) & 0xFF;
352 macaddr[1] = (val >> 8) & 0xFF;
353 macaddr[2] = (val >> 16) & 0xFF;
354 macaddr[3] = (val >> 24) & 0xFF;
355 val = jread32(jme, JME_RXUMA_HI);
356 macaddr[4] = (val >> 0) & 0xFF;
357 macaddr[5] = (val >> 8) & 0xFF;
358 memcpy(netdev->dev_addr, macaddr, 6);
359 spin_unlock_bh(&jme->macaddr_lock);
360}
361
362static inline void
363jme_set_rx_pcc(struct jme_adapter *jme, int p)
364{
365 switch (p) {
366 case PCC_OFF:
367 jwrite32(jme, JME_PCCRX0,
368 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
369 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
370 break;
371 case PCC_P1:
372 jwrite32(jme, JME_PCCRX0,
373 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
374 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
375 break;
376 case PCC_P2:
377 jwrite32(jme, JME_PCCRX0,
378 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
379 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
380 break;
381 case PCC_P3:
382 jwrite32(jme, JME_PCCRX0,
383 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
384 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
385 break;
386 default:
387 break;
388 }
389 wmb();
390
391 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
392 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
393}
394
395static void
396jme_start_irq(struct jme_adapter *jme)
397{
398 register struct dynpcc_info *dpi = &(jme->dpi);
399
400 jme_set_rx_pcc(jme, PCC_P1);
401 dpi->cur = PCC_P1;
402 dpi->attempt = PCC_P1;
403 dpi->cnt = 0;
404
405 jwrite32(jme, JME_PCCTX,
406 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
407 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
408 PCCTXQ0_EN
409 );
410
411 /*
412 * Enable Interrupts
413 */
414 jwrite32(jme, JME_IENS, INTR_ENABLE);
415}
416
417static inline void
418jme_stop_irq(struct jme_adapter *jme)
419{
420 /*
421 * Disable Interrupts
422 */
423 jwrite32f(jme, JME_IENC, INTR_ENABLE);
424}
425
426static u32
427jme_linkstat_from_phy(struct jme_adapter *jme)
428{
429 u32 phylink, bmsr;
430
431 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
432 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
433 if (bmsr & BMSR_ANCOMP)
434 phylink |= PHY_LINK_AUTONEG_COMPLETE;
435
436 return phylink;
437}
438
439static inline void
440jme_set_phyfifo_5level(struct jme_adapter *jme)
441{
442 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
443}
444
445static inline void
446jme_set_phyfifo_8level(struct jme_adapter *jme)
447{
448 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
449}
450
451static int
452jme_check_link(struct net_device *netdev, int testonly)
453{
454 struct jme_adapter *jme = netdev_priv(netdev);
455 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
456 char linkmsg[64];
457 int rc = 0;
458
459 linkmsg[0] = '\0';
460
461 if (jme->fpgaver)
462 phylink = jme_linkstat_from_phy(jme);
463 else
464 phylink = jread32(jme, JME_PHY_LINK);
465
466 if (phylink & PHY_LINK_UP) {
467 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
468 /*
469 * If we did not enable AN
470 * Speed/Duplex Info should be obtained from SMI
471 */
472 phylink = PHY_LINK_UP;
473
474 bmcr = jme_mdio_read(jme->dev,
475 jme->mii_if.phy_id,
476 MII_BMCR);
477
478 phylink |= ((bmcr & BMCR_SPEED1000) &&
479 (bmcr & BMCR_SPEED100) == 0) ?
480 PHY_LINK_SPEED_1000M :
481 (bmcr & BMCR_SPEED100) ?
482 PHY_LINK_SPEED_100M :
483 PHY_LINK_SPEED_10M;
484
485 phylink |= (bmcr & BMCR_FULLDPLX) ?
486 PHY_LINK_DUPLEX : 0;
487
488 strcat(linkmsg, "Forced: ");
489 } else {
490 /*
491 * Keep polling for speed/duplex resolve complete
492 */
493 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
494 --cnt) {
495
496 udelay(1);
497
498 if (jme->fpgaver)
499 phylink = jme_linkstat_from_phy(jme);
500 else
501 phylink = jread32(jme, JME_PHY_LINK);
502 }
503 if (!cnt)
504 pr_err("Waiting speed resolve timeout\n");
505
506 strcat(linkmsg, "ANed: ");
507 }
508
509 if (jme->phylink == phylink) {
510 rc = 1;
511 goto out;
512 }
513 if (testonly)
514 goto out;
515
516 jme->phylink = phylink;
517
518 /*
519 * The speed/duplex setting of jme->reg_ghc already cleared
520 * by jme_reset_mac_processor()
521 */
522 switch (phylink & PHY_LINK_SPEED_MASK) {
523 case PHY_LINK_SPEED_10M:
524 jme->reg_ghc |= GHC_SPEED_10M;
525 strcat(linkmsg, "10 Mbps, ");
526 break;
527 case PHY_LINK_SPEED_100M:
528 jme->reg_ghc |= GHC_SPEED_100M;
529 strcat(linkmsg, "100 Mbps, ");
530 break;
531 case PHY_LINK_SPEED_1000M:
532 jme->reg_ghc |= GHC_SPEED_1000M;
533 strcat(linkmsg, "1000 Mbps, ");
534 break;
535 default:
536 break;
537 }
538
539 if (phylink & PHY_LINK_DUPLEX) {
540 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
541 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
542 jme->reg_ghc |= GHC_DPX;
543 } else {
544 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
545 TXMCS_BACKOFF |
546 TXMCS_CARRIERSENSE |
547 TXMCS_COLLISION);
548 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
549 }
550
551 jwrite32(jme, JME_GHC, jme->reg_ghc);
552
553 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
554 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
555 GPREG1_RSSPATCH);
556 if (!(phylink & PHY_LINK_DUPLEX))
557 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
558 switch (phylink & PHY_LINK_SPEED_MASK) {
559 case PHY_LINK_SPEED_10M:
560 jme_set_phyfifo_8level(jme);
561 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
562 break;
563 case PHY_LINK_SPEED_100M:
564 jme_set_phyfifo_5level(jme);
565 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
566 break;
567 case PHY_LINK_SPEED_1000M:
568 jme_set_phyfifo_8level(jme);
569 break;
570 default:
571 break;
572 }
573 }
574 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
575
576 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
577 "Full-Duplex, " :
578 "Half-Duplex, ");
579 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
580 "MDI-X" :
581 "MDI");
582 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
583 netif_carrier_on(netdev);
584 } else {
585 if (testonly)
586 goto out;
587
588 netif_info(jme, link, jme->dev, "Link is down\n");
589 jme->phylink = 0;
590 netif_carrier_off(netdev);
591 }
592
593out:
594 return rc;
595}
596
597static int
598jme_setup_tx_resources(struct jme_adapter *jme)
599{
600 struct jme_ring *txring = &(jme->txring[0]);
601
602 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
604 &(txring->dmaalloc),
605 GFP_ATOMIC);
606
607 if (!txring->alloc)
608 goto err_set_null;
609
610 /*
611 * 16 Bytes align
612 */
613 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
614 RING_DESC_ALIGN);
615 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
616 txring->next_to_use = 0;
617 atomic_set(&txring->next_to_clean, 0);
618 atomic_set(&txring->nr_free, jme->tx_ring_size);
619
620 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
621 jme->tx_ring_size, GFP_ATOMIC);
622 if (unlikely(!(txring->bufinf)))
623 goto err_free_txring;
624
625 /*
626 * Initialize Transmit Descriptors
627 */
628 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
629 memset(txring->bufinf, 0,
630 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
631
632 return 0;
633
634err_free_txring:
635 dma_free_coherent(&(jme->pdev->dev),
636 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
637 txring->alloc,
638 txring->dmaalloc);
639
640err_set_null:
641 txring->desc = NULL;
642 txring->dmaalloc = 0;
643 txring->dma = 0;
644 txring->bufinf = NULL;
645
646 return -ENOMEM;
647}
648
649static void
650jme_free_tx_resources(struct jme_adapter *jme)
651{
652 int i;
653 struct jme_ring *txring = &(jme->txring[0]);
654 struct jme_buffer_info *txbi;
655
656 if (txring->alloc) {
657 if (txring->bufinf) {
658 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
659 txbi = txring->bufinf + i;
660 if (txbi->skb) {
661 dev_kfree_skb(txbi->skb);
662 txbi->skb = NULL;
663 }
664 txbi->mapping = 0;
665 txbi->len = 0;
666 txbi->nr_desc = 0;
667 txbi->start_xmit = 0;
668 }
669 kfree(txring->bufinf);
670 }
671
672 dma_free_coherent(&(jme->pdev->dev),
673 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
674 txring->alloc,
675 txring->dmaalloc);
676
677 txring->alloc = NULL;
678 txring->desc = NULL;
679 txring->dmaalloc = 0;
680 txring->dma = 0;
681 txring->bufinf = NULL;
682 }
683 txring->next_to_use = 0;
684 atomic_set(&txring->next_to_clean, 0);
685 atomic_set(&txring->nr_free, 0);
686}
687
688static inline void
689jme_enable_tx_engine(struct jme_adapter *jme)
690{
691 /*
692 * Select Queue 0
693 */
694 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
695 wmb();
696
697 /*
698 * Setup TX Queue 0 DMA Bass Address
699 */
700 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
701 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
702 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
703
704 /*
705 * Setup TX Descptor Count
706 */
707 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
708
709 /*
710 * Enable TX Engine
711 */
712 wmb();
713 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
714 TXCS_SELECT_QUEUE0 |
715 TXCS_ENABLE);
716
717 /*
718 * Start clock for TX MAC Processor
719 */
720 jme_mac_txclk_on(jme);
721}
722
723static inline void
724jme_restart_tx_engine(struct jme_adapter *jme)
725{
726 /*
727 * Restart TX Engine
728 */
729 jwrite32(jme, JME_TXCS, jme->reg_txcs |
730 TXCS_SELECT_QUEUE0 |
731 TXCS_ENABLE);
732}
733
734static inline void
735jme_disable_tx_engine(struct jme_adapter *jme)
736{
737 int i;
738 u32 val;
739
740 /*
741 * Disable TX Engine
742 */
743 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
744 wmb();
745
746 val = jread32(jme, JME_TXCS);
747 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
748 mdelay(1);
749 val = jread32(jme, JME_TXCS);
750 rmb();
751 }
752
753 if (!i)
754 pr_err("Disable TX engine timeout\n");
755
756 /*
757 * Stop clock for TX MAC Processor
758 */
759 jme_mac_txclk_off(jme);
760}
761
762static void
763jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
764{
765 struct jme_ring *rxring = &(jme->rxring[0]);
766 register struct rxdesc *rxdesc = rxring->desc;
767 struct jme_buffer_info *rxbi = rxring->bufinf;
768 rxdesc += i;
769 rxbi += i;
770
771 rxdesc->dw[0] = 0;
772 rxdesc->dw[1] = 0;
773 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
774 rxdesc->desc1.bufaddrl = cpu_to_le32(
775 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
776 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
777 if (jme->dev->features & NETIF_F_HIGHDMA)
778 rxdesc->desc1.flags = RXFLAG_64BIT;
779 wmb();
780 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
781}
782
783static int
784jme_make_new_rx_buf(struct jme_adapter *jme, int i)
785{
786 struct jme_ring *rxring = &(jme->rxring[0]);
787 struct jme_buffer_info *rxbi = rxring->bufinf + i;
788 struct sk_buff *skb;
789
790 skb = netdev_alloc_skb(jme->dev,
791 jme->dev->mtu + RX_EXTRA_LEN);
792 if (unlikely(!skb))
793 return -ENOMEM;
794#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
795 skb->dev = jme->dev;
796#endif
797
798 rxbi->skb = skb;
799 rxbi->len = skb_tailroom(skb);
800 rxbi->mapping = pci_map_page(jme->pdev,
801 virt_to_page(skb->data),
802 offset_in_page(skb->data),
803 rxbi->len,
804 PCI_DMA_FROMDEVICE);
805
806 return 0;
807}
808
809static void
810jme_free_rx_buf(struct jme_adapter *jme, int i)
811{
812 struct jme_ring *rxring = &(jme->rxring[0]);
813 struct jme_buffer_info *rxbi = rxring->bufinf;
814 rxbi += i;
815
816 if (rxbi->skb) {
817 pci_unmap_page(jme->pdev,
818 rxbi->mapping,
819 rxbi->len,
820 PCI_DMA_FROMDEVICE);
821 dev_kfree_skb(rxbi->skb);
822 rxbi->skb = NULL;
823 rxbi->mapping = 0;
824 rxbi->len = 0;
825 }
826}
827
828static void
829jme_free_rx_resources(struct jme_adapter *jme)
830{
831 int i;
832 struct jme_ring *rxring = &(jme->rxring[0]);
833
834 if (rxring->alloc) {
835 if (rxring->bufinf) {
836 for (i = 0 ; i < jme->rx_ring_size ; ++i)
837 jme_free_rx_buf(jme, i);
838 kfree(rxring->bufinf);
839 }
840
841 dma_free_coherent(&(jme->pdev->dev),
842 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
843 rxring->alloc,
844 rxring->dmaalloc);
845 rxring->alloc = NULL;
846 rxring->desc = NULL;
847 rxring->dmaalloc = 0;
848 rxring->dma = 0;
849 rxring->bufinf = NULL;
850 }
851 rxring->next_to_use = 0;
852 atomic_set(&rxring->next_to_clean, 0);
853}
854
855static int
856jme_setup_rx_resources(struct jme_adapter *jme)
857{
858 int i;
859 struct jme_ring *rxring = &(jme->rxring[0]);
860
861 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
862 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
863 &(rxring->dmaalloc),
864 GFP_ATOMIC);
865 if (!rxring->alloc)
866 goto err_set_null;
867
868 /*
869 * 16 Bytes align
870 */
871 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
872 RING_DESC_ALIGN);
873 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
874 rxring->next_to_use = 0;
875 atomic_set(&rxring->next_to_clean, 0);
876
877 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
878 jme->rx_ring_size, GFP_ATOMIC);
879 if (unlikely(!(rxring->bufinf)))
880 goto err_free_rxring;
881
882 /*
883 * Initiallize Receive Descriptors
884 */
885 memset(rxring->bufinf, 0,
886 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
887 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
888 if (unlikely(jme_make_new_rx_buf(jme, i))) {
889 jme_free_rx_resources(jme);
890 return -ENOMEM;
891 }
892
893 jme_set_clean_rxdesc(jme, i);
894 }
895
896 return 0;
897
898err_free_rxring:
899 dma_free_coherent(&(jme->pdev->dev),
900 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
901 rxring->alloc,
902 rxring->dmaalloc);
903err_set_null:
904 rxring->desc = NULL;
905 rxring->dmaalloc = 0;
906 rxring->dma = 0;
907 rxring->bufinf = NULL;
908
909 return -ENOMEM;
910}
911
912static inline void
913jme_enable_rx_engine(struct jme_adapter *jme)
914{
915 /*
916 * Select Queue 0
917 */
918 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
919 RXCS_QUEUESEL_Q0);
920 wmb();
921
922 /*
923 * Setup RX DMA Bass Address
924 */
925 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
926 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
927 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
928
929 /*
930 * Setup RX Descriptor Count
931 */
932 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
933
934 /*
935 * Setup Unicast Filter
936 */
937 jme_set_unicastaddr(jme->dev);
938 jme_set_multi(jme->dev);
939
940 /*
941 * Enable RX Engine
942 */
943 wmb();
944 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
945 RXCS_QUEUESEL_Q0 |
946 RXCS_ENABLE |
947 RXCS_QST);
948
949 /*
950 * Start clock for RX MAC Processor
951 */
952 jme_mac_rxclk_on(jme);
953}
954
955static inline void
956jme_restart_rx_engine(struct jme_adapter *jme)
957{
958 /*
959 * Start RX Engine
960 */
961 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
962 RXCS_QUEUESEL_Q0 |
963 RXCS_ENABLE |
964 RXCS_QST);
965}
966
967static inline void
968jme_disable_rx_engine(struct jme_adapter *jme)
969{
970 int i;
971 u32 val;
972
973 /*
974 * Disable RX Engine
975 */
976 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
977 wmb();
978
979 val = jread32(jme, JME_RXCS);
980 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
981 mdelay(1);
982 val = jread32(jme, JME_RXCS);
983 rmb();
984 }
985
986 if (!i)
987 pr_err("Disable RX engine timeout\n");
988
989 /*
990 * Stop clock for RX MAC Processor
991 */
992 jme_mac_rxclk_off(jme);
993}
994
995static u16
996jme_udpsum(struct sk_buff *skb)
997{
998 u16 csum = 0xFFFFu;
999
1000 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
1001 return csum;
1002 if (skb->protocol != htons(ETH_P_IP))
1003 return csum;
1004 skb_set_network_header(skb, ETH_HLEN);
1005 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1006 (skb->len < (ETH_HLEN +
1007 (ip_hdr(skb)->ihl << 2) +
1008 sizeof(struct udphdr)))) {
1009 skb_reset_network_header(skb);
1010 return csum;
1011 }
1012 skb_set_transport_header(skb,
1013 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1014 csum = udp_hdr(skb)->check;
1015 skb_reset_transport_header(skb);
1016 skb_reset_network_header(skb);
1017
1018 return csum;
1019}
1020
1021static int
1022jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1023{
1024 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1025 return false;
1026
1027 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1028 == RXWBFLAG_TCPON)) {
1029 if (flags & RXWBFLAG_IPV4)
1030 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1031 return false;
1032 }
1033
1034 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1035 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1036 if (flags & RXWBFLAG_IPV4)
1037 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1038 return false;
1039 }
1040
1041 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1042 == RXWBFLAG_IPV4)) {
1043 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1044 return false;
1045 }
1046
1047 return true;
1048}
1049
1050static void
1051jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1052{
1053 struct jme_ring *rxring = &(jme->rxring[0]);
1054 struct rxdesc *rxdesc = rxring->desc;
1055 struct jme_buffer_info *rxbi = rxring->bufinf;
1056 struct sk_buff *skb;
1057 int framesize;
1058
1059 rxdesc += idx;
1060 rxbi += idx;
1061
1062 skb = rxbi->skb;
1063 pci_dma_sync_single_for_cpu(jme->pdev,
1064 rxbi->mapping,
1065 rxbi->len,
1066 PCI_DMA_FROMDEVICE);
1067
1068 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1069 pci_dma_sync_single_for_device(jme->pdev,
1070 rxbi->mapping,
1071 rxbi->len,
1072 PCI_DMA_FROMDEVICE);
1073
1074 ++(NET_STAT(jme).rx_dropped);
1075 } else {
1076 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1077 - RX_PREPAD_SIZE;
1078
1079 skb_reserve(skb, RX_PREPAD_SIZE);
1080 skb_put(skb, framesize);
1081 skb->protocol = eth_type_trans(skb, jme->dev);
1082
1083 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1084 skb->ip_summed = CHECKSUM_UNNECESSARY;
1085 else
1086#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1087 skb->ip_summed = CHECKSUM_NONE;
1088#else
1089 skb_checksum_none_assert(skb);
1090#endif
1091
1092 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1093 if (jme->vlgrp) {
1094 jme->jme_vlan_rx(skb, jme->vlgrp,
1095 le16_to_cpu(rxdesc->descwb.vlan));
1096 NET_STAT(jme).rx_bytes += 4;
1097 } else {
1098 dev_kfree_skb(skb);
1099 }
1100 } else {
1101 jme->jme_rx(skb);
1102 }
1103
1104 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1105 cpu_to_le16(RXWBFLAG_DEST_MUL))
1106 ++(NET_STAT(jme).multicast);
1107
1108 NET_STAT(jme).rx_bytes += framesize;
1109 ++(NET_STAT(jme).rx_packets);
1110 }
1111
1112 jme_set_clean_rxdesc(jme, idx);
1113
1114}
1115
1116static int
1117jme_process_receive(struct jme_adapter *jme, int limit)
1118{
1119 struct jme_ring *rxring = &(jme->rxring[0]);
1120 struct rxdesc *rxdesc = rxring->desc;
1121 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1122
1123 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1124 goto out_inc;
1125
1126 if (unlikely(atomic_read(&jme->link_changing) != 1))
1127 goto out_inc;
1128
1129 if (unlikely(!netif_carrier_ok(jme->dev)))
1130 goto out_inc;
1131
1132 i = atomic_read(&rxring->next_to_clean);
1133 while (limit > 0) {
1134 rxdesc = rxring->desc;
1135 rxdesc += i;
1136
1137 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1138 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1139 goto out;
1140 --limit;
1141
1142 rmb();
1143 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1144
1145 if (unlikely(desccnt > 1 ||
1146 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1147
1148 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1149 ++(NET_STAT(jme).rx_crc_errors);
1150 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1151 ++(NET_STAT(jme).rx_fifo_errors);
1152 else
1153 ++(NET_STAT(jme).rx_errors);
1154
1155 if (desccnt > 1)
1156 limit -= desccnt - 1;
1157
1158 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1159 jme_set_clean_rxdesc(jme, j);
1160 j = (j + 1) & (mask);
1161 }
1162
1163 } else {
1164 jme_alloc_and_feed_skb(jme, i);
1165 }
1166
1167 i = (i + desccnt) & (mask);
1168 }
1169
1170out:
1171 atomic_set(&rxring->next_to_clean, i);
1172
1173out_inc:
1174 atomic_inc(&jme->rx_cleaning);
1175
1176 return limit > 0 ? limit : 0;
1177
1178}
1179
1180static void
1181jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1182{
1183 if (likely(atmp == dpi->cur)) {
1184 dpi->cnt = 0;
1185 return;
1186 }
1187
1188 if (dpi->attempt == atmp) {
1189 ++(dpi->cnt);
1190 } else {
1191 dpi->attempt = atmp;
1192 dpi->cnt = 0;
1193 }
1194
1195}
1196
1197static void
1198jme_dynamic_pcc(struct jme_adapter *jme)
1199{
1200 register struct dynpcc_info *dpi = &(jme->dpi);
1201
1202 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1203 jme_attempt_pcc(dpi, PCC_P3);
1204 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1205 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1206 jme_attempt_pcc(dpi, PCC_P2);
1207 else
1208 jme_attempt_pcc(dpi, PCC_P1);
1209
1210 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1211 if (dpi->attempt < dpi->cur)
1212 tasklet_schedule(&jme->rxclean_task);
1213 jme_set_rx_pcc(jme, dpi->attempt);
1214 dpi->cur = dpi->attempt;
1215 dpi->cnt = 0;
1216 }
1217}
1218
1219static void
1220jme_start_pcc_timer(struct jme_adapter *jme)
1221{
1222 struct dynpcc_info *dpi = &(jme->dpi);
1223 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1224 dpi->last_pkts = NET_STAT(jme).rx_packets;
1225 dpi->intr_cnt = 0;
1226 jwrite32(jme, JME_TMCSR,
1227 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1228}
1229
1230static inline void
1231jme_stop_pcc_timer(struct jme_adapter *jme)
1232{
1233 jwrite32(jme, JME_TMCSR, 0);
1234}
1235
1236static void
1237jme_shutdown_nic(struct jme_adapter *jme)
1238{
1239 u32 phylink;
1240
1241 phylink = jme_linkstat_from_phy(jme);
1242
1243 if (!(phylink & PHY_LINK_UP)) {
1244 /*
1245 * Disable all interrupt before issue timer
1246 */
1247 jme_stop_irq(jme);
1248 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1249 }
1250}
1251
1252static void
1253jme_pcc_tasklet(unsigned long arg)
1254{
1255 struct jme_adapter *jme = (struct jme_adapter *)arg;
1256 struct net_device *netdev = jme->dev;
1257
1258 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1259 jme_shutdown_nic(jme);
1260 return;
1261 }
1262
1263 if (unlikely(!netif_carrier_ok(netdev) ||
1264 (atomic_read(&jme->link_changing) != 1)
1265 )) {
1266 jme_stop_pcc_timer(jme);
1267 return;
1268 }
1269
1270 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1271 jme_dynamic_pcc(jme);
1272
1273 jme_start_pcc_timer(jme);
1274}
1275
1276static inline void
1277jme_polling_mode(struct jme_adapter *jme)
1278{
1279 jme_set_rx_pcc(jme, PCC_OFF);
1280}
1281
1282static inline void
1283jme_interrupt_mode(struct jme_adapter *jme)
1284{
1285 jme_set_rx_pcc(jme, PCC_P1);
1286}
1287
1288static inline int
1289jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1290{
1291 u32 apmc;
1292 apmc = jread32(jme, JME_APMC);
1293 return apmc & JME_APMC_PSEUDO_HP_EN;
1294}
1295
1296static void
1297jme_start_shutdown_timer(struct jme_adapter *jme)
1298{
1299 u32 apmc;
1300
1301 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1302 apmc &= ~JME_APMC_EPIEN_CTRL;
1303 if (!no_extplug) {
1304 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1305 wmb();
1306 }
1307 jwrite32f(jme, JME_APMC, apmc);
1308
1309 jwrite32f(jme, JME_TIMER2, 0);
1310 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1311 jwrite32(jme, JME_TMCSR,
1312 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1313}
1314
1315static void
1316jme_stop_shutdown_timer(struct jme_adapter *jme)
1317{
1318 u32 apmc;
1319
1320 jwrite32f(jme, JME_TMCSR, 0);
1321 jwrite32f(jme, JME_TIMER2, 0);
1322 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1323
1324 apmc = jread32(jme, JME_APMC);
1325 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1326 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1327 wmb();
1328 jwrite32f(jme, JME_APMC, apmc);
1329}
1330
1331static void
1332jme_link_change_tasklet(unsigned long arg)
1333{
1334 struct jme_adapter *jme = (struct jme_adapter *)arg;
1335 struct net_device *netdev = jme->dev;
1336 int rc;
1337
1338 while (!atomic_dec_and_test(&jme->link_changing)) {
1339 atomic_inc(&jme->link_changing);
1340 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1341 while (atomic_read(&jme->link_changing) != 1)
1342 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1343 }
1344
1345 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1346 goto out;
1347
1348 jme->old_mtu = netdev->mtu;
1349 netif_stop_queue(netdev);
1350 if (jme_pseudo_hotplug_enabled(jme))
1351 jme_stop_shutdown_timer(jme);
1352
1353 jme_stop_pcc_timer(jme);
1354 tasklet_disable(&jme->txclean_task);
1355 tasklet_disable(&jme->rxclean_task);
1356 tasklet_disable(&jme->rxempty_task);
1357
1358 if (netif_carrier_ok(netdev)) {
1359 jme_disable_rx_engine(jme);
1360 jme_disable_tx_engine(jme);
1361 jme_reset_mac_processor(jme);
1362 jme_free_rx_resources(jme);
1363 jme_free_tx_resources(jme);
1364
1365 if (test_bit(JME_FLAG_POLL, &jme->flags))
1366 jme_polling_mode(jme);
1367
1368 netif_carrier_off(netdev);
1369 }
1370
1371 jme_check_link(netdev, 0);
1372 if (netif_carrier_ok(netdev)) {
1373 rc = jme_setup_rx_resources(jme);
1374 if (rc) {
1375 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1376 goto out_enable_tasklet;
1377 }
1378
1379 rc = jme_setup_tx_resources(jme);
1380 if (rc) {
1381 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1382 goto err_out_free_rx_resources;
1383 }
1384
1385 jme_enable_rx_engine(jme);
1386 jme_enable_tx_engine(jme);
1387
1388 netif_start_queue(netdev);
1389
1390 if (test_bit(JME_FLAG_POLL, &jme->flags))
1391 jme_interrupt_mode(jme);
1392
1393 jme_start_pcc_timer(jme);
1394 } else if (jme_pseudo_hotplug_enabled(jme)) {
1395 jme_start_shutdown_timer(jme);
1396 }
1397
1398 goto out_enable_tasklet;
1399
1400err_out_free_rx_resources:
1401 jme_free_rx_resources(jme);
1402out_enable_tasklet:
1403 tasklet_enable(&jme->txclean_task);
1404 tasklet_hi_enable(&jme->rxclean_task);
1405 tasklet_hi_enable(&jme->rxempty_task);
1406out:
1407 atomic_inc(&jme->link_changing);
1408}
1409
1410static void
1411jme_rx_clean_tasklet(unsigned long arg)
1412{
1413 struct jme_adapter *jme = (struct jme_adapter *)arg;
1414 struct dynpcc_info *dpi = &(jme->dpi);
1415
1416 jme_process_receive(jme, jme->rx_ring_size);
1417 ++(dpi->intr_cnt);
1418
1419}
1420
1421static int
1422jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1423{
1424 struct jme_adapter *jme = jme_napi_priv(holder);
1425 DECLARE_NETDEV
1426 int rest;
1427
1428 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1429
1430 while (atomic_read(&jme->rx_empty) > 0) {
1431 atomic_dec(&jme->rx_empty);
1432 ++(NET_STAT(jme).rx_dropped);
1433 jme_restart_rx_engine(jme);
1434 }
1435 atomic_inc(&jme->rx_empty);
1436
1437 if (rest) {
1438 JME_RX_COMPLETE(netdev, holder);
1439 jme_interrupt_mode(jme);
1440 }
1441
1442 JME_NAPI_WEIGHT_SET(budget, rest);
1443 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1444}
1445
1446static void
1447jme_rx_empty_tasklet(unsigned long arg)
1448{
1449 struct jme_adapter *jme = (struct jme_adapter *)arg;
1450
1451 if (unlikely(atomic_read(&jme->link_changing) != 1))
1452 return;
1453
1454 if (unlikely(!netif_carrier_ok(jme->dev)))
1455 return;
1456
1457 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1458
1459 jme_rx_clean_tasklet(arg);
1460
1461 while (atomic_read(&jme->rx_empty) > 0) {
1462 atomic_dec(&jme->rx_empty);
1463 ++(NET_STAT(jme).rx_dropped);
1464 jme_restart_rx_engine(jme);
1465 }
1466 atomic_inc(&jme->rx_empty);
1467}
1468
1469static void
1470jme_wake_queue_if_stopped(struct jme_adapter *jme)
1471{
1472 struct jme_ring *txring = &(jme->txring[0]);
1473
1474 smp_wmb();
1475 if (unlikely(netif_queue_stopped(jme->dev) &&
1476 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1477 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1478 netif_wake_queue(jme->dev);
1479 }
1480
1481}
1482
1483static void
1484jme_tx_clean_tasklet(unsigned long arg)
1485{
1486 struct jme_adapter *jme = (struct jme_adapter *)arg;
1487 struct jme_ring *txring = &(jme->txring[0]);
1488 struct txdesc *txdesc = txring->desc;
1489 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1490 int i, j, cnt = 0, max, err, mask;
1491
1492 tx_dbg(jme, "Into txclean\n");
1493
1494 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1495 goto out;
1496
1497 if (unlikely(atomic_read(&jme->link_changing) != 1))
1498 goto out;
1499
1500 if (unlikely(!netif_carrier_ok(jme->dev)))
1501 goto out;
1502
1503 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1504 mask = jme->tx_ring_mask;
1505
1506 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1507
1508 ctxbi = txbi + i;
1509
1510 if (likely(ctxbi->skb &&
1511 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1512
1513 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1514 i, ctxbi->nr_desc, jiffies);
1515
1516 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1517
1518 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1519 ttxbi = txbi + ((i + j) & (mask));
1520 txdesc[(i + j) & (mask)].dw[0] = 0;
1521
1522 pci_unmap_page(jme->pdev,
1523 ttxbi->mapping,
1524 ttxbi->len,
1525 PCI_DMA_TODEVICE);
1526
1527 ttxbi->mapping = 0;
1528 ttxbi->len = 0;
1529 }
1530
1531 dev_kfree_skb(ctxbi->skb);
1532
1533 cnt += ctxbi->nr_desc;
1534
1535 if (unlikely(err)) {
1536 ++(NET_STAT(jme).tx_carrier_errors);
1537 } else {
1538 ++(NET_STAT(jme).tx_packets);
1539 NET_STAT(jme).tx_bytes += ctxbi->len;
1540 }
1541
1542 ctxbi->skb = NULL;
1543 ctxbi->len = 0;
1544 ctxbi->start_xmit = 0;
1545
1546 } else {
1547 break;
1548 }
1549
1550 i = (i + ctxbi->nr_desc) & mask;
1551
1552 ctxbi->nr_desc = 0;
1553 }
1554
1555 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1556 atomic_set(&txring->next_to_clean, i);
1557 atomic_add(cnt, &txring->nr_free);
1558
1559 jme_wake_queue_if_stopped(jme);
1560
1561out:
1562 atomic_inc(&jme->tx_cleaning);
1563}
1564
1565static void
1566jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1567{
1568 /*
1569 * Disable interrupt
1570 */
1571 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1572
1573 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1574 /*
1575 * Link change event is critical
1576 * all other events are ignored
1577 */
1578 jwrite32(jme, JME_IEVE, intrstat);
1579 tasklet_schedule(&jme->linkch_task);
1580 goto out_reenable;
1581 }
1582
1583 if (intrstat & INTR_TMINTR) {
1584 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1585 tasklet_schedule(&jme->pcc_task);
1586 }
1587
1588 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1589 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1590 tasklet_schedule(&jme->txclean_task);
1591 }
1592
1593 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1594 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1595 INTR_PCCRX0 |
1596 INTR_RX0EMP)) |
1597 INTR_RX0);
1598 }
1599
1600 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1601 if (intrstat & INTR_RX0EMP)
1602 atomic_inc(&jme->rx_empty);
1603
1604 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1605 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1606 jme_polling_mode(jme);
1607 JME_RX_SCHEDULE(jme);
1608 }
1609 }
1610 } else {
1611 if (intrstat & INTR_RX0EMP) {
1612 atomic_inc(&jme->rx_empty);
1613 tasklet_hi_schedule(&jme->rxempty_task);
1614 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1615 tasklet_hi_schedule(&jme->rxclean_task);
1616 }
1617 }
1618
1619out_reenable:
1620 /*
1621 * Re-enable interrupt
1622 */
1623 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1624}
1625
1626#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1627static irqreturn_t
1628jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1629#else
1630static irqreturn_t
1631jme_intr(int irq, void *dev_id)
1632#endif
1633{
1634 struct net_device *netdev = dev_id;
1635 struct jme_adapter *jme = netdev_priv(netdev);
1636 u32 intrstat;
1637
1638 intrstat = jread32(jme, JME_IEVE);
1639
1640 /*
1641 * Check if it's really an interrupt for us
1642 */
1643 if (unlikely((intrstat & INTR_ENABLE) == 0))
1644 return IRQ_NONE;
1645
1646 /*
1647 * Check if the device still exist
1648 */
1649 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1650 return IRQ_NONE;
1651
1652 jme_intr_msi(jme, intrstat);
1653
1654 return IRQ_HANDLED;
1655}
1656
1657#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1658static irqreturn_t
1659jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1660#else
1661static irqreturn_t
1662jme_msi(int irq, void *dev_id)
1663#endif
1664{
1665 struct net_device *netdev = dev_id;
1666 struct jme_adapter *jme = netdev_priv(netdev);
1667 u32 intrstat;
1668
1669 intrstat = jread32(jme, JME_IEVE);
1670
1671 jme_intr_msi(jme, intrstat);
1672
1673 return IRQ_HANDLED;
1674}
1675
1676static void
1677jme_reset_link(struct jme_adapter *jme)
1678{
1679 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1680}
1681
1682static void
1683jme_restart_an(struct jme_adapter *jme)
1684{
1685 u32 bmcr;
1686
1687 spin_lock_bh(&jme->phy_lock);
1688 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1689 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1690 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1691 spin_unlock_bh(&jme->phy_lock);
1692}
1693
1694static int
1695jme_request_irq(struct jme_adapter *jme)
1696{
1697 int rc;
1698 struct net_device *netdev = jme->dev;
1699#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1700 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1701 int irq_flags = SA_SHIRQ;
1702#else
1703 irq_handler_t handler = jme_intr;
1704 int irq_flags = IRQF_SHARED;
1705#endif
1706
1707 if (!pci_enable_msi(jme->pdev)) {
1708 set_bit(JME_FLAG_MSI, &jme->flags);
1709 handler = jme_msi;
1710 irq_flags = 0;
1711 }
1712
1713 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1714 netdev);
1715 if (rc) {
1716 netdev_err(netdev,
1717 "Unable to request %s interrupt (return: %d)\n",
1718 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1719 rc);
1720
1721 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1722 pci_disable_msi(jme->pdev);
1723 clear_bit(JME_FLAG_MSI, &jme->flags);
1724 }
1725 } else {
1726 netdev->irq = jme->pdev->irq;
1727 }
1728
1729 return rc;
1730}
1731
1732static void
1733jme_free_irq(struct jme_adapter *jme)
1734{
1735 free_irq(jme->pdev->irq, jme->dev);
1736 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1737 pci_disable_msi(jme->pdev);
1738 clear_bit(JME_FLAG_MSI, &jme->flags);
1739 jme->dev->irq = jme->pdev->irq;
1740 }
1741}
1742
1743static inline void
1744jme_new_phy_on(struct jme_adapter *jme)
1745{
1746 u32 reg;
1747
1748 reg = jread32(jme, JME_PHY_PWR);
1749 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1750 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1751 jwrite32(jme, JME_PHY_PWR, reg);
1752
1753 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1754 reg &= ~PE1_GPREG0_PBG;
1755 reg |= PE1_GPREG0_ENBG;
1756 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1757}
1758
1759static inline void
1760jme_new_phy_off(struct jme_adapter *jme)
1761{
1762 u32 reg;
1763
1764 reg = jread32(jme, JME_PHY_PWR);
1765 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1766 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1767 jwrite32(jme, JME_PHY_PWR, reg);
1768
1769 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1770 reg &= ~PE1_GPREG0_PBG;
1771 reg |= PE1_GPREG0_PDD3COLD;
1772 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1773}
1774
1775static inline void
1776jme_recal_phy(struct jme_adapter *jme)
1777{
1778 u32 miictl1000, comm2;
1779
1780 miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1781 miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
1782 miictl1000 |= JME_PHY_GCTRL_TESTMODE1;
1783 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
1784
1785 comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
1786 comm2 &= ~(0x0001u);
1787 comm2 |= 0x0011u;
1788 jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
1789
1790 mdelay(20);
1791
1792 comm2 = jme_phyext_read(jme, JME_PHYEXT_COMM2);
1793 comm2 &= ~(0x0013u);
1794 jme_phyext_write(jme, JME_PHYEXT_COMM2, comm2);
1795
1796 miictl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1797 miictl1000 &= ~JME_PHY_GCTRL_TESTMASK;
1798 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, miictl1000);
1799}
1800
1801static inline void
1802jme_set_phyparm(struct jme_adapter *jme, u32 val)
1803{
1804 u32 comm0, comm1;
1805
1806 comm0 = jme_phyext_read(jme, JME_PHYEXT_COMM0);
1807 comm1 = jme_phyext_read(jme, JME_PHYEXT_COMM1);
1808 comm0 &= ~(0xE000u);
1809 comm0 |= ((val << 13) & 0xE000u);
1810 comm1 &= ~(0x0001u);
1811 comm1 |= ((val >> 3) & 0x0001u);
1812 jme_phyext_write(jme, JME_PHYEXT_COMM0, comm0);
1813 jme_phyext_write(jme, JME_PHYEXT_COMM1, comm1);
1814}
1815
1816static inline void
1817jme_refill_phyparm(struct jme_adapter *jme)
1818{
1819 if (jme->chip_main_rev >= 6 ||
1820 (jme->chip_main_rev == 5 &&
1821 (jme->chip_sub_rev == 0 ||
1822 jme->chip_sub_rev == 1 ||
1823 jme->chip_sub_rev == 3))) {
1824 jme_set_phyparm(jme, 0x8);
1825 } else if (jme->chip_main_rev == 3 &&
1826 (jme->chip_sub_rev == 1 ||
1827 jme->chip_sub_rev == 2)) {
1828 jme_set_phyparm(jme, 0x7);
1829 } else if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260 &&
1830 jme->chip_main_rev == 2) {
1831 if (jme->chip_sub_rev == 0)
1832 jme_set_phyparm(jme, 0x3);
1833 else if (jme->chip_sub_rev == 2)
1834 jme_set_phyparm(jme, 0x2);
1835 }
1836}
1837
1838static inline void
1839jme_phy_on(struct jme_adapter *jme)
1840{
1841 u32 bmcr;
1842
1843 if (new_phy_power_ctrl(jme->chip_main_rev))
1844 jme_new_phy_on(jme);
1845
1846 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1847 bmcr &= ~BMCR_PDOWN;
1848 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1849
1850 jme_recal_phy(jme);
1851 jme_refill_phyparm(jme);
1852}
1853
1854static inline void
1855jme_phy_off(struct jme_adapter *jme)
1856{
1857 u32 bmcr;
1858
1859 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1860 bmcr |= BMCR_PDOWN;
1861 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1862
1863 if (new_phy_power_ctrl(jme->chip_main_rev))
1864 jme_new_phy_off(jme);
1865}
1866
1867static int
1868jme_open(struct net_device *netdev)
1869{
1870 struct jme_adapter *jme = netdev_priv(netdev);
1871 int rc;
1872
1873 jme_clear_pm(jme);
1874 JME_NAPI_ENABLE(jme);
1875
1876 tasklet_enable(&jme->linkch_task);
1877 tasklet_enable(&jme->txclean_task);
1878 tasklet_hi_enable(&jme->rxclean_task);
1879 tasklet_hi_enable(&jme->rxempty_task);
1880
1881 rc = jme_request_irq(jme);
1882 if (rc)
1883 goto err_out;
1884
1885 jme_start_irq(jme);
1886
1887 jme_phy_on(jme);
1888 if (test_bit(JME_FLAG_SSET, &jme->flags))
1889 jme_set_settings(netdev, &jme->old_ecmd);
1890 else
1891 jme_reset_phy_processor(jme);
1892
1893 jme_reset_link(jme);
1894
1895 return 0;
1896
1897err_out:
1898 netif_stop_queue(netdev);
1899 netif_carrier_off(netdev);
1900 return rc;
1901}
1902
1903static void
1904jme_set_100m_half(struct jme_adapter *jme)
1905{
1906 u32 bmcr, tmp;
1907
1908 jme_phy_on(jme);
1909 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1910 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1911 BMCR_SPEED1000 | BMCR_FULLDPLX);
1912 tmp |= BMCR_SPEED100;
1913
1914 if (bmcr != tmp)
1915 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1916
1917 if (jme->fpgaver)
1918 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1919 else
1920 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1921}
1922
1923#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1924static void
1925jme_wait_link(struct jme_adapter *jme)
1926{
1927 u32 phylink, to = JME_WAIT_LINK_TIME;
1928
1929 mdelay(1000);
1930 phylink = jme_linkstat_from_phy(jme);
1931 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1932 mdelay(10);
1933 phylink = jme_linkstat_from_phy(jme);
1934 }
1935}
1936
1937static void
1938jme_powersave_phy(struct jme_adapter *jme)
1939{
1940 if (jme->reg_pmcs) {
1941 jme_set_100m_half(jme);
1942
1943 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1944 jme_wait_link(jme);
1945
1946 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1947 } else {
1948 jme_phy_off(jme);
1949 }
1950}
1951
1952static int
1953jme_close(struct net_device *netdev)
1954{
1955 struct jme_adapter *jme = netdev_priv(netdev);
1956
1957 netif_stop_queue(netdev);
1958 netif_carrier_off(netdev);
1959
1960 jme_stop_irq(jme);
1961 jme_free_irq(jme);
1962
1963 JME_NAPI_DISABLE(jme);
1964
1965 tasklet_disable(&jme->linkch_task);
1966 tasklet_disable(&jme->txclean_task);
1967 tasklet_disable(&jme->rxclean_task);
1968 tasklet_disable(&jme->rxempty_task);
1969
1970 jme_disable_rx_engine(jme);
1971 jme_disable_tx_engine(jme);
1972 jme_reset_mac_processor(jme);
1973 jme_free_rx_resources(jme);
1974 jme_free_tx_resources(jme);
1975 jme->phylink = 0;
1976 jme_phy_off(jme);
1977
1978 return 0;
1979}
1980
1981static int
1982jme_alloc_txdesc(struct jme_adapter *jme,
1983 struct sk_buff *skb)
1984{
1985 struct jme_ring *txring = &(jme->txring[0]);
1986 int idx, nr_alloc, mask = jme->tx_ring_mask;
1987
1988 idx = txring->next_to_use;
1989 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1990
1991 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1992 return -1;
1993
1994 atomic_sub(nr_alloc, &txring->nr_free);
1995
1996 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1997
1998 return idx;
1999}
2000
2001static void
2002jme_fill_tx_map(struct pci_dev *pdev,
2003 struct txdesc *txdesc,
2004 struct jme_buffer_info *txbi,
2005 struct page *page,
2006 u32 page_offset,
2007 u32 len,
2008 u8 hidma)
2009{
2010 dma_addr_t dmaaddr;
2011
2012 dmaaddr = pci_map_page(pdev,
2013 page,
2014 page_offset,
2015 len,
2016 PCI_DMA_TODEVICE);
2017
2018 pci_dma_sync_single_for_device(pdev,
2019 dmaaddr,
2020 len,
2021 PCI_DMA_TODEVICE);
2022
2023 txdesc->dw[0] = 0;
2024 txdesc->dw[1] = 0;
2025 txdesc->desc2.flags = TXFLAG_OWN;
2026 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
2027 txdesc->desc2.datalen = cpu_to_le16(len);
2028 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
2029 txdesc->desc2.bufaddrl = cpu_to_le32(
2030 (__u64)dmaaddr & 0xFFFFFFFFUL);
2031
2032 txbi->mapping = dmaaddr;
2033 txbi->len = len;
2034}
2035
2036static void
2037jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2038{
2039 struct jme_ring *txring = &(jme->txring[0]);
2040 struct txdesc *txdesc = txring->desc, *ctxdesc;
2041 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2042 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
2043 int i, nr_frags = skb_shinfo(skb)->nr_frags;
2044 int mask = jme->tx_ring_mask;
2045 struct skb_frag_struct *frag;
2046 u32 len;
2047
2048 for (i = 0 ; i < nr_frags ; ++i) {
2049 frag = &skb_shinfo(skb)->frags[i];
2050 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2051 ctxbi = txbi + ((idx + i + 2) & (mask));
2052
2053 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
2054 frag->page_offset, frag->size, hidma);
2055 }
2056
2057 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2058 ctxdesc = txdesc + ((idx + 1) & (mask));
2059 ctxbi = txbi + ((idx + 1) & (mask));
2060 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2061 offset_in_page(skb->data), len, hidma);
2062
2063}
2064
2065static int
2066jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2067{
2068 if (unlikely(
2069#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2070 skb_shinfo(skb)->tso_size
2071#else
2072 skb_shinfo(skb)->gso_size
2073#endif
2074 && skb_header_cloned(skb) &&
2075 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2076 dev_kfree_skb(skb);
2077 return -1;
2078 }
2079
2080 return 0;
2081}
2082
2083static int
2084jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2085{
2086#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2087 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2088#else
2089 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2090#endif
2091 if (*mss) {
2092 *flags |= TXFLAG_LSEN;
2093
2094 if (skb->protocol == htons(ETH_P_IP)) {
2095 struct iphdr *iph = ip_hdr(skb);
2096
2097 iph->check = 0;
2098 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2099 iph->daddr, 0,
2100 IPPROTO_TCP,
2101 0);
2102 } else {
2103 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2104
2105 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2106 &ip6h->daddr, 0,
2107 IPPROTO_TCP,
2108 0);
2109 }
2110
2111 return 0;
2112 }
2113
2114 return 1;
2115}
2116
2117static void
2118jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2119{
2120#ifdef CHECKSUM_PARTIAL
2121 if (skb->ip_summed == CHECKSUM_PARTIAL)
2122#else
2123 if (skb->ip_summed == CHECKSUM_HW)
2124#endif
2125 {
2126 u8 ip_proto;
2127
2128#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2129 if (skb->protocol == htons(ETH_P_IP))
2130 ip_proto = ip_hdr(skb)->protocol;
2131 else if (skb->protocol == htons(ETH_P_IPV6))
2132 ip_proto = ipv6_hdr(skb)->nexthdr;
2133 else
2134 ip_proto = 0;
2135#else
2136 switch (skb->protocol) {
2137 case htons(ETH_P_IP):
2138 ip_proto = ip_hdr(skb)->protocol;
2139 break;
2140 case htons(ETH_P_IPV6):
2141 ip_proto = ipv6_hdr(skb)->nexthdr;
2142 break;
2143 default:
2144 ip_proto = 0;
2145 break;
2146 }
2147#endif
2148
2149 switch (ip_proto) {
2150 case IPPROTO_TCP:
2151 *flags |= TXFLAG_TCPCS;
2152 break;
2153 case IPPROTO_UDP:
2154 *flags |= TXFLAG_UDPCS;
2155 break;
2156 default:
2157 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2158 break;
2159 }
2160 }
2161}
2162
2163static inline void
2164jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2165{
2166 if (vlan_tx_tag_present(skb)) {
2167 *flags |= TXFLAG_TAGON;
2168 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2169 }
2170}
2171
2172static int
2173jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2174{
2175 struct jme_ring *txring = &(jme->txring[0]);
2176 struct txdesc *txdesc;
2177 struct jme_buffer_info *txbi;
2178 u8 flags;
2179
2180 txdesc = (struct txdesc *)txring->desc + idx;
2181 txbi = txring->bufinf + idx;
2182
2183 txdesc->dw[0] = 0;
2184 txdesc->dw[1] = 0;
2185 txdesc->dw[2] = 0;
2186 txdesc->dw[3] = 0;
2187 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2188 /*
2189 * Set OWN bit at final.
2190 * When kernel transmit faster than NIC.
2191 * And NIC trying to send this descriptor before we tell
2192 * it to start sending this TX queue.
2193 * Other fields are already filled correctly.
2194 */
2195 wmb();
2196 flags = TXFLAG_OWN | TXFLAG_INT;
2197 /*
2198 * Set checksum flags while not tso
2199 */
2200 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2201 jme_tx_csum(jme, skb, &flags);
2202 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2203 jme_map_tx_skb(jme, skb, idx);
2204 txdesc->desc1.flags = flags;
2205 /*
2206 * Set tx buffer info after telling NIC to send
2207 * For better tx_clean timing
2208 */
2209 wmb();
2210 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2211 txbi->skb = skb;
2212 txbi->len = skb->len;
2213 txbi->start_xmit = jiffies;
2214 if (!txbi->start_xmit)
2215 txbi->start_xmit = (0UL-1);
2216
2217 return 0;
2218}
2219
2220static void
2221jme_stop_queue_if_full(struct jme_adapter *jme)
2222{
2223 struct jme_ring *txring = &(jme->txring[0]);
2224 struct jme_buffer_info *txbi = txring->bufinf;
2225 int idx = atomic_read(&txring->next_to_clean);
2226
2227 txbi += idx;
2228
2229 smp_wmb();
2230 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2231 netif_stop_queue(jme->dev);
2232 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2233 smp_wmb();
2234 if (atomic_read(&txring->nr_free)
2235 >= (jme->tx_wake_threshold)) {
2236 netif_wake_queue(jme->dev);
2237 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2238 }
2239 }
2240
2241 if (unlikely(txbi->start_xmit &&
2242 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2243 txbi->skb)) {
2244 netif_stop_queue(jme->dev);
2245 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2246 }
2247}
2248
2249/*
2250 * This function is already protected by netif_tx_lock()
2251 */
2252
2253#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2254static int
2255#else
2256static netdev_tx_t
2257#endif
2258jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2259{
2260 struct jme_adapter *jme = netdev_priv(netdev);
2261 int idx;
2262
2263 if (unlikely(jme_expand_header(jme, skb))) {
2264 ++(NET_STAT(jme).tx_dropped);
2265 return NETDEV_TX_OK;
2266 }
2267
2268 idx = jme_alloc_txdesc(jme, skb);
2269
2270 if (unlikely(idx < 0)) {
2271 netif_stop_queue(netdev);
2272 netif_err(jme, tx_err, jme->dev,
2273 "BUG! Tx ring full when queue awake!\n");
2274
2275 return NETDEV_TX_BUSY;
2276 }
2277
2278 jme_fill_tx_desc(jme, skb, idx);
2279
2280 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2281 TXCS_SELECT_QUEUE0 |
2282 TXCS_QUEUE0S |
2283 TXCS_ENABLE);
2284#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2285 netdev->trans_start = jiffies;
2286#endif
2287
2288 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2289 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2290 jme_stop_queue_if_full(jme);
2291
2292 return NETDEV_TX_OK;
2293}
2294
2295static void
2296jme_set_unicastaddr(struct net_device *netdev)
2297{
2298 struct jme_adapter *jme = netdev_priv(netdev);
2299 u32 val;
2300
2301 val = (netdev->dev_addr[3] & 0xff) << 24 |
2302 (netdev->dev_addr[2] & 0xff) << 16 |
2303 (netdev->dev_addr[1] & 0xff) << 8 |
2304 (netdev->dev_addr[0] & 0xff);
2305 jwrite32(jme, JME_RXUMA_LO, val);
2306 val = (netdev->dev_addr[5] & 0xff) << 8 |
2307 (netdev->dev_addr[4] & 0xff);
2308 jwrite32(jme, JME_RXUMA_HI, val);
2309}
2310
2311static int
2312jme_set_macaddr(struct net_device *netdev, void *p)
2313{
2314 struct jme_adapter *jme = netdev_priv(netdev);
2315 struct sockaddr *addr = p;
2316
2317 if (netif_running(netdev))
2318 return -EBUSY;
2319
2320 spin_lock_bh(&jme->macaddr_lock);
2321 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2322 jme_set_unicastaddr(netdev);
2323 spin_unlock_bh(&jme->macaddr_lock);
2324
2325 return 0;
2326}
2327
2328static void
2329jme_set_multi(struct net_device *netdev)
2330{
2331 struct jme_adapter *jme = netdev_priv(netdev);
2332 u32 mc_hash[2] = {};
2333#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2334 int i;
2335#endif
2336
2337 spin_lock_bh(&jme->rxmcs_lock);
2338
2339 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2340
2341 if (netdev->flags & IFF_PROMISC) {
2342 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2343 } else if (netdev->flags & IFF_ALLMULTI) {
2344 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2345 } else if (netdev->flags & IFF_MULTICAST) {
2346#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2347 struct dev_mc_list *mclist;
2348#else
2349 struct netdev_hw_addr *ha;
2350#endif
2351 int bit_nr;
2352
2353 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2354#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2355 for (i = 0, mclist = netdev->mc_list;
2356 mclist && i < netdev->mc_count;
2357 ++i, mclist = mclist->next) {
2358#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2359 netdev_for_each_mc_addr(mclist, netdev) {
2360#else
2361 netdev_for_each_mc_addr(ha, netdev) {
2362#endif
2363#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2364 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2365#else
2366 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2367#endif
2368 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2369 }
2370
2371 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2372 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2373 }
2374
2375 wmb();
2376 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2377
2378 spin_unlock_bh(&jme->rxmcs_lock);
2379}
2380
2381static int
2382jme_change_mtu(struct net_device *netdev, int new_mtu)
2383{
2384 struct jme_adapter *jme = netdev_priv(netdev);
2385
2386 if (new_mtu == jme->old_mtu)
2387 return 0;
2388
2389 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2390 ((new_mtu) < IPV6_MIN_MTU))
2391 return -EINVAL;
2392
2393 if (new_mtu > 4000) {
2394 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2395 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2396 jme_restart_rx_engine(jme);
2397 } else {
2398 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2399 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2400 jme_restart_rx_engine(jme);
2401 }
2402
2403 if (new_mtu > 1900) {
2404 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2405 NETIF_F_TSO | NETIF_F_TSO6);
2406 } else {
2407 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2408 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2409 if (test_bit(JME_FLAG_TSO, &jme->flags))
2410 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2411 }
2412
2413 netdev->mtu = new_mtu;
2414 jme_reset_link(jme);
2415
2416 return 0;
2417}
2418
2419static void
2420jme_tx_timeout(struct net_device *netdev)
2421{
2422 struct jme_adapter *jme = netdev_priv(netdev);
2423
2424 jme->phylink = 0;
2425 jme_reset_phy_processor(jme);
2426 if (test_bit(JME_FLAG_SSET, &jme->flags))
2427 jme_set_settings(netdev, &jme->old_ecmd);
2428
2429 /*
2430 * Force to Reset the link again
2431 */
2432 jme_reset_link(jme);
2433}
2434
2435static inline void jme_pause_rx(struct jme_adapter *jme)
2436{
2437 atomic_dec(&jme->link_changing);
2438
2439 jme_set_rx_pcc(jme, PCC_OFF);
2440 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2441 JME_NAPI_DISABLE(jme);
2442 } else {
2443 tasklet_disable(&jme->rxclean_task);
2444 tasklet_disable(&jme->rxempty_task);
2445 }
2446}
2447
2448static inline void jme_resume_rx(struct jme_adapter *jme)
2449{
2450 struct dynpcc_info *dpi = &(jme->dpi);
2451
2452 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2453 JME_NAPI_ENABLE(jme);
2454 } else {
2455 tasklet_hi_enable(&jme->rxclean_task);
2456 tasklet_hi_enable(&jme->rxempty_task);
2457 }
2458 dpi->cur = PCC_P1;
2459 dpi->attempt = PCC_P1;
2460 dpi->cnt = 0;
2461 jme_set_rx_pcc(jme, PCC_P1);
2462
2463 atomic_inc(&jme->link_changing);
2464}
2465
2466static void
2467jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2468{
2469 struct jme_adapter *jme = netdev_priv(netdev);
2470
2471 jme_pause_rx(jme);
2472 jme->vlgrp = grp;
2473 jme_resume_rx(jme);
2474}
2475
2476#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2477static void
2478jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2479{
2480 struct jme_adapter *jme = netdev_priv(netdev);
2481
2482 if(jme->vlgrp) {
2483 jme_pause_rx(jme);
2484#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2485 jme->vlgrp->vlan_devices[vid] = NULL;
2486#else
2487 vlan_group_set_device(jme->vlgrp, vid, NULL);
2488#endif
2489 jme_resume_rx(jme);
2490 }
2491}
2492#endif
2493
2494static void
2495jme_get_drvinfo(struct net_device *netdev,
2496 struct ethtool_drvinfo *info)
2497{
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499
2500 strcpy(info->driver, DRV_NAME);
2501 strcpy(info->version, DRV_VERSION);
2502 strcpy(info->bus_info, pci_name(jme->pdev));
2503}
2504
2505static int
2506jme_get_regs_len(struct net_device *netdev)
2507{
2508 return JME_REG_LEN;
2509}
2510
2511static void
2512mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2513{
2514 int i;
2515
2516 for (i = 0 ; i < len ; i += 4)
2517 p[i >> 2] = jread32(jme, reg + i);
2518}
2519
2520static void
2521mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2522{
2523 int i;
2524 u16 *p16 = (u16 *)p;
2525
2526 for (i = 0 ; i < reg_nr ; ++i)
2527 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2528}
2529
2530static void
2531jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2532{
2533 struct jme_adapter *jme = netdev_priv(netdev);
2534 u32 *p32 = (u32 *)p;
2535
2536 memset(p, 0xFF, JME_REG_LEN);
2537
2538 regs->version = 1;
2539 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2540
2541 p32 += 0x100 >> 2;
2542 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2543
2544 p32 += 0x100 >> 2;
2545 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2546
2547 p32 += 0x100 >> 2;
2548 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2549
2550 p32 += 0x100 >> 2;
2551 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2552
2553 p32 += 0x100 >> 2;
2554 jme_phyext_memcpy(jme, p32, JME_PHY_SPEC_REG_NR);
2555}
2556
2557static int
2558jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2559{
2560 struct jme_adapter *jme = netdev_priv(netdev);
2561
2562 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2563 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2564
2565 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2566 ecmd->use_adaptive_rx_coalesce = false;
2567 ecmd->rx_coalesce_usecs = 0;
2568 ecmd->rx_max_coalesced_frames = 0;
2569 return 0;
2570 }
2571
2572 ecmd->use_adaptive_rx_coalesce = true;
2573
2574 switch (jme->dpi.cur) {
2575 case PCC_P1:
2576 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2577 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2578 break;
2579 case PCC_P2:
2580 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2581 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2582 break;
2583 case PCC_P3:
2584 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2585 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2586 break;
2587 default:
2588 break;
2589 }
2590
2591 return 0;
2592}
2593
2594static int
2595jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2596{
2597 struct jme_adapter *jme = netdev_priv(netdev);
2598 struct dynpcc_info *dpi = &(jme->dpi);
2599
2600 if (netif_running(netdev))
2601 return -EBUSY;
2602
2603 if (ecmd->use_adaptive_rx_coalesce &&
2604 test_bit(JME_FLAG_POLL, &jme->flags)) {
2605 clear_bit(JME_FLAG_POLL, &jme->flags);
2606 jme->jme_rx = netif_rx;
2607 jme->jme_vlan_rx = vlan_hwaccel_rx;
2608 dpi->cur = PCC_P1;
2609 dpi->attempt = PCC_P1;
2610 dpi->cnt = 0;
2611 jme_set_rx_pcc(jme, PCC_P1);
2612 jme_interrupt_mode(jme);
2613 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2614 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2615 set_bit(JME_FLAG_POLL, &jme->flags);
2616 jme->jme_rx = netif_receive_skb;
2617 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2618 jme_interrupt_mode(jme);
2619 }
2620
2621 return 0;
2622}
2623
2624static void
2625jme_get_pauseparam(struct net_device *netdev,
2626 struct ethtool_pauseparam *ecmd)
2627{
2628 struct jme_adapter *jme = netdev_priv(netdev);
2629 u32 val;
2630
2631 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2632 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2633
2634 spin_lock_bh(&jme->phy_lock);
2635 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2636 spin_unlock_bh(&jme->phy_lock);
2637
2638 ecmd->autoneg =
2639 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2640}
2641
2642static int
2643jme_set_pauseparam(struct net_device *netdev,
2644 struct ethtool_pauseparam *ecmd)
2645{
2646 struct jme_adapter *jme = netdev_priv(netdev);
2647 u32 val;
2648
2649 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2650 (ecmd->tx_pause != 0)) {
2651
2652 if (ecmd->tx_pause)
2653 jme->reg_txpfc |= TXPFC_PF_EN;
2654 else
2655 jme->reg_txpfc &= ~TXPFC_PF_EN;
2656
2657 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2658 }
2659
2660 spin_lock_bh(&jme->rxmcs_lock);
2661 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2662 (ecmd->rx_pause != 0)) {
2663
2664 if (ecmd->rx_pause)
2665 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2666 else
2667 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2668
2669 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2670 }
2671 spin_unlock_bh(&jme->rxmcs_lock);
2672
2673 spin_lock_bh(&jme->phy_lock);
2674 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2675 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2676 (ecmd->autoneg != 0)) {
2677
2678 if (ecmd->autoneg)
2679 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2680 else
2681 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2682
2683 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2684 MII_ADVERTISE, val);
2685 }
2686 spin_unlock_bh(&jme->phy_lock);
2687
2688 return 0;
2689}
2690
2691static void
2692jme_get_wol(struct net_device *netdev,
2693 struct ethtool_wolinfo *wol)
2694{
2695 struct jme_adapter *jme = netdev_priv(netdev);
2696
2697 wol->supported = WAKE_MAGIC | WAKE_PHY;
2698
2699 wol->wolopts = 0;
2700
2701 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2702 wol->wolopts |= WAKE_PHY;
2703
2704 if (jme->reg_pmcs & PMCS_MFEN)
2705 wol->wolopts |= WAKE_MAGIC;
2706
2707}
2708
2709static int
2710jme_set_wol(struct net_device *netdev,
2711 struct ethtool_wolinfo *wol)
2712{
2713 struct jme_adapter *jme = netdev_priv(netdev);
2714
2715 if (wol->wolopts & (WAKE_MAGICSECURE |
2716 WAKE_UCAST |
2717 WAKE_MCAST |
2718 WAKE_BCAST |
2719 WAKE_ARP))
2720 return -EOPNOTSUPP;
2721
2722 jme->reg_pmcs = 0;
2723
2724 if (wol->wolopts & WAKE_PHY)
2725 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2726
2727 if (wol->wolopts & WAKE_MAGIC)
2728 jme->reg_pmcs |= PMCS_MFEN;
2729
2730 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2731
2732 return 0;
2733}
2734
2735static int
2736jme_get_settings(struct net_device *netdev,
2737 struct ethtool_cmd *ecmd)
2738{
2739 struct jme_adapter *jme = netdev_priv(netdev);
2740 int rc;
2741
2742 spin_lock_bh(&jme->phy_lock);
2743 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2744 spin_unlock_bh(&jme->phy_lock);
2745 return rc;
2746}
2747
2748static int
2749jme_set_settings(struct net_device *netdev,
2750 struct ethtool_cmd *ecmd)
2751{
2752 struct jme_adapter *jme = netdev_priv(netdev);
2753 int rc, fdc = 0;
2754
2755 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2756 return -EINVAL;
2757
2758 /*
2759 * Check If user changed duplex only while force_media.
2760 * Hardware would not generate link change interrupt.
2761 */
2762 if (jme->mii_if.force_media &&
2763 ecmd->autoneg != AUTONEG_ENABLE &&
2764 (jme->mii_if.full_duplex != ecmd->duplex))
2765 fdc = 1;
2766
2767 spin_lock_bh(&jme->phy_lock);
2768 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2769 spin_unlock_bh(&jme->phy_lock);
2770
2771 if (!rc) {
2772 if (fdc)
2773 jme_reset_link(jme);
2774 jme->old_ecmd = *ecmd;
2775 set_bit(JME_FLAG_SSET, &jme->flags);
2776 }
2777
2778 return rc;
2779}
2780
2781static int
2782jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2783{
2784 int rc;
2785 struct jme_adapter *jme = netdev_priv(netdev);
2786 struct mii_ioctl_data *mii_data = if_mii(rq);
2787 unsigned int duplex_chg;
2788
2789 if (cmd == SIOCSMIIREG) {
2790 u16 val = mii_data->val_in;
2791 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2792 (val & BMCR_SPEED1000))
2793 return -EINVAL;
2794 }
2795
2796 spin_lock_bh(&jme->phy_lock);
2797 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2798 spin_unlock_bh(&jme->phy_lock);
2799
2800 if (!rc && (cmd == SIOCSMIIREG)) {
2801 if (duplex_chg)
2802 jme_reset_link(jme);
2803 jme_get_settings(netdev, &jme->old_ecmd);
2804 set_bit(JME_FLAG_SSET, &jme->flags);
2805 }
2806
2807 return rc;
2808}
2809
2810static u32
2811jme_get_link(struct net_device *netdev)
2812{
2813 struct jme_adapter *jme = netdev_priv(netdev);
2814 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2815}
2816
2817static u32
2818jme_get_msglevel(struct net_device *netdev)
2819{
2820 struct jme_adapter *jme = netdev_priv(netdev);
2821 return jme->msg_enable;
2822}
2823
2824static void
2825jme_set_msglevel(struct net_device *netdev, u32 value)
2826{
2827 struct jme_adapter *jme = netdev_priv(netdev);
2828 jme->msg_enable = value;
2829}
2830
2831static u32
2832jme_get_rx_csum(struct net_device *netdev)
2833{
2834 struct jme_adapter *jme = netdev_priv(netdev);
2835 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2836}
2837
2838static int
2839jme_set_rx_csum(struct net_device *netdev, u32 on)
2840{
2841 struct jme_adapter *jme = netdev_priv(netdev);
2842
2843 spin_lock_bh(&jme->rxmcs_lock);
2844 if (on)
2845 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2846 else
2847 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2848 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2849 spin_unlock_bh(&jme->rxmcs_lock);
2850
2851 return 0;
2852}
2853
2854static int
2855jme_set_tx_csum(struct net_device *netdev, u32 on)
2856{
2857 struct jme_adapter *jme = netdev_priv(netdev);
2858
2859 if (on) {
2860 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2861 if (netdev->mtu <= 1900)
2862 netdev->features |=
2863 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2864 } else {
2865 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2866 netdev->features &=
2867 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2868 }
2869
2870 return 0;
2871}
2872
2873static int
2874jme_set_tso(struct net_device *netdev, u32 on)
2875{
2876 struct jme_adapter *jme = netdev_priv(netdev);
2877
2878 if (on) {
2879 set_bit(JME_FLAG_TSO, &jme->flags);
2880 if (netdev->mtu <= 1900)
2881 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2882 } else {
2883 clear_bit(JME_FLAG_TSO, &jme->flags);
2884 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2885 }
2886
2887 return 0;
2888}
2889
2890static int
2891jme_nway_reset(struct net_device *netdev)
2892{
2893 struct jme_adapter *jme = netdev_priv(netdev);
2894 jme_restart_an(jme);
2895 return 0;
2896}
2897
2898static u8
2899jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2900{
2901 u32 val;
2902 int to;
2903
2904 val = jread32(jme, JME_SMBCSR);
2905 to = JME_SMB_BUSY_TIMEOUT;
2906 while ((val & SMBCSR_BUSY) && --to) {
2907 msleep(1);
2908 val = jread32(jme, JME_SMBCSR);
2909 }
2910 if (!to) {
2911 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2912 return 0xFF;
2913 }
2914
2915 jwrite32(jme, JME_SMBINTF,
2916 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2917 SMBINTF_HWRWN_READ |
2918 SMBINTF_HWCMD);
2919
2920 val = jread32(jme, JME_SMBINTF);
2921 to = JME_SMB_BUSY_TIMEOUT;
2922 while ((val & SMBINTF_HWCMD) && --to) {
2923 msleep(1);
2924 val = jread32(jme, JME_SMBINTF);
2925 }
2926 if (!to) {
2927 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2928 return 0xFF;
2929 }
2930
2931 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2932}
2933
2934static void
2935jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2936{
2937 u32 val;
2938 int to;
2939
2940 val = jread32(jme, JME_SMBCSR);
2941 to = JME_SMB_BUSY_TIMEOUT;
2942 while ((val & SMBCSR_BUSY) && --to) {
2943 msleep(1);
2944 val = jread32(jme, JME_SMBCSR);
2945 }
2946 if (!to) {
2947 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2948 return;
2949 }
2950
2951 jwrite32(jme, JME_SMBINTF,
2952 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2953 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2954 SMBINTF_HWRWN_WRITE |
2955 SMBINTF_HWCMD);
2956
2957 val = jread32(jme, JME_SMBINTF);
2958 to = JME_SMB_BUSY_TIMEOUT;
2959 while ((val & SMBINTF_HWCMD) && --to) {
2960 msleep(1);
2961 val = jread32(jme, JME_SMBINTF);
2962 }
2963 if (!to) {
2964 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2965 return;
2966 }
2967
2968 mdelay(2);
2969}
2970
2971static int
2972jme_get_eeprom_len(struct net_device *netdev)
2973{
2974 struct jme_adapter *jme = netdev_priv(netdev);
2975 u32 val;
2976 val = jread32(jme, JME_SMBCSR);
2977 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2978}
2979
2980static int
2981jme_get_eeprom(struct net_device *netdev,
2982 struct ethtool_eeprom *eeprom, u8 *data)
2983{
2984 struct jme_adapter *jme = netdev_priv(netdev);
2985 int i, offset = eeprom->offset, len = eeprom->len;
2986
2987 /*
2988 * ethtool will check the boundary for us
2989 */
2990 eeprom->magic = JME_EEPROM_MAGIC;
2991 for (i = 0 ; i < len ; ++i)
2992 data[i] = jme_smb_read(jme, i + offset);
2993
2994 return 0;
2995}
2996
2997static int
2998jme_set_eeprom(struct net_device *netdev,
2999 struct ethtool_eeprom *eeprom, u8 *data)
3000{
3001 struct jme_adapter *jme = netdev_priv(netdev);
3002 int i, offset = eeprom->offset, len = eeprom->len;
3003
3004 if (eeprom->magic != JME_EEPROM_MAGIC)
3005 return -EINVAL;
3006
3007 /*
3008 * ethtool will check the boundary for us
3009 */
3010 for (i = 0 ; i < len ; ++i)
3011 jme_smb_write(jme, i + offset, data[i]);
3012
3013 return 0;
3014}
3015
3016#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
3017static struct ethtool_ops jme_ethtool_ops = {
3018#else
3019static const struct ethtool_ops jme_ethtool_ops = {
3020#endif
3021 .get_drvinfo = jme_get_drvinfo,
3022 .get_regs_len = jme_get_regs_len,
3023 .get_regs = jme_get_regs,
3024 .get_coalesce = jme_get_coalesce,
3025 .set_coalesce = jme_set_coalesce,
3026 .get_pauseparam = jme_get_pauseparam,
3027 .set_pauseparam = jme_set_pauseparam,
3028 .get_wol = jme_get_wol,
3029 .set_wol = jme_set_wol,
3030 .get_settings = jme_get_settings,
3031 .set_settings = jme_set_settings,
3032 .get_link = jme_get_link,
3033 .get_msglevel = jme_get_msglevel,
3034 .set_msglevel = jme_set_msglevel,
3035 .get_rx_csum = jme_get_rx_csum,
3036 .set_rx_csum = jme_set_rx_csum,
3037 .set_tx_csum = jme_set_tx_csum,
3038 .set_tso = jme_set_tso,
3039 .set_sg = ethtool_op_set_sg,
3040 .nway_reset = jme_nway_reset,
3041 .get_eeprom_len = jme_get_eeprom_len,
3042 .get_eeprom = jme_get_eeprom,
3043 .set_eeprom = jme_set_eeprom,
3044};
3045
3046static int
3047jme_pci_dma64(struct pci_dev *pdev)
3048{
3049 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3050#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3051 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
3052#else
3053 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
3054#endif
3055 )
3056#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3057 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
3058#else
3059 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
3060#endif
3061 return 1;
3062
3063 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
3064#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3065 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3066#else
3067 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3068#endif
3069 )
3070#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3071 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3072#else
3073 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3074#endif
3075 return 1;
3076
3077#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3078 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3079 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3080#else
3081 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3082 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3083#endif
3084 return 0;
3085
3086 return -1;
3087}
3088
3089static inline void
3090jme_phy_init(struct jme_adapter *jme)
3091{
3092 u16 reg26;
3093
3094 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3095 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3096}
3097
3098static inline void
3099jme_check_hw_ver(struct jme_adapter *jme)
3100{
3101 u32 chipmode;
3102
3103 chipmode = jread32(jme, JME_CHIPMODE);
3104
3105 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3106 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3107 jme->chip_main_rev = jme->chiprev & 0xF;
3108 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3109}
3110
3111#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3112static const struct net_device_ops jme_netdev_ops = {
3113 .ndo_open = jme_open,
3114 .ndo_stop = jme_close,
3115 .ndo_validate_addr = eth_validate_addr,
3116 .ndo_do_ioctl = jme_ioctl,
3117 .ndo_start_xmit = jme_start_xmit,
3118 .ndo_set_mac_address = jme_set_macaddr,
3119 .ndo_set_multicast_list = jme_set_multi,
3120 .ndo_change_mtu = jme_change_mtu,
3121 .ndo_tx_timeout = jme_tx_timeout,
3122 .ndo_vlan_rx_register = jme_vlan_rx_register,
3123};
3124#endif
3125
3126static int __devinit
3127jme_init_one(struct pci_dev *pdev,
3128 const struct pci_device_id *ent)
3129{
3130 int rc = 0, using_dac, i;
3131 struct net_device *netdev;
3132 struct jme_adapter *jme;
3133 u16 bmcr, bmsr;
3134 u32 apmc;
3135
3136 /*
3137 * set up PCI device basics
3138 */
3139 rc = pci_enable_device(pdev);
3140 if (rc) {
3141 pr_err("Cannot enable PCI device\n");
3142 goto err_out;
3143 }
3144
3145 using_dac = jme_pci_dma64(pdev);
3146 if (using_dac < 0) {
3147 pr_err("Cannot set PCI DMA Mask\n");
3148 rc = -EIO;
3149 goto err_out_disable_pdev;
3150 }
3151
3152 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3153 pr_err("No PCI resource region found\n");
3154 rc = -ENOMEM;
3155 goto err_out_disable_pdev;
3156 }
3157
3158 rc = pci_request_regions(pdev, DRV_NAME);
3159 if (rc) {
3160 pr_err("Cannot obtain PCI resource region\n");
3161 goto err_out_disable_pdev;
3162 }
3163
3164 pci_set_master(pdev);
3165
3166 /*
3167 * alloc and init net device
3168 */
3169 netdev = alloc_etherdev(sizeof(*jme));
3170 if (!netdev) {
3171 pr_err("Cannot allocate netdev structure\n");
3172 rc = -ENOMEM;
3173 goto err_out_release_regions;
3174 }
3175#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3176 netdev->netdev_ops = &jme_netdev_ops;
3177#else
3178 netdev->open = jme_open;
3179 netdev->stop = jme_close;
3180 netdev->do_ioctl = jme_ioctl;
3181 netdev->hard_start_xmit = jme_start_xmit;
3182 netdev->set_mac_address = jme_set_macaddr;
3183 netdev->set_multicast_list = jme_set_multi;
3184 netdev->change_mtu = jme_change_mtu;
3185 netdev->tx_timeout = jme_tx_timeout;
3186 netdev->vlan_rx_register = jme_vlan_rx_register;
3187#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3188 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3189#endif
3190 NETDEV_GET_STATS(netdev, &jme_get_stats);
3191#endif
3192 netdev->ethtool_ops = &jme_ethtool_ops;
3193 netdev->watchdog_timeo = TX_TIMEOUT;
3194 netdev->features = NETIF_F_IP_CSUM |
3195 NETIF_F_IPV6_CSUM |
3196 NETIF_F_SG |
3197 NETIF_F_TSO |
3198 NETIF_F_TSO6 |
3199 NETIF_F_HW_VLAN_TX |
3200 NETIF_F_HW_VLAN_RX;
3201 if (using_dac)
3202 netdev->features |= NETIF_F_HIGHDMA;
3203
3204 SET_NETDEV_DEV(netdev, &pdev->dev);
3205 pci_set_drvdata(pdev, netdev);
3206
3207 /*
3208 * init adapter info
3209 */
3210 jme = netdev_priv(netdev);
3211 jme->pdev = pdev;
3212 jme->dev = netdev;
3213 jme->jme_rx = netif_rx;
3214 jme->jme_vlan_rx = vlan_hwaccel_rx;
3215 jme->old_mtu = netdev->mtu = 1500;
3216 jme->phylink = 0;
3217 jme->tx_ring_size = 1 << 10;
3218 jme->tx_ring_mask = jme->tx_ring_size - 1;
3219 jme->tx_wake_threshold = 1 << 9;
3220 jme->rx_ring_size = 1 << 9;
3221 jme->rx_ring_mask = jme->rx_ring_size - 1;
3222 jme->msg_enable = JME_DEF_MSG_ENABLE;
3223 jme->regs = ioremap(pci_resource_start(pdev, 0),
3224 pci_resource_len(pdev, 0));
3225 if (!(jme->regs)) {
3226 pr_err("Mapping PCI resource region error\n");
3227 rc = -ENOMEM;
3228 goto err_out_free_netdev;
3229 }
3230
3231 if (no_pseudohp) {
3232 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3233 jwrite32(jme, JME_APMC, apmc);
3234 } else if (force_pseudohp) {
3235 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3236 jwrite32(jme, JME_APMC, apmc);
3237 }
3238
3239 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3240
3241 spin_lock_init(&jme->phy_lock);
3242 spin_lock_init(&jme->macaddr_lock);
3243 spin_lock_init(&jme->rxmcs_lock);
3244
3245 atomic_set(&jme->link_changing, 1);
3246 atomic_set(&jme->rx_cleaning, 1);
3247 atomic_set(&jme->tx_cleaning, 1);
3248 atomic_set(&jme->rx_empty, 1);
3249
3250 tasklet_init(&jme->pcc_task,
3251 jme_pcc_tasklet,
3252 (unsigned long) jme);
3253 tasklet_init(&jme->linkch_task,
3254 jme_link_change_tasklet,
3255 (unsigned long) jme);
3256 tasklet_init(&jme->txclean_task,
3257 jme_tx_clean_tasklet,
3258 (unsigned long) jme);
3259 tasklet_init(&jme->rxclean_task,
3260 jme_rx_clean_tasklet,
3261 (unsigned long) jme);
3262 tasklet_init(&jme->rxempty_task,
3263 jme_rx_empty_tasklet,
3264 (unsigned long) jme);
3265 tasklet_disable_nosync(&jme->linkch_task);
3266 tasklet_disable_nosync(&jme->txclean_task);
3267 tasklet_disable_nosync(&jme->rxclean_task);
3268 tasklet_disable_nosync(&jme->rxempty_task);
3269 jme->dpi.cur = PCC_P1;
3270
3271 jme->reg_ghc = 0;
3272 jme->reg_rxcs = RXCS_DEFAULT;
3273 jme->reg_rxmcs = RXMCS_DEFAULT;
3274 jme->reg_txpfc = 0;
3275 jme->reg_pmcs = PMCS_MFEN;
3276 jme->reg_gpreg1 = GPREG1_DEFAULT;
3277 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3278 set_bit(JME_FLAG_TSO, &jme->flags);
3279
3280 /*
3281 * Get Max Read Req Size from PCI Config Space
3282 */
3283 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3284 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3285 switch (jme->mrrs) {
3286 case MRRS_128B:
3287 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3288 break;
3289 case MRRS_256B:
3290 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3291 break;
3292 default:
3293 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3294 break;
3295 }
3296
3297 /*
3298 * Must check before reset_mac_processor
3299 */
3300 jme_check_hw_ver(jme);
3301 jme->mii_if.dev = netdev;
3302 if (jme->fpgaver) {
3303 jme->mii_if.phy_id = 0;
3304 for (i = 1 ; i < 32 ; ++i) {
3305 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3306 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3307 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3308 jme->mii_if.phy_id = i;
3309 break;
3310 }
3311 }
3312
3313 if (!jme->mii_if.phy_id) {
3314 rc = -EIO;
3315 pr_err("Can not find phy_id\n");
3316 goto err_out_unmap;
3317 }
3318
3319 jme->reg_ghc |= GHC_LINK_POLL;
3320 } else {
3321 jme->mii_if.phy_id = 1;
3322 }
3323 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3324 jme->mii_if.supports_gmii = true;
3325 else
3326 jme->mii_if.supports_gmii = false;
3327 jme->mii_if.phy_id_mask = 0x1F;
3328 jme->mii_if.reg_num_mask = 0x1F;
3329 jme->mii_if.mdio_read = jme_mdio_read;
3330 jme->mii_if.mdio_write = jme_mdio_write;
3331
3332 jme_clear_pm(jme);
3333 jme_set_phyfifo_5level(jme);
3334 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3335 if (!jme->fpgaver)
3336 jme_phy_init(jme);
3337 jme_phy_off(jme);
3338
3339 /*
3340 * Reset MAC processor and reload EEPROM for MAC Address
3341 */
3342 jme_reset_mac_processor(jme);
3343 rc = jme_reload_eeprom(jme);
3344 if (rc) {
3345 pr_err("Reload eeprom for reading MAC Address error\n");
3346 goto err_out_unmap;
3347 }
3348 jme_load_macaddr(netdev);
3349
3350 /*
3351 * Tell stack that we are not ready to work until open()
3352 */
3353 netif_carrier_off(netdev);
3354
3355 rc = register_netdev(netdev);
3356 if (rc) {
3357 pr_err("Cannot register net device\n");
3358 goto err_out_unmap;
3359 }
3360
3361 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3362 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3363 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3364 "JMC250 Gigabit Ethernet" :
3365 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3366 "JMC260 Fast Ethernet" : "Unknown",
3367 (jme->fpgaver != 0) ? " (FPGA)" : "",
3368 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3369 jme->pcirev,
3370 netdev->dev_addr[0],
3371 netdev->dev_addr[1],
3372 netdev->dev_addr[2],
3373 netdev->dev_addr[3],
3374 netdev->dev_addr[4],
3375 netdev->dev_addr[5]);
3376
3377 return 0;
3378
3379err_out_unmap:
3380 iounmap(jme->regs);
3381err_out_free_netdev:
3382 pci_set_drvdata(pdev, NULL);
3383 free_netdev(netdev);
3384err_out_release_regions:
3385 pci_release_regions(pdev);
3386err_out_disable_pdev:
3387 pci_disable_device(pdev);
3388err_out:
3389 return rc;
3390}
3391
3392static void __devexit
3393jme_remove_one(struct pci_dev *pdev)
3394{
3395 struct net_device *netdev = pci_get_drvdata(pdev);
3396 struct jme_adapter *jme = netdev_priv(netdev);
3397
3398 unregister_netdev(netdev);
3399 iounmap(jme->regs);
3400 pci_set_drvdata(pdev, NULL);
3401 free_netdev(netdev);
3402 pci_release_regions(pdev);
3403 pci_disable_device(pdev);
3404
3405}
3406
3407static void
3408jme_shutdown(struct pci_dev *pdev)
3409{
3410 struct net_device *netdev = pci_get_drvdata(pdev);
3411 struct jme_adapter *jme = netdev_priv(netdev);
3412
3413 jme_powersave_phy(jme);
3414#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3415 pci_enable_wake(pdev, PCI_D3hot, true);
3416#else
3417 pci_pme_active(pdev, true);
3418#endif
3419}
3420
3421#ifdef CONFIG_PM
3422static int
3423jme_suspend(struct pci_dev *pdev, pm_message_t state)
3424{
3425 struct net_device *netdev = pci_get_drvdata(pdev);
3426 struct jme_adapter *jme = netdev_priv(netdev);
3427
3428 atomic_dec(&jme->link_changing);
3429
3430 netif_device_detach(netdev);
3431 netif_stop_queue(netdev);
3432 jme_stop_irq(jme);
3433
3434 tasklet_disable(&jme->txclean_task);
3435 tasklet_disable(&jme->rxclean_task);
3436 tasklet_disable(&jme->rxempty_task);
3437
3438 if (netif_carrier_ok(netdev)) {
3439 if (test_bit(JME_FLAG_POLL, &jme->flags))
3440 jme_polling_mode(jme);
3441
3442 jme_stop_pcc_timer(jme);
3443 jme_disable_rx_engine(jme);
3444 jme_disable_tx_engine(jme);
3445 jme_reset_mac_processor(jme);
3446 jme_free_rx_resources(jme);
3447 jme_free_tx_resources(jme);
3448 netif_carrier_off(netdev);
3449 jme->phylink = 0;
3450 }
3451
3452 tasklet_enable(&jme->txclean_task);
3453 tasklet_hi_enable(&jme->rxclean_task);
3454 tasklet_hi_enable(&jme->rxempty_task);
3455
3456 pci_save_state(pdev);
3457 jme_powersave_phy(jme);
3458#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3459 pci_enable_wake(pdev, PCI_D3hot, true);
3460#else
3461 pci_pme_active(pdev, true);
3462#endif
3463 pci_set_power_state(pdev, PCI_D3hot);
3464
3465 return 0;
3466}
3467
3468static int
3469jme_resume(struct pci_dev *pdev)
3470{
3471 struct net_device *netdev = pci_get_drvdata(pdev);
3472 struct jme_adapter *jme = netdev_priv(netdev);
3473
3474 jme_clear_pm(jme);
3475 pci_restore_state(pdev);
3476
3477 jme_phy_on(jme);
3478 if (test_bit(JME_FLAG_SSET, &jme->flags))
3479 jme_set_settings(netdev, &jme->old_ecmd);
3480 else
3481 jme_reset_phy_processor(jme);
3482
3483 jme_start_irq(jme);
3484 netif_device_attach(netdev);
3485
3486 atomic_inc(&jme->link_changing);
3487
3488 jme_reset_link(jme);
3489
3490 return 0;
3491}
3492#endif
3493
3494#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3495static struct pci_device_id jme_pci_tbl[] = {
3496#else
3497static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3498#endif
3499 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3500 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3501 { }
3502};
3503
3504static struct pci_driver jme_driver = {
3505 .name = DRV_NAME,
3506 .id_table = jme_pci_tbl,
3507 .probe = jme_init_one,
3508 .remove = __devexit_p(jme_remove_one),
3509#ifdef CONFIG_PM
3510 .suspend = jme_suspend,
3511 .resume = jme_resume,
3512#endif /* CONFIG_PM */
3513 .shutdown = jme_shutdown,
3514};
3515
3516static int __init
3517jme_init_module(void)
3518{
3519 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3520 return pci_register_driver(&jme_driver);
3521}
3522
3523static void __exit
3524jme_cleanup_module(void)
3525{
3526 pci_unregister_driver(&jme_driver);
3527}
3528
3529module_init(jme_init_module);
3530module_exit(jme_cleanup_module);
3531
3532MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3533MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3534MODULE_LICENSE("GPL");
3535MODULE_VERSION(DRV_VERSION);
3536MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3537
JMicron Ethernet Linux driver