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jme: Fix hardware action of full-duplex
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1/*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25#include <linux/version.h>
26#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
28#endif
29
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/pci.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/mii.h>
37#include <linux/crc32.h>
38#include <linux/delay.h>
39#include <linux/spinlock.h>
40#include <linux/in.h>
41#include <linux/ip.h>
42#include <linux/ipv6.h>
43#include <linux/tcp.h>
44#include <linux/udp.h>
45#include <linux/if_vlan.h>
46#include <linux/slab.h>
47#include <net/ip6_checksum.h>
48#include "jme.h"
49
50static int force_pseudohp = -1;
51static int no_pseudohp = -1;
52static int no_extplug = -1;
53module_param(force_pseudohp, int, 0);
54MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56module_param(no_pseudohp, int, 0);
57MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58module_param(no_extplug, int, 0);
59MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
61
62static int
63jme_mdio_read(struct net_device *netdev, int phy, int reg)
64{
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
67
68read_again:
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
70 smi_phy_addr(phy) |
71 smi_reg_addr(reg));
72
73 wmb();
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
75 udelay(20);
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
78 break;
79 }
80
81 if (i == 0) {
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
83 return 0;
84 }
85
86 if (again--)
87 goto read_again;
88
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
90}
91
92static void
93jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
95{
96 struct jme_adapter *jme = netdev_priv(netdev);
97 int i;
98
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
102
103 wmb();
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
105 udelay(20);
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
107 break;
108 }
109
110 if (i == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
112}
113
114static inline void
115jme_reset_phy_processor(struct jme_adapter *jme)
116{
117 u32 val;
118
119 jme_mdio_write(jme->dev,
120 jme->mii_if.phy_id,
121 MII_ADVERTISE, ADVERTISE_ALL |
122 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
123
124 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
125 jme_mdio_write(jme->dev,
126 jme->mii_if.phy_id,
127 MII_CTRL1000,
128 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
129
130 val = jme_mdio_read(jme->dev,
131 jme->mii_if.phy_id,
132 MII_BMCR);
133
134 jme_mdio_write(jme->dev,
135 jme->mii_if.phy_id,
136 MII_BMCR, val | BMCR_RESET);
137}
138
139static void
140jme_setup_wakeup_frame(struct jme_adapter *jme,
141 const u32 *mask, u32 crc, int fnr)
142{
143 int i;
144
145 /*
146 * Setup CRC pattern
147 */
148 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
149 wmb();
150 jwrite32(jme, JME_WFODP, crc);
151 wmb();
152
153 /*
154 * Setup Mask
155 */
156 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
157 jwrite32(jme, JME_WFOI,
158 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
159 (fnr & WFOI_FRAME_SEL));
160 wmb();
161 jwrite32(jme, JME_WFODP, mask[i]);
162 wmb();
163 }
164}
165
166static inline void
167jme_reset_mac_processor(struct jme_adapter *jme)
168{
169 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
170 u32 crc = 0xCDCDCDCD;
171 u32 gpreg0;
172 int i;
173
174 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
175 udelay(2);
176 jwrite32(jme, JME_GHC, jme->reg_ghc);
177
178 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
179 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
180 jwrite32(jme, JME_RXQDC, 0x00000000);
181 jwrite32(jme, JME_RXNDA, 0x00000000);
182 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
183 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
184 jwrite32(jme, JME_TXQDC, 0x00000000);
185 jwrite32(jme, JME_TXNDA, 0x00000000);
186
187 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
188 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
189 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
190 jme_setup_wakeup_frame(jme, mask, crc, i);
191 if (jme->fpgaver)
192 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
193 else
194 gpreg0 = GPREG0_DEFAULT;
195 jwrite32(jme, JME_GPREG0, gpreg0);
196 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197}
198
199static inline void
200jme_reset_ghc_speed(struct jme_adapter *jme)
201{
202 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
203 jwrite32(jme, JME_GHC, jme->reg_ghc);
204}
205
206static inline void
207jme_clear_pm(struct jme_adapter *jme)
208{
209 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
210 pci_set_power_state(jme->pdev, PCI_D0);
211 pci_enable_wake(jme->pdev, PCI_D0, false);
212}
213
214static int
215jme_reload_eeprom(struct jme_adapter *jme)
216{
217 u32 val;
218 int i;
219
220 val = jread32(jme, JME_SMBCSR);
221
222 if (val & SMBCSR_EEPROMD) {
223 val |= SMBCSR_CNACK;
224 jwrite32(jme, JME_SMBCSR, val);
225 val |= SMBCSR_RELOAD;
226 jwrite32(jme, JME_SMBCSR, val);
227 mdelay(12);
228
229 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
230 mdelay(1);
231 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
232 break;
233 }
234
235 if (i == 0) {
236 pr_err("eeprom reload timeout\n");
237 return -EIO;
238 }
239 }
240
241 return 0;
242}
243
244static void
245jme_load_macaddr(struct net_device *netdev)
246{
247 struct jme_adapter *jme = netdev_priv(netdev);
248 unsigned char macaddr[6];
249 u32 val;
250
251 spin_lock_bh(&jme->macaddr_lock);
252 val = jread32(jme, JME_RXUMA_LO);
253 macaddr[0] = (val >> 0) & 0xFF;
254 macaddr[1] = (val >> 8) & 0xFF;
255 macaddr[2] = (val >> 16) & 0xFF;
256 macaddr[3] = (val >> 24) & 0xFF;
257 val = jread32(jme, JME_RXUMA_HI);
258 macaddr[4] = (val >> 0) & 0xFF;
259 macaddr[5] = (val >> 8) & 0xFF;
260 memcpy(netdev->dev_addr, macaddr, 6);
261 spin_unlock_bh(&jme->macaddr_lock);
262}
263
264static inline void
265jme_set_rx_pcc(struct jme_adapter *jme, int p)
266{
267 switch (p) {
268 case PCC_OFF:
269 jwrite32(jme, JME_PCCRX0,
270 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
271 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
272 break;
273 case PCC_P1:
274 jwrite32(jme, JME_PCCRX0,
275 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
276 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
277 break;
278 case PCC_P2:
279 jwrite32(jme, JME_PCCRX0,
280 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
281 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
282 break;
283 case PCC_P3:
284 jwrite32(jme, JME_PCCRX0,
285 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
286 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
287 break;
288 default:
289 break;
290 }
291 wmb();
292
293 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
294 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
295}
296
297static void
298jme_start_irq(struct jme_adapter *jme)
299{
300 register struct dynpcc_info *dpi = &(jme->dpi);
301
302 jme_set_rx_pcc(jme, PCC_P1);
303 dpi->cur = PCC_P1;
304 dpi->attempt = PCC_P1;
305 dpi->cnt = 0;
306
307 jwrite32(jme, JME_PCCTX,
308 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
309 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
310 PCCTXQ0_EN
311 );
312
313 /*
314 * Enable Interrupts
315 */
316 jwrite32(jme, JME_IENS, INTR_ENABLE);
317}
318
319static inline void
320jme_stop_irq(struct jme_adapter *jme)
321{
322 /*
323 * Disable Interrupts
324 */
325 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326}
327
328static u32
329jme_linkstat_from_phy(struct jme_adapter *jme)
330{
331 u32 phylink, bmsr;
332
333 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
334 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
335 if (bmsr & BMSR_ANCOMP)
336 phylink |= PHY_LINK_AUTONEG_COMPLETE;
337
338 return phylink;
339}
340
341static inline void
342jme_set_phyfifo_5level(struct jme_adapter *jme)
343{
344 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345}
346
347static inline void
348jme_set_phyfifo_8level(struct jme_adapter *jme)
349{
350 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351}
352
353static int
354jme_check_link(struct net_device *netdev, int testonly)
355{
356 struct jme_adapter *jme = netdev_priv(netdev);
357 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
358 char linkmsg[64];
359 int rc = 0;
360
361 linkmsg[0] = '\0';
362
363 if (jme->fpgaver)
364 phylink = jme_linkstat_from_phy(jme);
365 else
366 phylink = jread32(jme, JME_PHY_LINK);
367
368 if (phylink & PHY_LINK_UP) {
369 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
370 /*
371 * If we did not enable AN
372 * Speed/Duplex Info should be obtained from SMI
373 */
374 phylink = PHY_LINK_UP;
375
376 bmcr = jme_mdio_read(jme->dev,
377 jme->mii_if.phy_id,
378 MII_BMCR);
379
380 phylink |= ((bmcr & BMCR_SPEED1000) &&
381 (bmcr & BMCR_SPEED100) == 0) ?
382 PHY_LINK_SPEED_1000M :
383 (bmcr & BMCR_SPEED100) ?
384 PHY_LINK_SPEED_100M :
385 PHY_LINK_SPEED_10M;
386
387 phylink |= (bmcr & BMCR_FULLDPLX) ?
388 PHY_LINK_DUPLEX : 0;
389
390 strcat(linkmsg, "Forced: ");
391 } else {
392 /*
393 * Keep polling for speed/duplex resolve complete
394 */
395 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
396 --cnt) {
397
398 udelay(1);
399
400 if (jme->fpgaver)
401 phylink = jme_linkstat_from_phy(jme);
402 else
403 phylink = jread32(jme, JME_PHY_LINK);
404 }
405 if (!cnt)
406 pr_err("Waiting speed resolve timeout\n");
407
408 strcat(linkmsg, "ANed: ");
409 }
410
411 if (jme->phylink == phylink) {
412 rc = 1;
413 goto out;
414 }
415 if (testonly)
416 goto out;
417
418 jme->phylink = phylink;
419
420 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
421 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
422 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
423 switch (phylink & PHY_LINK_SPEED_MASK) {
424 case PHY_LINK_SPEED_10M:
425 ghc |= GHC_SPEED_10M |
426 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
427 strcat(linkmsg, "10 Mbps, ");
428 break;
429 case PHY_LINK_SPEED_100M:
430 ghc |= GHC_SPEED_100M |
431 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
432 strcat(linkmsg, "100 Mbps, ");
433 break;
434 case PHY_LINK_SPEED_1000M:
435 ghc |= GHC_SPEED_1000M |
436 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
437 strcat(linkmsg, "1000 Mbps, ");
438 break;
439 default:
440 break;
441 }
442
443 if (phylink & PHY_LINK_DUPLEX) {
444 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
446 ghc |= GHC_DPX;
447 } else {
448 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
449 TXMCS_BACKOFF |
450 TXMCS_CARRIERSENSE |
451 TXMCS_COLLISION);
452 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
453 }
454
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifo_8level(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
463 break;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifo_5level(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
467 break;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifo_8level(jme);
470 break;
471 default:
472 break;
473 }
474 }
475
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
478 jme->reg_ghc = ghc;
479
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
481 "Full-Duplex, " :
482 "Half-Duplex, ");
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
484 "MDI-X" :
485 "MDI");
486 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
487 netif_carrier_on(netdev);
488 } else {
489 if (testonly)
490 goto out;
491
492 netif_info(jme, link, jme->dev, "Link is down\n");
493 jme->phylink = 0;
494 netif_carrier_off(netdev);
495 }
496
497out:
498 return rc;
499}
500
501static int
502jme_setup_tx_resources(struct jme_adapter *jme)
503{
504 struct jme_ring *txring = &(jme->txring[0]);
505
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
508 &(txring->dmaalloc),
509 GFP_ATOMIC);
510
511 if (!txring->alloc)
512 goto err_set_null;
513
514 /*
515 * 16 Bytes align
516 */
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
518 RING_DESC_ALIGN);
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
523
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
528
529 /*
530 * Initialize Transmit Descriptors
531 */
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
535
536 return 0;
537
538err_free_txring:
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
541 txring->alloc,
542 txring->dmaalloc);
543
544err_set_null:
545 txring->desc = NULL;
546 txring->dmaalloc = 0;
547 txring->dma = 0;
548 txring->bufinf = NULL;
549
550 return -ENOMEM;
551}
552
553static void
554jme_free_tx_resources(struct jme_adapter *jme)
555{
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
559
560 if (txring->alloc) {
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
564 if (txbi->skb) {
565 dev_kfree_skb(txbi->skb);
566 txbi->skb = NULL;
567 }
568 txbi->mapping = 0;
569 txbi->len = 0;
570 txbi->nr_desc = 0;
571 txbi->start_xmit = 0;
572 }
573 kfree(txring->bufinf);
574 }
575
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
578 txring->alloc,
579 txring->dmaalloc);
580
581 txring->alloc = NULL;
582 txring->desc = NULL;
583 txring->dmaalloc = 0;
584 txring->dma = 0;
585 txring->bufinf = NULL;
586 }
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
590}
591
592static inline void
593jme_enable_tx_engine(struct jme_adapter *jme)
594{
595 /*
596 * Select Queue 0
597 */
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
599 wmb();
600
601 /*
602 * Setup TX Queue 0 DMA Bass Address
603 */
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
607
608 /*
609 * Setup TX Descptor Count
610 */
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
612
613 /*
614 * Enable TX Engine
615 */
616 wmb();
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
618 TXCS_SELECT_QUEUE0 |
619 TXCS_ENABLE);
620
621}
622
623static inline void
624jme_restart_tx_engine(struct jme_adapter *jme)
625{
626 /*
627 * Restart TX Engine
628 */
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
630 TXCS_SELECT_QUEUE0 |
631 TXCS_ENABLE);
632}
633
634static inline void
635jme_disable_tx_engine(struct jme_adapter *jme)
636{
637 int i;
638 u32 val;
639
640 /*
641 * Disable TX Engine
642 */
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
644 wmb();
645
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
648 mdelay(1);
649 val = jread32(jme, JME_TXCS);
650 rmb();
651 }
652
653 if (!i)
654 pr_err("Disable TX engine timeout\n");
655}
656
657static void
658jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
659{
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
663 rxdesc += i;
664 rxbi += i;
665
666 rxdesc->dw[0] = 0;
667 rxdesc->dw[1] = 0;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
674 wmb();
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
676}
677
678static int
679jme_make_new_rx_buf(struct jme_adapter *jme, int i)
680{
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
683 struct sk_buff *skb;
684
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
687 if (unlikely(!skb))
688 return -ENOMEM;
689#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
690 skb->dev = jme->dev;
691#endif
692
693 rxbi->skb = skb;
694 rxbi->len = skb_tailroom(skb);
695 rxbi->mapping = pci_map_page(jme->pdev,
696 virt_to_page(skb->data),
697 offset_in_page(skb->data),
698 rxbi->len,
699 PCI_DMA_FROMDEVICE);
700
701 return 0;
702}
703
704static void
705jme_free_rx_buf(struct jme_adapter *jme, int i)
706{
707 struct jme_ring *rxring = &(jme->rxring[0]);
708 struct jme_buffer_info *rxbi = rxring->bufinf;
709 rxbi += i;
710
711 if (rxbi->skb) {
712 pci_unmap_page(jme->pdev,
713 rxbi->mapping,
714 rxbi->len,
715 PCI_DMA_FROMDEVICE);
716 dev_kfree_skb(rxbi->skb);
717 rxbi->skb = NULL;
718 rxbi->mapping = 0;
719 rxbi->len = 0;
720 }
721}
722
723static void
724jme_free_rx_resources(struct jme_adapter *jme)
725{
726 int i;
727 struct jme_ring *rxring = &(jme->rxring[0]);
728
729 if (rxring->alloc) {
730 if (rxring->bufinf) {
731 for (i = 0 ; i < jme->rx_ring_size ; ++i)
732 jme_free_rx_buf(jme, i);
733 kfree(rxring->bufinf);
734 }
735
736 dma_free_coherent(&(jme->pdev->dev),
737 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
738 rxring->alloc,
739 rxring->dmaalloc);
740 rxring->alloc = NULL;
741 rxring->desc = NULL;
742 rxring->dmaalloc = 0;
743 rxring->dma = 0;
744 rxring->bufinf = NULL;
745 }
746 rxring->next_to_use = 0;
747 atomic_set(&rxring->next_to_clean, 0);
748}
749
750static int
751jme_setup_rx_resources(struct jme_adapter *jme)
752{
753 int i;
754 struct jme_ring *rxring = &(jme->rxring[0]);
755
756 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
757 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
758 &(rxring->dmaalloc),
759 GFP_ATOMIC);
760 if (!rxring->alloc)
761 goto err_set_null;
762
763 /*
764 * 16 Bytes align
765 */
766 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
767 RING_DESC_ALIGN);
768 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
769 rxring->next_to_use = 0;
770 atomic_set(&rxring->next_to_clean, 0);
771
772 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
773 jme->rx_ring_size, GFP_ATOMIC);
774 if (unlikely(!(rxring->bufinf)))
775 goto err_free_rxring;
776
777 /*
778 * Initiallize Receive Descriptors
779 */
780 memset(rxring->bufinf, 0,
781 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
782 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
783 if (unlikely(jme_make_new_rx_buf(jme, i))) {
784 jme_free_rx_resources(jme);
785 return -ENOMEM;
786 }
787
788 jme_set_clean_rxdesc(jme, i);
789 }
790
791 return 0;
792
793err_free_rxring:
794 dma_free_coherent(&(jme->pdev->dev),
795 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
796 rxring->alloc,
797 rxring->dmaalloc);
798err_set_null:
799 rxring->desc = NULL;
800 rxring->dmaalloc = 0;
801 rxring->dma = 0;
802 rxring->bufinf = NULL;
803
804 return -ENOMEM;
805}
806
807static inline void
808jme_enable_rx_engine(struct jme_adapter *jme)
809{
810 /*
811 * Select Queue 0
812 */
813 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
814 RXCS_QUEUESEL_Q0);
815 wmb();
816
817 /*
818 * Setup RX DMA Bass Address
819 */
820 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
821 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
822 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
823
824 /*
825 * Setup RX Descriptor Count
826 */
827 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
828
829 /*
830 * Setup Unicast Filter
831 */
832 jme_set_multi(jme->dev);
833
834 /*
835 * Enable RX Engine
836 */
837 wmb();
838 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
839 RXCS_QUEUESEL_Q0 |
840 RXCS_ENABLE |
841 RXCS_QST);
842}
843
844static inline void
845jme_restart_rx_engine(struct jme_adapter *jme)
846{
847 /*
848 * Start RX Engine
849 */
850 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
851 RXCS_QUEUESEL_Q0 |
852 RXCS_ENABLE |
853 RXCS_QST);
854}
855
856static inline void
857jme_disable_rx_engine(struct jme_adapter *jme)
858{
859 int i;
860 u32 val;
861
862 /*
863 * Disable RX Engine
864 */
865 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
866 wmb();
867
868 val = jread32(jme, JME_RXCS);
869 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
870 mdelay(1);
871 val = jread32(jme, JME_RXCS);
872 rmb();
873 }
874
875 if (!i)
876 pr_err("Disable RX engine timeout\n");
877
878}
879
880static int
881jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
882{
883 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
884 return false;
885
886 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
887 == RXWBFLAG_TCPON)) {
888 if (flags & RXWBFLAG_IPV4)
889 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
890 return false;
891 }
892
893 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
894 == RXWBFLAG_UDPON)) {
895 if (flags & RXWBFLAG_IPV4)
896 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
897 return false;
898 }
899
900 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
901 == RXWBFLAG_IPV4)) {
902 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
903 return false;
904 }
905
906 return true;
907}
908
909static void
910jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
911{
912 struct jme_ring *rxring = &(jme->rxring[0]);
913 struct rxdesc *rxdesc = rxring->desc;
914 struct jme_buffer_info *rxbi = rxring->bufinf;
915 struct sk_buff *skb;
916 int framesize;
917
918 rxdesc += idx;
919 rxbi += idx;
920
921 skb = rxbi->skb;
922 pci_dma_sync_single_for_cpu(jme->pdev,
923 rxbi->mapping,
924 rxbi->len,
925 PCI_DMA_FROMDEVICE);
926
927 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
928 pci_dma_sync_single_for_device(jme->pdev,
929 rxbi->mapping,
930 rxbi->len,
931 PCI_DMA_FROMDEVICE);
932
933 ++(NET_STAT(jme).rx_dropped);
934 } else {
935 framesize = le16_to_cpu(rxdesc->descwb.framesize)
936 - RX_PREPAD_SIZE;
937
938 skb_reserve(skb, RX_PREPAD_SIZE);
939 skb_put(skb, framesize);
940 skb->protocol = eth_type_trans(skb, jme->dev);
941
942 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
943 skb->ip_summed = CHECKSUM_UNNECESSARY;
944 else
945#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
946 skb->ip_summed = CHECKSUM_NONE;
947#else
948 skb_checksum_none_assert(skb);
949#endif
950
951 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
952 if (jme->vlgrp) {
953 jme->jme_vlan_rx(skb, jme->vlgrp,
954 le16_to_cpu(rxdesc->descwb.vlan));
955 NET_STAT(jme).rx_bytes += 4;
956 } else {
957 dev_kfree_skb(skb);
958 }
959 } else {
960 jme->jme_rx(skb);
961 }
962
963 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
964 cpu_to_le16(RXWBFLAG_DEST_MUL))
965 ++(NET_STAT(jme).multicast);
966
967 NET_STAT(jme).rx_bytes += framesize;
968 ++(NET_STAT(jme).rx_packets);
969 }
970
971 jme_set_clean_rxdesc(jme, idx);
972
973}
974
975static int
976jme_process_receive(struct jme_adapter *jme, int limit)
977{
978 struct jme_ring *rxring = &(jme->rxring[0]);
979 struct rxdesc *rxdesc = rxring->desc;
980 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
981
982 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
983 goto out_inc;
984
985 if (unlikely(atomic_read(&jme->link_changing) != 1))
986 goto out_inc;
987
988 if (unlikely(!netif_carrier_ok(jme->dev)))
989 goto out_inc;
990
991 i = atomic_read(&rxring->next_to_clean);
992 while (limit > 0) {
993 rxdesc = rxring->desc;
994 rxdesc += i;
995
996 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
997 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
998 goto out;
999 --limit;
1000
1001 rmb();
1002 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1003
1004 if (unlikely(desccnt > 1 ||
1005 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1006
1007 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1008 ++(NET_STAT(jme).rx_crc_errors);
1009 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1010 ++(NET_STAT(jme).rx_fifo_errors);
1011 else
1012 ++(NET_STAT(jme).rx_errors);
1013
1014 if (desccnt > 1)
1015 limit -= desccnt - 1;
1016
1017 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1018 jme_set_clean_rxdesc(jme, j);
1019 j = (j + 1) & (mask);
1020 }
1021
1022 } else {
1023 jme_alloc_and_feed_skb(jme, i);
1024 }
1025
1026 i = (i + desccnt) & (mask);
1027 }
1028
1029out:
1030 atomic_set(&rxring->next_to_clean, i);
1031
1032out_inc:
1033 atomic_inc(&jme->rx_cleaning);
1034
1035 return limit > 0 ? limit : 0;
1036
1037}
1038
1039static void
1040jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1041{
1042 if (likely(atmp == dpi->cur)) {
1043 dpi->cnt = 0;
1044 return;
1045 }
1046
1047 if (dpi->attempt == atmp) {
1048 ++(dpi->cnt);
1049 } else {
1050 dpi->attempt = atmp;
1051 dpi->cnt = 0;
1052 }
1053
1054}
1055
1056static void
1057jme_dynamic_pcc(struct jme_adapter *jme)
1058{
1059 register struct dynpcc_info *dpi = &(jme->dpi);
1060
1061 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1062 jme_attempt_pcc(dpi, PCC_P3);
1063 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1064 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1065 jme_attempt_pcc(dpi, PCC_P2);
1066 else
1067 jme_attempt_pcc(dpi, PCC_P1);
1068
1069 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1070 if (dpi->attempt < dpi->cur)
1071 tasklet_schedule(&jme->rxclean_task);
1072 jme_set_rx_pcc(jme, dpi->attempt);
1073 dpi->cur = dpi->attempt;
1074 dpi->cnt = 0;
1075 }
1076}
1077
1078static void
1079jme_start_pcc_timer(struct jme_adapter *jme)
1080{
1081 struct dynpcc_info *dpi = &(jme->dpi);
1082 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1083 dpi->last_pkts = NET_STAT(jme).rx_packets;
1084 dpi->intr_cnt = 0;
1085 jwrite32(jme, JME_TMCSR,
1086 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1087}
1088
1089static inline void
1090jme_stop_pcc_timer(struct jme_adapter *jme)
1091{
1092 jwrite32(jme, JME_TMCSR, 0);
1093}
1094
1095static void
1096jme_shutdown_nic(struct jme_adapter *jme)
1097{
1098 u32 phylink;
1099
1100 phylink = jme_linkstat_from_phy(jme);
1101
1102 if (!(phylink & PHY_LINK_UP)) {
1103 /*
1104 * Disable all interrupt before issue timer
1105 */
1106 jme_stop_irq(jme);
1107 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1108 }
1109}
1110
1111static void
1112jme_pcc_tasklet(unsigned long arg)
1113{
1114 struct jme_adapter *jme = (struct jme_adapter *)arg;
1115 struct net_device *netdev = jme->dev;
1116
1117 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1118 jme_shutdown_nic(jme);
1119 return;
1120 }
1121
1122 if (unlikely(!netif_carrier_ok(netdev) ||
1123 (atomic_read(&jme->link_changing) != 1)
1124 )) {
1125 jme_stop_pcc_timer(jme);
1126 return;
1127 }
1128
1129 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1130 jme_dynamic_pcc(jme);
1131
1132 jme_start_pcc_timer(jme);
1133}
1134
1135static inline void
1136jme_polling_mode(struct jme_adapter *jme)
1137{
1138 jme_set_rx_pcc(jme, PCC_OFF);
1139}
1140
1141static inline void
1142jme_interrupt_mode(struct jme_adapter *jme)
1143{
1144 jme_set_rx_pcc(jme, PCC_P1);
1145}
1146
1147static inline int
1148jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1149{
1150 u32 apmc;
1151 apmc = jread32(jme, JME_APMC);
1152 return apmc & JME_APMC_PSEUDO_HP_EN;
1153}
1154
1155static void
1156jme_start_shutdown_timer(struct jme_adapter *jme)
1157{
1158 u32 apmc;
1159
1160 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1161 apmc &= ~JME_APMC_EPIEN_CTRL;
1162 if (!no_extplug) {
1163 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1164 wmb();
1165 }
1166 jwrite32f(jme, JME_APMC, apmc);
1167
1168 jwrite32f(jme, JME_TIMER2, 0);
1169 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1170 jwrite32(jme, JME_TMCSR,
1171 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1172}
1173
1174static void
1175jme_stop_shutdown_timer(struct jme_adapter *jme)
1176{
1177 u32 apmc;
1178
1179 jwrite32f(jme, JME_TMCSR, 0);
1180 jwrite32f(jme, JME_TIMER2, 0);
1181 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1182
1183 apmc = jread32(jme, JME_APMC);
1184 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1185 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1186 wmb();
1187 jwrite32f(jme, JME_APMC, apmc);
1188}
1189
1190static void
1191jme_link_change_tasklet(unsigned long arg)
1192{
1193 struct jme_adapter *jme = (struct jme_adapter *)arg;
1194 struct net_device *netdev = jme->dev;
1195 int rc;
1196
1197 while (!atomic_dec_and_test(&jme->link_changing)) {
1198 atomic_inc(&jme->link_changing);
1199 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1200 while (atomic_read(&jme->link_changing) != 1)
1201 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1202 }
1203
1204 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1205 goto out;
1206
1207 jme->old_mtu = netdev->mtu;
1208 netif_stop_queue(netdev);
1209 if (jme_pseudo_hotplug_enabled(jme))
1210 jme_stop_shutdown_timer(jme);
1211
1212 jme_stop_pcc_timer(jme);
1213 tasklet_disable(&jme->txclean_task);
1214 tasklet_disable(&jme->rxclean_task);
1215 tasklet_disable(&jme->rxempty_task);
1216
1217 if (netif_carrier_ok(netdev)) {
1218 jme_reset_ghc_speed(jme);
1219 jme_disable_rx_engine(jme);
1220 jme_disable_tx_engine(jme);
1221 jme_reset_mac_processor(jme);
1222 jme_free_rx_resources(jme);
1223 jme_free_tx_resources(jme);
1224
1225 if (test_bit(JME_FLAG_POLL, &jme->flags))
1226 jme_polling_mode(jme);
1227
1228 netif_carrier_off(netdev);
1229 }
1230
1231 jme_check_link(netdev, 0);
1232 if (netif_carrier_ok(netdev)) {
1233 rc = jme_setup_rx_resources(jme);
1234 if (rc) {
1235 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1236 goto out_enable_tasklet;
1237 }
1238
1239 rc = jme_setup_tx_resources(jme);
1240 if (rc) {
1241 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1242 goto err_out_free_rx_resources;
1243 }
1244
1245 jme_enable_rx_engine(jme);
1246 jme_enable_tx_engine(jme);
1247
1248 netif_start_queue(netdev);
1249
1250 if (test_bit(JME_FLAG_POLL, &jme->flags))
1251 jme_interrupt_mode(jme);
1252
1253 jme_start_pcc_timer(jme);
1254 } else if (jme_pseudo_hotplug_enabled(jme)) {
1255 jme_start_shutdown_timer(jme);
1256 }
1257
1258 goto out_enable_tasklet;
1259
1260err_out_free_rx_resources:
1261 jme_free_rx_resources(jme);
1262out_enable_tasklet:
1263 tasklet_enable(&jme->txclean_task);
1264 tasklet_hi_enable(&jme->rxclean_task);
1265 tasklet_hi_enable(&jme->rxempty_task);
1266out:
1267 atomic_inc(&jme->link_changing);
1268}
1269
1270static void
1271jme_rx_clean_tasklet(unsigned long arg)
1272{
1273 struct jme_adapter *jme = (struct jme_adapter *)arg;
1274 struct dynpcc_info *dpi = &(jme->dpi);
1275
1276 jme_process_receive(jme, jme->rx_ring_size);
1277 ++(dpi->intr_cnt);
1278
1279}
1280
1281static int
1282jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1283{
1284 struct jme_adapter *jme = jme_napi_priv(holder);
1285 DECLARE_NETDEV
1286 int rest;
1287
1288 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1289
1290 while (atomic_read(&jme->rx_empty) > 0) {
1291 atomic_dec(&jme->rx_empty);
1292 ++(NET_STAT(jme).rx_dropped);
1293 jme_restart_rx_engine(jme);
1294 }
1295 atomic_inc(&jme->rx_empty);
1296
1297 if (rest) {
1298 JME_RX_COMPLETE(netdev, holder);
1299 jme_interrupt_mode(jme);
1300 }
1301
1302 JME_NAPI_WEIGHT_SET(budget, rest);
1303 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1304}
1305
1306static void
1307jme_rx_empty_tasklet(unsigned long arg)
1308{
1309 struct jme_adapter *jme = (struct jme_adapter *)arg;
1310
1311 if (unlikely(atomic_read(&jme->link_changing) != 1))
1312 return;
1313
1314 if (unlikely(!netif_carrier_ok(jme->dev)))
1315 return;
1316
1317 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1318
1319 jme_rx_clean_tasklet(arg);
1320
1321 while (atomic_read(&jme->rx_empty) > 0) {
1322 atomic_dec(&jme->rx_empty);
1323 ++(NET_STAT(jme).rx_dropped);
1324 jme_restart_rx_engine(jme);
1325 }
1326 atomic_inc(&jme->rx_empty);
1327}
1328
1329static void
1330jme_wake_queue_if_stopped(struct jme_adapter *jme)
1331{
1332 struct jme_ring *txring = &(jme->txring[0]);
1333
1334 smp_wmb();
1335 if (unlikely(netif_queue_stopped(jme->dev) &&
1336 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1337 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1338 netif_wake_queue(jme->dev);
1339 }
1340
1341}
1342
1343static void
1344jme_tx_clean_tasklet(unsigned long arg)
1345{
1346 struct jme_adapter *jme = (struct jme_adapter *)arg;
1347 struct jme_ring *txring = &(jme->txring[0]);
1348 struct txdesc *txdesc = txring->desc;
1349 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1350 int i, j, cnt = 0, max, err, mask;
1351
1352 tx_dbg(jme, "Into txclean\n");
1353
1354 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1355 goto out;
1356
1357 if (unlikely(atomic_read(&jme->link_changing) != 1))
1358 goto out;
1359
1360 if (unlikely(!netif_carrier_ok(jme->dev)))
1361 goto out;
1362
1363 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1364 mask = jme->tx_ring_mask;
1365
1366 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1367
1368 ctxbi = txbi + i;
1369
1370 if (likely(ctxbi->skb &&
1371 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1372
1373 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1374 i, ctxbi->nr_desc, jiffies);
1375
1376 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1377
1378 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1379 ttxbi = txbi + ((i + j) & (mask));
1380 txdesc[(i + j) & (mask)].dw[0] = 0;
1381
1382 pci_unmap_page(jme->pdev,
1383 ttxbi->mapping,
1384 ttxbi->len,
1385 PCI_DMA_TODEVICE);
1386
1387 ttxbi->mapping = 0;
1388 ttxbi->len = 0;
1389 }
1390
1391 dev_kfree_skb(ctxbi->skb);
1392
1393 cnt += ctxbi->nr_desc;
1394
1395 if (unlikely(err)) {
1396 ++(NET_STAT(jme).tx_carrier_errors);
1397 } else {
1398 ++(NET_STAT(jme).tx_packets);
1399 NET_STAT(jme).tx_bytes += ctxbi->len;
1400 }
1401
1402 ctxbi->skb = NULL;
1403 ctxbi->len = 0;
1404 ctxbi->start_xmit = 0;
1405
1406 } else {
1407 break;
1408 }
1409
1410 i = (i + ctxbi->nr_desc) & mask;
1411
1412 ctxbi->nr_desc = 0;
1413 }
1414
1415 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1416 atomic_set(&txring->next_to_clean, i);
1417 atomic_add(cnt, &txring->nr_free);
1418
1419 jme_wake_queue_if_stopped(jme);
1420
1421out:
1422 atomic_inc(&jme->tx_cleaning);
1423}
1424
1425static void
1426jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1427{
1428 /*
1429 * Disable interrupt
1430 */
1431 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1432
1433 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1434 /*
1435 * Link change event is critical
1436 * all other events are ignored
1437 */
1438 jwrite32(jme, JME_IEVE, intrstat);
1439 tasklet_schedule(&jme->linkch_task);
1440 goto out_reenable;
1441 }
1442
1443 if (intrstat & INTR_TMINTR) {
1444 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1445 tasklet_schedule(&jme->pcc_task);
1446 }
1447
1448 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1449 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1450 tasklet_schedule(&jme->txclean_task);
1451 }
1452
1453 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1454 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1455 INTR_PCCRX0 |
1456 INTR_RX0EMP)) |
1457 INTR_RX0);
1458 }
1459
1460 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1461 if (intrstat & INTR_RX0EMP)
1462 atomic_inc(&jme->rx_empty);
1463
1464 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1465 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1466 jme_polling_mode(jme);
1467 JME_RX_SCHEDULE(jme);
1468 }
1469 }
1470 } else {
1471 if (intrstat & INTR_RX0EMP) {
1472 atomic_inc(&jme->rx_empty);
1473 tasklet_hi_schedule(&jme->rxempty_task);
1474 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1475 tasklet_hi_schedule(&jme->rxclean_task);
1476 }
1477 }
1478
1479out_reenable:
1480 /*
1481 * Re-enable interrupt
1482 */
1483 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1484}
1485
1486#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1487static irqreturn_t
1488jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1489#else
1490static irqreturn_t
1491jme_intr(int irq, void *dev_id)
1492#endif
1493{
1494 struct net_device *netdev = dev_id;
1495 struct jme_adapter *jme = netdev_priv(netdev);
1496 u32 intrstat;
1497
1498 intrstat = jread32(jme, JME_IEVE);
1499
1500 /*
1501 * Check if it's really an interrupt for us
1502 */
1503 if (unlikely((intrstat & INTR_ENABLE) == 0))
1504 return IRQ_NONE;
1505
1506 /*
1507 * Check if the device still exist
1508 */
1509 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1510 return IRQ_NONE;
1511
1512 jme_intr_msi(jme, intrstat);
1513
1514 return IRQ_HANDLED;
1515}
1516
1517#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1518static irqreturn_t
1519jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1520#else
1521static irqreturn_t
1522jme_msi(int irq, void *dev_id)
1523#endif
1524{
1525 struct net_device *netdev = dev_id;
1526 struct jme_adapter *jme = netdev_priv(netdev);
1527 u32 intrstat;
1528
1529 intrstat = jread32(jme, JME_IEVE);
1530
1531 jme_intr_msi(jme, intrstat);
1532
1533 return IRQ_HANDLED;
1534}
1535
1536static void
1537jme_reset_link(struct jme_adapter *jme)
1538{
1539 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1540}
1541
1542static void
1543jme_restart_an(struct jme_adapter *jme)
1544{
1545 u32 bmcr;
1546
1547 spin_lock_bh(&jme->phy_lock);
1548 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1549 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1550 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1551 spin_unlock_bh(&jme->phy_lock);
1552}
1553
1554static int
1555jme_request_irq(struct jme_adapter *jme)
1556{
1557 int rc;
1558 struct net_device *netdev = jme->dev;
1559#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1560 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1561 int irq_flags = SA_SHIRQ;
1562#else
1563 irq_handler_t handler = jme_intr;
1564 int irq_flags = IRQF_SHARED;
1565#endif
1566
1567 if (!pci_enable_msi(jme->pdev)) {
1568 set_bit(JME_FLAG_MSI, &jme->flags);
1569 handler = jme_msi;
1570 irq_flags = 0;
1571 }
1572
1573 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1574 netdev);
1575 if (rc) {
1576 netdev_err(netdev,
1577 "Unable to request %s interrupt (return: %d)\n",
1578 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1579 rc);
1580
1581 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1582 pci_disable_msi(jme->pdev);
1583 clear_bit(JME_FLAG_MSI, &jme->flags);
1584 }
1585 } else {
1586 netdev->irq = jme->pdev->irq;
1587 }
1588
1589 return rc;
1590}
1591
1592static void
1593jme_free_irq(struct jme_adapter *jme)
1594{
1595 free_irq(jme->pdev->irq, jme->dev);
1596 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1597 pci_disable_msi(jme->pdev);
1598 clear_bit(JME_FLAG_MSI, &jme->flags);
1599 jme->dev->irq = jme->pdev->irq;
1600 }
1601}
1602
1603static inline void
1604jme_new_phy_on(struct jme_adapter *jme)
1605{
1606 u32 reg;
1607
1608 reg = jread32(jme, JME_PHY_PWR);
1609 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1610 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1611 jwrite32(jme, JME_PHY_PWR, reg);
1612
1613 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1614 reg &= ~PE1_GPREG0_PBG;
1615 reg |= PE1_GPREG0_ENBG;
1616 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1617}
1618
1619static inline void
1620jme_new_phy_off(struct jme_adapter *jme)
1621{
1622 u32 reg;
1623
1624 reg = jread32(jme, JME_PHY_PWR);
1625 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1626 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1627 jwrite32(jme, JME_PHY_PWR, reg);
1628
1629 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1630 reg &= ~PE1_GPREG0_PBG;
1631 reg |= PE1_GPREG0_PDD3COLD;
1632 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1633}
1634
1635static inline void
1636jme_phy_on(struct jme_adapter *jme)
1637{
1638 u32 bmcr;
1639
1640 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1641 bmcr &= ~BMCR_PDOWN;
1642 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1643
1644 if (new_phy_power_ctrl(jme->chip_main_rev))
1645 jme_new_phy_on(jme);
1646}
1647
1648static inline void
1649jme_phy_off(struct jme_adapter *jme)
1650{
1651 u32 bmcr;
1652
1653 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1654 bmcr |= BMCR_PDOWN;
1655 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1656
1657 if (new_phy_power_ctrl(jme->chip_main_rev))
1658 jme_new_phy_off(jme);
1659}
1660
1661static int
1662jme_open(struct net_device *netdev)
1663{
1664 struct jme_adapter *jme = netdev_priv(netdev);
1665 int rc;
1666
1667 jme_clear_pm(jme);
1668 JME_NAPI_ENABLE(jme);
1669
1670 tasklet_enable(&jme->linkch_task);
1671 tasklet_enable(&jme->txclean_task);
1672 tasklet_hi_enable(&jme->rxclean_task);
1673 tasklet_hi_enable(&jme->rxempty_task);
1674
1675 rc = jme_request_irq(jme);
1676 if (rc)
1677 goto err_out;
1678
1679 jme_start_irq(jme);
1680
1681 jme_phy_on(jme);
1682 if (test_bit(JME_FLAG_SSET, &jme->flags))
1683 jme_set_settings(netdev, &jme->old_ecmd);
1684 else
1685 jme_reset_phy_processor(jme);
1686
1687 jme_reset_link(jme);
1688
1689 return 0;
1690
1691err_out:
1692 netif_stop_queue(netdev);
1693 netif_carrier_off(netdev);
1694 return rc;
1695}
1696
1697static void
1698jme_set_100m_half(struct jme_adapter *jme)
1699{
1700 u32 bmcr, tmp;
1701
1702 jme_phy_on(jme);
1703 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1704 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1705 BMCR_SPEED1000 | BMCR_FULLDPLX);
1706 tmp |= BMCR_SPEED100;
1707
1708 if (bmcr != tmp)
1709 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1710
1711 if (jme->fpgaver)
1712 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1713 else
1714 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1715}
1716
1717#define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1718static void
1719jme_wait_link(struct jme_adapter *jme)
1720{
1721 u32 phylink, to = JME_WAIT_LINK_TIME;
1722
1723 mdelay(1000);
1724 phylink = jme_linkstat_from_phy(jme);
1725 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1726 mdelay(10);
1727 phylink = jme_linkstat_from_phy(jme);
1728 }
1729}
1730
1731static void
1732jme_powersave_phy(struct jme_adapter *jme)
1733{
1734 if (jme->reg_pmcs) {
1735 jme_set_100m_half(jme);
1736
1737 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1738 jme_wait_link(jme);
1739
1740 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1741 } else {
1742 jme_phy_off(jme);
1743 }
1744}
1745
1746static int
1747jme_close(struct net_device *netdev)
1748{
1749 struct jme_adapter *jme = netdev_priv(netdev);
1750
1751 netif_stop_queue(netdev);
1752 netif_carrier_off(netdev);
1753
1754 jme_stop_irq(jme);
1755 jme_free_irq(jme);
1756
1757 JME_NAPI_DISABLE(jme);
1758
1759 tasklet_disable(&jme->linkch_task);
1760 tasklet_disable(&jme->txclean_task);
1761 tasklet_disable(&jme->rxclean_task);
1762 tasklet_disable(&jme->rxempty_task);
1763
1764 jme_reset_ghc_speed(jme);
1765 jme_disable_rx_engine(jme);
1766 jme_disable_tx_engine(jme);
1767 jme_reset_mac_processor(jme);
1768 jme_free_rx_resources(jme);
1769 jme_free_tx_resources(jme);
1770 jme->phylink = 0;
1771 jme_phy_off(jme);
1772
1773 return 0;
1774}
1775
1776static int
1777jme_alloc_txdesc(struct jme_adapter *jme,
1778 struct sk_buff *skb)
1779{
1780 struct jme_ring *txring = &(jme->txring[0]);
1781 int idx, nr_alloc, mask = jme->tx_ring_mask;
1782
1783 idx = txring->next_to_use;
1784 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1785
1786 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1787 return -1;
1788
1789 atomic_sub(nr_alloc, &txring->nr_free);
1790
1791 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1792
1793 return idx;
1794}
1795
1796static void
1797jme_fill_tx_map(struct pci_dev *pdev,
1798 struct txdesc *txdesc,
1799 struct jme_buffer_info *txbi,
1800 struct page *page,
1801 u32 page_offset,
1802 u32 len,
1803 u8 hidma)
1804{
1805 dma_addr_t dmaaddr;
1806
1807 dmaaddr = pci_map_page(pdev,
1808 page,
1809 page_offset,
1810 len,
1811 PCI_DMA_TODEVICE);
1812
1813 pci_dma_sync_single_for_device(pdev,
1814 dmaaddr,
1815 len,
1816 PCI_DMA_TODEVICE);
1817
1818 txdesc->dw[0] = 0;
1819 txdesc->dw[1] = 0;
1820 txdesc->desc2.flags = TXFLAG_OWN;
1821 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1822 txdesc->desc2.datalen = cpu_to_le16(len);
1823 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1824 txdesc->desc2.bufaddrl = cpu_to_le32(
1825 (__u64)dmaaddr & 0xFFFFFFFFUL);
1826
1827 txbi->mapping = dmaaddr;
1828 txbi->len = len;
1829}
1830
1831static void
1832jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1833{
1834 struct jme_ring *txring = &(jme->txring[0]);
1835 struct txdesc *txdesc = txring->desc, *ctxdesc;
1836 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1837 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1838 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1839 int mask = jme->tx_ring_mask;
1840 struct skb_frag_struct *frag;
1841 u32 len;
1842
1843 for (i = 0 ; i < nr_frags ; ++i) {
1844 frag = &skb_shinfo(skb)->frags[i];
1845 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1846 ctxbi = txbi + ((idx + i + 2) & (mask));
1847
1848 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1849 frag->page_offset, frag->size, hidma);
1850 }
1851
1852 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1853 ctxdesc = txdesc + ((idx + 1) & (mask));
1854 ctxbi = txbi + ((idx + 1) & (mask));
1855 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1856 offset_in_page(skb->data), len, hidma);
1857
1858}
1859
1860static int
1861jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1862{
1863 if (unlikely(
1864#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1865 skb_shinfo(skb)->tso_size
1866#else
1867 skb_shinfo(skb)->gso_size
1868#endif
1869 && skb_header_cloned(skb) &&
1870 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1871 dev_kfree_skb(skb);
1872 return -1;
1873 }
1874
1875 return 0;
1876}
1877
1878static int
1879jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1880{
1881#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1882 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
1883#else
1884 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1885#endif
1886 if (*mss) {
1887 *flags |= TXFLAG_LSEN;
1888
1889 if (skb->protocol == htons(ETH_P_IP)) {
1890 struct iphdr *iph = ip_hdr(skb);
1891
1892 iph->check = 0;
1893 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1894 iph->daddr, 0,
1895 IPPROTO_TCP,
1896 0);
1897 } else {
1898 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1899
1900 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1901 &ip6h->daddr, 0,
1902 IPPROTO_TCP,
1903 0);
1904 }
1905
1906 return 0;
1907 }
1908
1909 return 1;
1910}
1911
1912static void
1913jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1914{
1915#ifdef CHECKSUM_PARTIAL
1916 if (skb->ip_summed == CHECKSUM_PARTIAL)
1917#else
1918 if (skb->ip_summed == CHECKSUM_HW)
1919#endif
1920 {
1921 u8 ip_proto;
1922
1923#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
1924 if (skb->protocol == htons(ETH_P_IP))
1925 ip_proto = ip_hdr(skb)->protocol;
1926 else if (skb->protocol == htons(ETH_P_IPV6))
1927 ip_proto = ipv6_hdr(skb)->nexthdr;
1928 else
1929 ip_proto = 0;
1930#else
1931 switch (skb->protocol) {
1932 case htons(ETH_P_IP):
1933 ip_proto = ip_hdr(skb)->protocol;
1934 break;
1935 case htons(ETH_P_IPV6):
1936 ip_proto = ipv6_hdr(skb)->nexthdr;
1937 break;
1938 default:
1939 ip_proto = 0;
1940 break;
1941 }
1942#endif
1943
1944 switch (ip_proto) {
1945 case IPPROTO_TCP:
1946 *flags |= TXFLAG_TCPCS;
1947 break;
1948 case IPPROTO_UDP:
1949 *flags |= TXFLAG_UDPCS;
1950 break;
1951 default:
1952 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
1953 break;
1954 }
1955 }
1956}
1957
1958static inline void
1959jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1960{
1961 if (vlan_tx_tag_present(skb)) {
1962 *flags |= TXFLAG_TAGON;
1963 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1964 }
1965}
1966
1967static int
1968jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1969{
1970 struct jme_ring *txring = &(jme->txring[0]);
1971 struct txdesc *txdesc;
1972 struct jme_buffer_info *txbi;
1973 u8 flags;
1974
1975 txdesc = (struct txdesc *)txring->desc + idx;
1976 txbi = txring->bufinf + idx;
1977
1978 txdesc->dw[0] = 0;
1979 txdesc->dw[1] = 0;
1980 txdesc->dw[2] = 0;
1981 txdesc->dw[3] = 0;
1982 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1983 /*
1984 * Set OWN bit at final.
1985 * When kernel transmit faster than NIC.
1986 * And NIC trying to send this descriptor before we tell
1987 * it to start sending this TX queue.
1988 * Other fields are already filled correctly.
1989 */
1990 wmb();
1991 flags = TXFLAG_OWN | TXFLAG_INT;
1992 /*
1993 * Set checksum flags while not tso
1994 */
1995 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1996 jme_tx_csum(jme, skb, &flags);
1997 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1998 jme_map_tx_skb(jme, skb, idx);
1999 txdesc->desc1.flags = flags;
2000 /*
2001 * Set tx buffer info after telling NIC to send
2002 * For better tx_clean timing
2003 */
2004 wmb();
2005 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2006 txbi->skb = skb;
2007 txbi->len = skb->len;
2008 txbi->start_xmit = jiffies;
2009 if (!txbi->start_xmit)
2010 txbi->start_xmit = (0UL-1);
2011
2012 return 0;
2013}
2014
2015static void
2016jme_stop_queue_if_full(struct jme_adapter *jme)
2017{
2018 struct jme_ring *txring = &(jme->txring[0]);
2019 struct jme_buffer_info *txbi = txring->bufinf;
2020 int idx = atomic_read(&txring->next_to_clean);
2021
2022 txbi += idx;
2023
2024 smp_wmb();
2025 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2026 netif_stop_queue(jme->dev);
2027 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2028 smp_wmb();
2029 if (atomic_read(&txring->nr_free)
2030 >= (jme->tx_wake_threshold)) {
2031 netif_wake_queue(jme->dev);
2032 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2033 }
2034 }
2035
2036 if (unlikely(txbi->start_xmit &&
2037 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2038 txbi->skb)) {
2039 netif_stop_queue(jme->dev);
2040 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2041 }
2042}
2043
2044/*
2045 * This function is already protected by netif_tx_lock()
2046 */
2047
2048#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2049static int
2050#else
2051static netdev_tx_t
2052#endif
2053jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2054{
2055 struct jme_adapter *jme = netdev_priv(netdev);
2056 int idx;
2057
2058 if (unlikely(jme_expand_header(jme, skb))) {
2059 ++(NET_STAT(jme).tx_dropped);
2060 return NETDEV_TX_OK;
2061 }
2062
2063 idx = jme_alloc_txdesc(jme, skb);
2064
2065 if (unlikely(idx < 0)) {
2066 netif_stop_queue(netdev);
2067 netif_err(jme, tx_err, jme->dev,
2068 "BUG! Tx ring full when queue awake!\n");
2069
2070 return NETDEV_TX_BUSY;
2071 }
2072
2073 jme_fill_tx_desc(jme, skb, idx);
2074
2075 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2076 TXCS_SELECT_QUEUE0 |
2077 TXCS_QUEUE0S |
2078 TXCS_ENABLE);
2079#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2080 netdev->trans_start = jiffies;
2081#endif
2082
2083 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2084 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2085 jme_stop_queue_if_full(jme);
2086
2087 return NETDEV_TX_OK;
2088}
2089
2090static int
2091jme_set_macaddr(struct net_device *netdev, void *p)
2092{
2093 struct jme_adapter *jme = netdev_priv(netdev);
2094 struct sockaddr *addr = p;
2095 u32 val;
2096
2097 if (netif_running(netdev))
2098 return -EBUSY;
2099
2100 spin_lock_bh(&jme->macaddr_lock);
2101 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2102
2103 val = (addr->sa_data[3] & 0xff) << 24 |
2104 (addr->sa_data[2] & 0xff) << 16 |
2105 (addr->sa_data[1] & 0xff) << 8 |
2106 (addr->sa_data[0] & 0xff);
2107 jwrite32(jme, JME_RXUMA_LO, val);
2108 val = (addr->sa_data[5] & 0xff) << 8 |
2109 (addr->sa_data[4] & 0xff);
2110 jwrite32(jme, JME_RXUMA_HI, val);
2111 spin_unlock_bh(&jme->macaddr_lock);
2112
2113 return 0;
2114}
2115
2116static void
2117jme_set_multi(struct net_device *netdev)
2118{
2119 struct jme_adapter *jme = netdev_priv(netdev);
2120 u32 mc_hash[2] = {};
2121#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2122 int i;
2123#endif
2124
2125 spin_lock_bh(&jme->rxmcs_lock);
2126
2127 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2128
2129 if (netdev->flags & IFF_PROMISC) {
2130 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2131 } else if (netdev->flags & IFF_ALLMULTI) {
2132 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2133 } else if (netdev->flags & IFF_MULTICAST) {
2134#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2135 struct dev_mc_list *mclist;
2136#else
2137 struct netdev_hw_addr *ha;
2138#endif
2139 int bit_nr;
2140
2141 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2142#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2143 for (i = 0, mclist = netdev->mc_list;
2144 mclist && i < netdev->mc_count;
2145 ++i, mclist = mclist->next) {
2146#elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2147 netdev_for_each_mc_addr(mclist, netdev) {
2148#else
2149 netdev_for_each_mc_addr(ha, netdev) {
2150#endif
2151#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2152 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2153#else
2154 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2155#endif
2156 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2157 }
2158
2159 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2160 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2161 }
2162
2163 wmb();
2164 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2165
2166 spin_unlock_bh(&jme->rxmcs_lock);
2167}
2168
2169static int
2170jme_change_mtu(struct net_device *netdev, int new_mtu)
2171{
2172 struct jme_adapter *jme = netdev_priv(netdev);
2173
2174 if (new_mtu == jme->old_mtu)
2175 return 0;
2176
2177 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2178 ((new_mtu) < IPV6_MIN_MTU))
2179 return -EINVAL;
2180
2181 if (new_mtu > 4000) {
2182 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2183 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2184 jme_restart_rx_engine(jme);
2185 } else {
2186 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2187 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2188 jme_restart_rx_engine(jme);
2189 }
2190
2191 if (new_mtu > 1900) {
2192 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2193 NETIF_F_TSO | NETIF_F_TSO6);
2194 } else {
2195 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2196 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2197 if (test_bit(JME_FLAG_TSO, &jme->flags))
2198 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2199 }
2200
2201 netdev->mtu = new_mtu;
2202 jme_reset_link(jme);
2203
2204 return 0;
2205}
2206
2207static void
2208jme_tx_timeout(struct net_device *netdev)
2209{
2210 struct jme_adapter *jme = netdev_priv(netdev);
2211
2212 jme->phylink = 0;
2213 jme_reset_phy_processor(jme);
2214 if (test_bit(JME_FLAG_SSET, &jme->flags))
2215 jme_set_settings(netdev, &jme->old_ecmd);
2216
2217 /*
2218 * Force to Reset the link again
2219 */
2220 jme_reset_link(jme);
2221}
2222
2223static inline void jme_pause_rx(struct jme_adapter *jme)
2224{
2225 atomic_dec(&jme->link_changing);
2226
2227 jme_set_rx_pcc(jme, PCC_OFF);
2228 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2229 JME_NAPI_DISABLE(jme);
2230 } else {
2231 tasklet_disable(&jme->rxclean_task);
2232 tasklet_disable(&jme->rxempty_task);
2233 }
2234}
2235
2236static inline void jme_resume_rx(struct jme_adapter *jme)
2237{
2238 struct dynpcc_info *dpi = &(jme->dpi);
2239
2240 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2241 JME_NAPI_ENABLE(jme);
2242 } else {
2243 tasklet_hi_enable(&jme->rxclean_task);
2244 tasklet_hi_enable(&jme->rxempty_task);
2245 }
2246 dpi->cur = PCC_P1;
2247 dpi->attempt = PCC_P1;
2248 dpi->cnt = 0;
2249 jme_set_rx_pcc(jme, PCC_P1);
2250
2251 atomic_inc(&jme->link_changing);
2252}
2253
2254static void
2255jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2256{
2257 struct jme_adapter *jme = netdev_priv(netdev);
2258
2259 jme_pause_rx(jme);
2260 jme->vlgrp = grp;
2261 jme_resume_rx(jme);
2262}
2263
2264#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2265static void
2266jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2267{
2268 struct jme_adapter *jme = netdev_priv(netdev);
2269
2270 if(jme->vlgrp) {
2271 jme_pause_rx(jme);
2272#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2273 jme->vlgrp->vlan_devices[vid] = NULL;
2274#else
2275 vlan_group_set_device(jme->vlgrp, vid, NULL);
2276#endif
2277 jme_resume_rx(jme);
2278 }
2279}
2280#endif
2281
2282static void
2283jme_get_drvinfo(struct net_device *netdev,
2284 struct ethtool_drvinfo *info)
2285{
2286 struct jme_adapter *jme = netdev_priv(netdev);
2287
2288 strcpy(info->driver, DRV_NAME);
2289 strcpy(info->version, DRV_VERSION);
2290 strcpy(info->bus_info, pci_name(jme->pdev));
2291}
2292
2293static int
2294jme_get_regs_len(struct net_device *netdev)
2295{
2296 return JME_REG_LEN;
2297}
2298
2299static void
2300mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2301{
2302 int i;
2303
2304 for (i = 0 ; i < len ; i += 4)
2305 p[i >> 2] = jread32(jme, reg + i);
2306}
2307
2308static void
2309mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2310{
2311 int i;
2312 u16 *p16 = (u16 *)p;
2313
2314 for (i = 0 ; i < reg_nr ; ++i)
2315 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2316}
2317
2318static void
2319jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2320{
2321 struct jme_adapter *jme = netdev_priv(netdev);
2322 u32 *p32 = (u32 *)p;
2323
2324 memset(p, 0xFF, JME_REG_LEN);
2325
2326 regs->version = 1;
2327 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2328
2329 p32 += 0x100 >> 2;
2330 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2331
2332 p32 += 0x100 >> 2;
2333 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2334
2335 p32 += 0x100 >> 2;
2336 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2337
2338 p32 += 0x100 >> 2;
2339 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2340}
2341
2342static int
2343jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2344{
2345 struct jme_adapter *jme = netdev_priv(netdev);
2346
2347 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2348 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2349
2350 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2351 ecmd->use_adaptive_rx_coalesce = false;
2352 ecmd->rx_coalesce_usecs = 0;
2353 ecmd->rx_max_coalesced_frames = 0;
2354 return 0;
2355 }
2356
2357 ecmd->use_adaptive_rx_coalesce = true;
2358
2359 switch (jme->dpi.cur) {
2360 case PCC_P1:
2361 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2362 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2363 break;
2364 case PCC_P2:
2365 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2366 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2367 break;
2368 case PCC_P3:
2369 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2370 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2371 break;
2372 default:
2373 break;
2374 }
2375
2376 return 0;
2377}
2378
2379static int
2380jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2381{
2382 struct jme_adapter *jme = netdev_priv(netdev);
2383 struct dynpcc_info *dpi = &(jme->dpi);
2384
2385 if (netif_running(netdev))
2386 return -EBUSY;
2387
2388 if (ecmd->use_adaptive_rx_coalesce &&
2389 test_bit(JME_FLAG_POLL, &jme->flags)) {
2390 clear_bit(JME_FLAG_POLL, &jme->flags);
2391 jme->jme_rx = netif_rx;
2392 jme->jme_vlan_rx = vlan_hwaccel_rx;
2393 dpi->cur = PCC_P1;
2394 dpi->attempt = PCC_P1;
2395 dpi->cnt = 0;
2396 jme_set_rx_pcc(jme, PCC_P1);
2397 jme_interrupt_mode(jme);
2398 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2399 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2400 set_bit(JME_FLAG_POLL, &jme->flags);
2401 jme->jme_rx = netif_receive_skb;
2402 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2403 jme_interrupt_mode(jme);
2404 }
2405
2406 return 0;
2407}
2408
2409static void
2410jme_get_pauseparam(struct net_device *netdev,
2411 struct ethtool_pauseparam *ecmd)
2412{
2413 struct jme_adapter *jme = netdev_priv(netdev);
2414 u32 val;
2415
2416 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2417 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2418
2419 spin_lock_bh(&jme->phy_lock);
2420 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2421 spin_unlock_bh(&jme->phy_lock);
2422
2423 ecmd->autoneg =
2424 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2425}
2426
2427static int
2428jme_set_pauseparam(struct net_device *netdev,
2429 struct ethtool_pauseparam *ecmd)
2430{
2431 struct jme_adapter *jme = netdev_priv(netdev);
2432 u32 val;
2433
2434 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2435 (ecmd->tx_pause != 0)) {
2436
2437 if (ecmd->tx_pause)
2438 jme->reg_txpfc |= TXPFC_PF_EN;
2439 else
2440 jme->reg_txpfc &= ~TXPFC_PF_EN;
2441
2442 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2443 }
2444
2445 spin_lock_bh(&jme->rxmcs_lock);
2446 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2447 (ecmd->rx_pause != 0)) {
2448
2449 if (ecmd->rx_pause)
2450 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2451 else
2452 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2453
2454 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2455 }
2456 spin_unlock_bh(&jme->rxmcs_lock);
2457
2458 spin_lock_bh(&jme->phy_lock);
2459 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2460 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2461 (ecmd->autoneg != 0)) {
2462
2463 if (ecmd->autoneg)
2464 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2465 else
2466 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2467
2468 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2469 MII_ADVERTISE, val);
2470 }
2471 spin_unlock_bh(&jme->phy_lock);
2472
2473 return 0;
2474}
2475
2476static void
2477jme_get_wol(struct net_device *netdev,
2478 struct ethtool_wolinfo *wol)
2479{
2480 struct jme_adapter *jme = netdev_priv(netdev);
2481
2482 wol->supported = WAKE_MAGIC | WAKE_PHY;
2483
2484 wol->wolopts = 0;
2485
2486 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2487 wol->wolopts |= WAKE_PHY;
2488
2489 if (jme->reg_pmcs & PMCS_MFEN)
2490 wol->wolopts |= WAKE_MAGIC;
2491
2492}
2493
2494static int
2495jme_set_wol(struct net_device *netdev,
2496 struct ethtool_wolinfo *wol)
2497{
2498 struct jme_adapter *jme = netdev_priv(netdev);
2499
2500 if (wol->wolopts & (WAKE_MAGICSECURE |
2501 WAKE_UCAST |
2502 WAKE_MCAST |
2503 WAKE_BCAST |
2504 WAKE_ARP))
2505 return -EOPNOTSUPP;
2506
2507 jme->reg_pmcs = 0;
2508
2509 if (wol->wolopts & WAKE_PHY)
2510 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2511
2512 if (wol->wolopts & WAKE_MAGIC)
2513 jme->reg_pmcs |= PMCS_MFEN;
2514
2515 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2516
2517 return 0;
2518}
2519
2520static int
2521jme_get_settings(struct net_device *netdev,
2522 struct ethtool_cmd *ecmd)
2523{
2524 struct jme_adapter *jme = netdev_priv(netdev);
2525 int rc;
2526
2527 spin_lock_bh(&jme->phy_lock);
2528 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2529 spin_unlock_bh(&jme->phy_lock);
2530 return rc;
2531}
2532
2533static int
2534jme_set_settings(struct net_device *netdev,
2535 struct ethtool_cmd *ecmd)
2536{
2537 struct jme_adapter *jme = netdev_priv(netdev);
2538 int rc, fdc = 0;
2539
2540 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2541 return -EINVAL;
2542
2543 /*
2544 * Check If user changed duplex only while force_media.
2545 * Hardware would not generate link change interrupt.
2546 */
2547 if (jme->mii_if.force_media &&
2548 ecmd->autoneg != AUTONEG_ENABLE &&
2549 (jme->mii_if.full_duplex != ecmd->duplex))
2550 fdc = 1;
2551
2552 spin_lock_bh(&jme->phy_lock);
2553 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2554 spin_unlock_bh(&jme->phy_lock);
2555
2556 if (!rc) {
2557 if (fdc)
2558 jme_reset_link(jme);
2559 jme->old_ecmd = *ecmd;
2560 set_bit(JME_FLAG_SSET, &jme->flags);
2561 }
2562
2563 return rc;
2564}
2565
2566static int
2567jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2568{
2569 int rc;
2570 struct jme_adapter *jme = netdev_priv(netdev);
2571 struct mii_ioctl_data *mii_data = if_mii(rq);
2572 unsigned int duplex_chg;
2573
2574 if (cmd == SIOCSMIIREG) {
2575 u16 val = mii_data->val_in;
2576 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2577 (val & BMCR_SPEED1000))
2578 return -EINVAL;
2579 }
2580
2581 spin_lock_bh(&jme->phy_lock);
2582 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2583 spin_unlock_bh(&jme->phy_lock);
2584
2585 if (!rc && (cmd == SIOCSMIIREG)) {
2586 if (duplex_chg)
2587 jme_reset_link(jme);
2588 jme_get_settings(netdev, &jme->old_ecmd);
2589 set_bit(JME_FLAG_SSET, &jme->flags);
2590 }
2591
2592 return rc;
2593}
2594
2595static u32
2596jme_get_link(struct net_device *netdev)
2597{
2598 struct jme_adapter *jme = netdev_priv(netdev);
2599 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2600}
2601
2602static u32
2603jme_get_msglevel(struct net_device *netdev)
2604{
2605 struct jme_adapter *jme = netdev_priv(netdev);
2606 return jme->msg_enable;
2607}
2608
2609static void
2610jme_set_msglevel(struct net_device *netdev, u32 value)
2611{
2612 struct jme_adapter *jme = netdev_priv(netdev);
2613 jme->msg_enable = value;
2614}
2615
2616static u32
2617jme_get_rx_csum(struct net_device *netdev)
2618{
2619 struct jme_adapter *jme = netdev_priv(netdev);
2620 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2621}
2622
2623static int
2624jme_set_rx_csum(struct net_device *netdev, u32 on)
2625{
2626 struct jme_adapter *jme = netdev_priv(netdev);
2627
2628 spin_lock_bh(&jme->rxmcs_lock);
2629 if (on)
2630 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2631 else
2632 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2633 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2634 spin_unlock_bh(&jme->rxmcs_lock);
2635
2636 return 0;
2637}
2638
2639static int
2640jme_set_tx_csum(struct net_device *netdev, u32 on)
2641{
2642 struct jme_adapter *jme = netdev_priv(netdev);
2643
2644 if (on) {
2645 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2646 if (netdev->mtu <= 1900)
2647 netdev->features |=
2648 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2649 } else {
2650 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2651 netdev->features &=
2652 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2653 }
2654
2655 return 0;
2656}
2657
2658static int
2659jme_set_tso(struct net_device *netdev, u32 on)
2660{
2661 struct jme_adapter *jme = netdev_priv(netdev);
2662
2663 if (on) {
2664 set_bit(JME_FLAG_TSO, &jme->flags);
2665 if (netdev->mtu <= 1900)
2666 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2667 } else {
2668 clear_bit(JME_FLAG_TSO, &jme->flags);
2669 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2670 }
2671
2672 return 0;
2673}
2674
2675static int
2676jme_nway_reset(struct net_device *netdev)
2677{
2678 struct jme_adapter *jme = netdev_priv(netdev);
2679 jme_restart_an(jme);
2680 return 0;
2681}
2682
2683static u8
2684jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2685{
2686 u32 val;
2687 int to;
2688
2689 val = jread32(jme, JME_SMBCSR);
2690 to = JME_SMB_BUSY_TIMEOUT;
2691 while ((val & SMBCSR_BUSY) && --to) {
2692 msleep(1);
2693 val = jread32(jme, JME_SMBCSR);
2694 }
2695 if (!to) {
2696 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2697 return 0xFF;
2698 }
2699
2700 jwrite32(jme, JME_SMBINTF,
2701 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2702 SMBINTF_HWRWN_READ |
2703 SMBINTF_HWCMD);
2704
2705 val = jread32(jme, JME_SMBINTF);
2706 to = JME_SMB_BUSY_TIMEOUT;
2707 while ((val & SMBINTF_HWCMD) && --to) {
2708 msleep(1);
2709 val = jread32(jme, JME_SMBINTF);
2710 }
2711 if (!to) {
2712 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2713 return 0xFF;
2714 }
2715
2716 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2717}
2718
2719static void
2720jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2721{
2722 u32 val;
2723 int to;
2724
2725 val = jread32(jme, JME_SMBCSR);
2726 to = JME_SMB_BUSY_TIMEOUT;
2727 while ((val & SMBCSR_BUSY) && --to) {
2728 msleep(1);
2729 val = jread32(jme, JME_SMBCSR);
2730 }
2731 if (!to) {
2732 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2733 return;
2734 }
2735
2736 jwrite32(jme, JME_SMBINTF,
2737 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2738 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2739 SMBINTF_HWRWN_WRITE |
2740 SMBINTF_HWCMD);
2741
2742 val = jread32(jme, JME_SMBINTF);
2743 to = JME_SMB_BUSY_TIMEOUT;
2744 while ((val & SMBINTF_HWCMD) && --to) {
2745 msleep(1);
2746 val = jread32(jme, JME_SMBINTF);
2747 }
2748 if (!to) {
2749 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2750 return;
2751 }
2752
2753 mdelay(2);
2754}
2755
2756static int
2757jme_get_eeprom_len(struct net_device *netdev)
2758{
2759 struct jme_adapter *jme = netdev_priv(netdev);
2760 u32 val;
2761 val = jread32(jme, JME_SMBCSR);
2762 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2763}
2764
2765static int
2766jme_get_eeprom(struct net_device *netdev,
2767 struct ethtool_eeprom *eeprom, u8 *data)
2768{
2769 struct jme_adapter *jme = netdev_priv(netdev);
2770 int i, offset = eeprom->offset, len = eeprom->len;
2771
2772 /*
2773 * ethtool will check the boundary for us
2774 */
2775 eeprom->magic = JME_EEPROM_MAGIC;
2776 for (i = 0 ; i < len ; ++i)
2777 data[i] = jme_smb_read(jme, i + offset);
2778
2779 return 0;
2780}
2781
2782static int
2783jme_set_eeprom(struct net_device *netdev,
2784 struct ethtool_eeprom *eeprom, u8 *data)
2785{
2786 struct jme_adapter *jme = netdev_priv(netdev);
2787 int i, offset = eeprom->offset, len = eeprom->len;
2788
2789 if (eeprom->magic != JME_EEPROM_MAGIC)
2790 return -EINVAL;
2791
2792 /*
2793 * ethtool will check the boundary for us
2794 */
2795 for (i = 0 ; i < len ; ++i)
2796 jme_smb_write(jme, i + offset, data[i]);
2797
2798 return 0;
2799}
2800
2801#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2802static struct ethtool_ops jme_ethtool_ops = {
2803#else
2804static const struct ethtool_ops jme_ethtool_ops = {
2805#endif
2806 .get_drvinfo = jme_get_drvinfo,
2807 .get_regs_len = jme_get_regs_len,
2808 .get_regs = jme_get_regs,
2809 .get_coalesce = jme_get_coalesce,
2810 .set_coalesce = jme_set_coalesce,
2811 .get_pauseparam = jme_get_pauseparam,
2812 .set_pauseparam = jme_set_pauseparam,
2813 .get_wol = jme_get_wol,
2814 .set_wol = jme_set_wol,
2815 .get_settings = jme_get_settings,
2816 .set_settings = jme_set_settings,
2817 .get_link = jme_get_link,
2818 .get_msglevel = jme_get_msglevel,
2819 .set_msglevel = jme_set_msglevel,
2820 .get_rx_csum = jme_get_rx_csum,
2821 .set_rx_csum = jme_set_rx_csum,
2822 .set_tx_csum = jme_set_tx_csum,
2823 .set_tso = jme_set_tso,
2824 .set_sg = ethtool_op_set_sg,
2825 .nway_reset = jme_nway_reset,
2826 .get_eeprom_len = jme_get_eeprom_len,
2827 .get_eeprom = jme_get_eeprom,
2828 .set_eeprom = jme_set_eeprom,
2829};
2830
2831static int
2832jme_pci_dma64(struct pci_dev *pdev)
2833{
2834 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2835#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2836 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2837#else
2838 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2839#endif
2840 )
2841#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2842 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2843#else
2844 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2845#endif
2846 return 1;
2847
2848 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2849#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2850 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2851#else
2852 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2853#endif
2854 )
2855#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2856 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2857#else
2858 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2859#endif
2860 return 1;
2861
2862#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2863 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2864 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2865#else
2866 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2867 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2868#endif
2869 return 0;
2870
2871 return -1;
2872}
2873
2874static inline void
2875jme_phy_init(struct jme_adapter *jme)
2876{
2877 u16 reg26;
2878
2879 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2880 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2881}
2882
2883static inline void
2884jme_check_hw_ver(struct jme_adapter *jme)
2885{
2886 u32 chipmode;
2887
2888 chipmode = jread32(jme, JME_CHIPMODE);
2889
2890 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2891 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2892 jme->chip_main_rev = jme->chiprev & 0xF;
2893 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2894}
2895
2896#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2897static const struct net_device_ops jme_netdev_ops = {
2898 .ndo_open = jme_open,
2899 .ndo_stop = jme_close,
2900 .ndo_validate_addr = eth_validate_addr,
2901 .ndo_do_ioctl = jme_ioctl,
2902 .ndo_start_xmit = jme_start_xmit,
2903 .ndo_set_mac_address = jme_set_macaddr,
2904 .ndo_set_multicast_list = jme_set_multi,
2905 .ndo_change_mtu = jme_change_mtu,
2906 .ndo_tx_timeout = jme_tx_timeout,
2907 .ndo_vlan_rx_register = jme_vlan_rx_register,
2908};
2909#endif
2910
2911static int __devinit
2912jme_init_one(struct pci_dev *pdev,
2913 const struct pci_device_id *ent)
2914{
2915 int rc = 0, using_dac, i;
2916 struct net_device *netdev;
2917 struct jme_adapter *jme;
2918 u16 bmcr, bmsr;
2919 u32 apmc;
2920
2921 /*
2922 * set up PCI device basics
2923 */
2924 rc = pci_enable_device(pdev);
2925 if (rc) {
2926 pr_err("Cannot enable PCI device\n");
2927 goto err_out;
2928 }
2929
2930 using_dac = jme_pci_dma64(pdev);
2931 if (using_dac < 0) {
2932 pr_err("Cannot set PCI DMA Mask\n");
2933 rc = -EIO;
2934 goto err_out_disable_pdev;
2935 }
2936
2937 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2938 pr_err("No PCI resource region found\n");
2939 rc = -ENOMEM;
2940 goto err_out_disable_pdev;
2941 }
2942
2943 rc = pci_request_regions(pdev, DRV_NAME);
2944 if (rc) {
2945 pr_err("Cannot obtain PCI resource region\n");
2946 goto err_out_disable_pdev;
2947 }
2948
2949 pci_set_master(pdev);
2950
2951 /*
2952 * alloc and init net device
2953 */
2954 netdev = alloc_etherdev(sizeof(*jme));
2955 if (!netdev) {
2956 pr_err("Cannot allocate netdev structure\n");
2957 rc = -ENOMEM;
2958 goto err_out_release_regions;
2959 }
2960#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2961 netdev->netdev_ops = &jme_netdev_ops;
2962#else
2963 netdev->open = jme_open;
2964 netdev->stop = jme_close;
2965 netdev->do_ioctl = jme_ioctl;
2966 netdev->hard_start_xmit = jme_start_xmit;
2967 netdev->set_mac_address = jme_set_macaddr;
2968 netdev->set_multicast_list = jme_set_multi;
2969 netdev->change_mtu = jme_change_mtu;
2970 netdev->tx_timeout = jme_tx_timeout;
2971 netdev->vlan_rx_register = jme_vlan_rx_register;
2972#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2973 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
2974#endif
2975 NETDEV_GET_STATS(netdev, &jme_get_stats);
2976#endif
2977 netdev->ethtool_ops = &jme_ethtool_ops;
2978 netdev->watchdog_timeo = TX_TIMEOUT;
2979 netdev->features = NETIF_F_IP_CSUM |
2980 NETIF_F_IPV6_CSUM |
2981 NETIF_F_SG |
2982 NETIF_F_TSO |
2983 NETIF_F_TSO6 |
2984 NETIF_F_HW_VLAN_TX |
2985 NETIF_F_HW_VLAN_RX;
2986 if (using_dac)
2987 netdev->features |= NETIF_F_HIGHDMA;
2988
2989 SET_NETDEV_DEV(netdev, &pdev->dev);
2990 pci_set_drvdata(pdev, netdev);
2991
2992 /*
2993 * init adapter info
2994 */
2995 jme = netdev_priv(netdev);
2996 jme->pdev = pdev;
2997 jme->dev = netdev;
2998 jme->jme_rx = netif_rx;
2999 jme->jme_vlan_rx = vlan_hwaccel_rx;
3000 jme->old_mtu = netdev->mtu = 1500;
3001 jme->phylink = 0;
3002 jme->tx_ring_size = 1 << 10;
3003 jme->tx_ring_mask = jme->tx_ring_size - 1;
3004 jme->tx_wake_threshold = 1 << 9;
3005 jme->rx_ring_size = 1 << 9;
3006 jme->rx_ring_mask = jme->rx_ring_size - 1;
3007 jme->msg_enable = JME_DEF_MSG_ENABLE;
3008 jme->regs = ioremap(pci_resource_start(pdev, 0),
3009 pci_resource_len(pdev, 0));
3010 if (!(jme->regs)) {
3011 pr_err("Mapping PCI resource region error\n");
3012 rc = -ENOMEM;
3013 goto err_out_free_netdev;
3014 }
3015
3016 if (no_pseudohp) {
3017 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3018 jwrite32(jme, JME_APMC, apmc);
3019 } else if (force_pseudohp) {
3020 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3021 jwrite32(jme, JME_APMC, apmc);
3022 }
3023
3024 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3025
3026 spin_lock_init(&jme->phy_lock);
3027 spin_lock_init(&jme->macaddr_lock);
3028 spin_lock_init(&jme->rxmcs_lock);
3029
3030 atomic_set(&jme->link_changing, 1);
3031 atomic_set(&jme->rx_cleaning, 1);
3032 atomic_set(&jme->tx_cleaning, 1);
3033 atomic_set(&jme->rx_empty, 1);
3034
3035 tasklet_init(&jme->pcc_task,
3036 jme_pcc_tasklet,
3037 (unsigned long) jme);
3038 tasklet_init(&jme->linkch_task,
3039 jme_link_change_tasklet,
3040 (unsigned long) jme);
3041 tasklet_init(&jme->txclean_task,
3042 jme_tx_clean_tasklet,
3043 (unsigned long) jme);
3044 tasklet_init(&jme->rxclean_task,
3045 jme_rx_clean_tasklet,
3046 (unsigned long) jme);
3047 tasklet_init(&jme->rxempty_task,
3048 jme_rx_empty_tasklet,
3049 (unsigned long) jme);
3050 tasklet_disable_nosync(&jme->linkch_task);
3051 tasklet_disable_nosync(&jme->txclean_task);
3052 tasklet_disable_nosync(&jme->rxclean_task);
3053 tasklet_disable_nosync(&jme->rxempty_task);
3054 jme->dpi.cur = PCC_P1;
3055
3056 jme->reg_ghc = 0;
3057 jme->reg_rxcs = RXCS_DEFAULT;
3058 jme->reg_rxmcs = RXMCS_DEFAULT;
3059 jme->reg_txpfc = 0;
3060 jme->reg_pmcs = PMCS_MFEN;
3061 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3062 set_bit(JME_FLAG_TSO, &jme->flags);
3063
3064 /*
3065 * Get Max Read Req Size from PCI Config Space
3066 */
3067 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3068 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3069 switch (jme->mrrs) {
3070 case MRRS_128B:
3071 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3072 break;
3073 case MRRS_256B:
3074 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3075 break;
3076 default:
3077 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3078 break;
3079 }
3080
3081 /*
3082 * Must check before reset_mac_processor
3083 */
3084 jme_check_hw_ver(jme);
3085 jme->mii_if.dev = netdev;
3086 if (jme->fpgaver) {
3087 jme->mii_if.phy_id = 0;
3088 for (i = 1 ; i < 32 ; ++i) {
3089 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3090 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3091 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3092 jme->mii_if.phy_id = i;
3093 break;
3094 }
3095 }
3096
3097 if (!jme->mii_if.phy_id) {
3098 rc = -EIO;
3099 pr_err("Can not find phy_id\n");
3100 goto err_out_unmap;
3101 }
3102
3103 jme->reg_ghc |= GHC_LINK_POLL;
3104 } else {
3105 jme->mii_if.phy_id = 1;
3106 }
3107 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3108 jme->mii_if.supports_gmii = true;
3109 else
3110 jme->mii_if.supports_gmii = false;
3111 jme->mii_if.phy_id_mask = 0x1F;
3112 jme->mii_if.reg_num_mask = 0x1F;
3113 jme->mii_if.mdio_read = jme_mdio_read;
3114 jme->mii_if.mdio_write = jme_mdio_write;
3115
3116 jme_clear_pm(jme);
3117 jme_set_phyfifo_5level(jme);
3118 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3119 if (!jme->fpgaver)
3120 jme_phy_init(jme);
3121 jme_phy_off(jme);
3122
3123 /*
3124 * Reset MAC processor and reload EEPROM for MAC Address
3125 */
3126 jme_reset_mac_processor(jme);
3127 rc = jme_reload_eeprom(jme);
3128 if (rc) {
3129 pr_err("Reload eeprom for reading MAC Address error\n");
3130 goto err_out_unmap;
3131 }
3132 jme_load_macaddr(netdev);
3133
3134 /*
3135 * Tell stack that we are not ready to work until open()
3136 */
3137 netif_carrier_off(netdev);
3138
3139 rc = register_netdev(netdev);
3140 if (rc) {
3141 pr_err("Cannot register net device\n");
3142 goto err_out_unmap;
3143 }
3144
3145 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3146 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3147 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3148 "JMC250 Gigabit Ethernet" :
3149 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3150 "JMC260 Fast Ethernet" : "Unknown",
3151 (jme->fpgaver != 0) ? " (FPGA)" : "",
3152 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3153 jme->pcirev,
3154 netdev->dev_addr[0],
3155 netdev->dev_addr[1],
3156 netdev->dev_addr[2],
3157 netdev->dev_addr[3],
3158 netdev->dev_addr[4],
3159 netdev->dev_addr[5]);
3160
3161 return 0;
3162
3163err_out_unmap:
3164 iounmap(jme->regs);
3165err_out_free_netdev:
3166 pci_set_drvdata(pdev, NULL);
3167 free_netdev(netdev);
3168err_out_release_regions:
3169 pci_release_regions(pdev);
3170err_out_disable_pdev:
3171 pci_disable_device(pdev);
3172err_out:
3173 return rc;
3174}
3175
3176static void __devexit
3177jme_remove_one(struct pci_dev *pdev)
3178{
3179 struct net_device *netdev = pci_get_drvdata(pdev);
3180 struct jme_adapter *jme = netdev_priv(netdev);
3181
3182 unregister_netdev(netdev);
3183 iounmap(jme->regs);
3184 pci_set_drvdata(pdev, NULL);
3185 free_netdev(netdev);
3186 pci_release_regions(pdev);
3187 pci_disable_device(pdev);
3188
3189}
3190
3191static void
3192jme_shutdown(struct pci_dev *pdev)
3193{
3194 struct net_device *netdev = pci_get_drvdata(pdev);
3195 struct jme_adapter *jme = netdev_priv(netdev);
3196
3197 jme_powersave_phy(jme);
3198#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3199 pci_enable_wake(pdev, PCI_D3hot, true);
3200#else
3201 pci_pme_active(pdev, true);
3202#endif
3203}
3204
3205#ifdef CONFIG_PM
3206static int
3207jme_suspend(struct pci_dev *pdev, pm_message_t state)
3208{
3209 struct net_device *netdev = pci_get_drvdata(pdev);
3210 struct jme_adapter *jme = netdev_priv(netdev);
3211
3212 atomic_dec(&jme->link_changing);
3213
3214 netif_device_detach(netdev);
3215 netif_stop_queue(netdev);
3216 jme_stop_irq(jme);
3217
3218 tasklet_disable(&jme->txclean_task);
3219 tasklet_disable(&jme->rxclean_task);
3220 tasklet_disable(&jme->rxempty_task);
3221
3222 if (netif_carrier_ok(netdev)) {
3223 if (test_bit(JME_FLAG_POLL, &jme->flags))
3224 jme_polling_mode(jme);
3225
3226 jme_stop_pcc_timer(jme);
3227 jme_reset_ghc_speed(jme);
3228 jme_disable_rx_engine(jme);
3229 jme_disable_tx_engine(jme);
3230 jme_reset_mac_processor(jme);
3231 jme_free_rx_resources(jme);
3232 jme_free_tx_resources(jme);
3233 netif_carrier_off(netdev);
3234 jme->phylink = 0;
3235 }
3236
3237 tasklet_enable(&jme->txclean_task);
3238 tasklet_hi_enable(&jme->rxclean_task);
3239 tasklet_hi_enable(&jme->rxempty_task);
3240
3241 pci_save_state(pdev);
3242 jme_powersave_phy(jme);
3243 pci_enable_wake(pdev, PCI_D3hot, true);
3244 pci_set_power_state(pdev, PCI_D3hot);
3245
3246 return 0;
3247}
3248
3249static int
3250jme_resume(struct pci_dev *pdev)
3251{
3252 struct net_device *netdev = pci_get_drvdata(pdev);
3253 struct jme_adapter *jme = netdev_priv(netdev);
3254
3255 jme_clear_pm(jme);
3256 pci_restore_state(pdev);
3257
3258 jme_phy_on(jme);
3259 if (test_bit(JME_FLAG_SSET, &jme->flags))
3260 jme_set_settings(netdev, &jme->old_ecmd);
3261 else
3262 jme_reset_phy_processor(jme);
3263
3264 jme_start_irq(jme);
3265 netif_device_attach(netdev);
3266
3267 atomic_inc(&jme->link_changing);
3268
3269 jme_reset_link(jme);
3270
3271 return 0;
3272}
3273#endif
3274
3275#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3276static struct pci_device_id jme_pci_tbl[] = {
3277#else
3278static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3279#endif
3280 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3281 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3282 { }
3283};
3284
3285static struct pci_driver jme_driver = {
3286 .name = DRV_NAME,
3287 .id_table = jme_pci_tbl,
3288 .probe = jme_init_one,
3289 .remove = __devexit_p(jme_remove_one),
3290#ifdef CONFIG_PM
3291 .suspend = jme_suspend,
3292 .resume = jme_resume,
3293#endif /* CONFIG_PM */
3294 .shutdown = jme_shutdown,
3295};
3296
3297static int __init
3298jme_init_module(void)
3299{
3300 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3301 return pci_register_driver(&jme_driver);
3302}
3303
3304static void __exit
3305jme_cleanup_module(void)
3306{
3307 pci_unregister_driver(&jme_driver);
3308}
3309
3310module_init(jme_init_module);
3311module_exit(jme_cleanup_module);
3312
3313MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3314MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3315MODULE_LICENSE("GPL");
3316MODULE_VERSION(DRV_VERSION);
3317MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3318
JMicron Ethernet Linux driver